刘子宸
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342549bd5c
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Fixed CLINT address map.
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2026-05-19 22:15:30 +08:00 |
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刘子宸
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9d4bc1e79f
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Added RISC-V A extension.
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2026-05-13 17:22:38 +08:00 |
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刘子宸
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bd51e32487
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Moved `ringbuffer` and `width_t` to namespace `libanemo`.
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2026-04-11 15:22:15 +08:00 |
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刘子宸
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0ff4753ab0
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Added address translation.
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2026-04-09 12:00:09 +08:00 |
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刘子宸
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a336b2d975
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Optimized performance of virtual memory.
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2026-04-04 22:39:22 +08:00 |
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刘子宸
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734f3f16e9
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Changed the memory interface of `abstract_cpu` from `memory` to `memory_view`.
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2025-09-12 13:29:36 +08:00 |
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刘子宸
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25280346db
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`memory_veiw` can have different position mapped to base address with source.
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2025-08-09 00:58:41 +08:00 |
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刘子宸
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04ef9a2276
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Added `memory_view`.
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2025-08-06 01:48:02 +08:00 |
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刘子宸
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1894331c5b
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Addded example for a minimal RISC-V simulator.
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2025-08-04 14:37:08 +08:00 |
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刘子宸
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594b4cb101
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Moved emulator backend to namespace `riscv`.
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2025-08-04 14:22:04 +08:00 |
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刘子宸
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4771a17e11
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Refactored project layout.
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2025-08-03 21:45:14 +08:00 |
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刘子宸
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4878dba4d5
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Staged to new emulator.
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2025-08-03 14:42:25 +08:00 |
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刘子宸
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521794ce51
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RV64IM support.
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2025-08-03 03:10:30 +08:00 |
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刘子宸
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723232645c
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Improved difftest logic.
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2025-08-03 00:41:03 +08:00 |
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刘子宸
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4921bef5dc
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New RISC-V emulator with privileged operation support.
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2025-08-03 00:38:42 +08:00 |
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刘子宸
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69edff820a
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New RISC-V simulator backends.
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2025-08-02 17:14:06 +08:00 |
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刘子宸
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69ae644920
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An unprivileged only RISC-V CPU fast emulator.
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2025-07-30 22:04:14 +08:00 |
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刘子宸
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daf4a0588e
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`simple_difftest` now compares trap events.
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2025-07-24 01:34:51 +08:00 |
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刘子宸
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22805f671d
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Migrate `rv32i_cpu_system` to a subclass of `riscv_cpu<uint32_t>`.
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2025-07-24 01:33:50 +08:00 |
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刘子宸
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55ae688a79
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Fixed display format of `event_t`.
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2025-07-23 22:27:17 +08:00 |
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刘子宸
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30ac32dd8c
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An unprivileged only RISC-V CPU base class.
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2025-07-23 22:26:34 +08:00 |
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刘子宸
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36f73c4cbe
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Fixed mistakes in difftest and the `trace` SDB command.
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2025-07-23 18:44:49 +08:00 |
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刘子宸
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b596e5df5c
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Migrate RISC-V constant definitions to static constexpr members of template structs.
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2025-07-23 13:36:23 +08:00 |
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刘子宸
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b0453f21b2
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`simple_difftest` now copies the trace of the DUT into its buffer.
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2025-07-22 21:28:32 +08:00 |
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刘子宸
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a5864a9939
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New `libvio` interface.
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2025-07-22 04:53:29 +08:00 |
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刘子宸
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da0c8ed576
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Starndard differencial testing interface.
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2025-07-20 01:40:44 +08:00 |
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刘子宸
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5b4ffbb2fd
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Added changes that should have been commited.
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2025-07-20 00:34:56 +08:00 |
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刘子宸
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2003baab28
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SDB expression functions.
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2025-07-20 00:32:07 +08:00 |
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刘子宸
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287b319697
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Cache interface
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2025-07-12 16:42:12 +08:00 |
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刘子宸
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0be3aa68ce
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New memory interface
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2025-07-12 16:04:36 +08:00 |
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刘子宸
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58c4f3573c
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RV64I realated definitions
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2025-07-11 23:34:22 +08:00 |
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刘子宸
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b0dbd415b3
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API change
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2025-07-11 23:32:58 +08:00 |
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刘子宸
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91ae75611f
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API change
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2025-07-02 23:03:53 +08:00 |
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刘子宸
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20f0ce4535
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Added API stopped
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2025-07-01 01:14:41 +08:00 |
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刘子宸
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e3b0c83bd1
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Refactor RV32I to new interface
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2025-06-30 22:46:44 +08:00 |
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刘子宸
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0c4576b5ec
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unified cpu interface
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2025-06-30 22:45:46 +08:00 |
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刘子宸
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5dbc788a59
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unified memory interface
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2025-06-30 22:44:57 +08:00 |
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刘子宸
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e810bc6ce0
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fixd initialization
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2025-03-29 11:02:21 +08:00 |
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刘子宸
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216591ffbb
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difftest support
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2025-03-28 18:03:53 +08:00 |
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刘子宸
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6b3df62d99
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riscv32_cpu_nemu is a subclass of riscv32_cpu
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2025-03-28 11:16:23 +08:00 |
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刘子宸
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b6ce1d42b1
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Port emulator from NEMU
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2025-03-27 15:02:37 +08:00 |