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  • c29f51b6e2 Added gdb server. main 刘子宸 2026-05-20 15:57:53 +0800
  • 342549bd5c Fixed CLINT address map. 刘子宸 2026-05-19 22:15:30 +0800
  • dcca687395 Added log interface. 刘子宸 2026-05-19 18:17:56 +0800
  • b851d99598 Added PTY ioflow backend. 刘子宸 2026-05-14 14:02:42 +0800
  • 9d4bc1e79f Added RISC-V A extension. 刘子宸 2026-05-13 17:22:38 +0800
  • 2b1b429bd6 Added virtual peripheral UART Lite and CLINT. 刘子宸 2026-05-11 19:40:58 +0800
  • 8549c5b373 New IO backend interface. 刘子宸 2026-05-09 20:06:16 +0800
  • 6b423fab0c Changed `ringbuffer` so its capacity can only be powers of 2. 刘子宸 2026-04-11 17:23:06 +0800
  • bd51e32487 Moved `ringbuffer` and `width_t` to namespace `libanemo`. 刘子宸 2026-04-11 15:22:15 +0800
  • 0ff4753ab0 Added address translation. 刘子宸 2026-04-09 12:00:09 +0800
  • a336b2d975 Optimized performance of virtual memory. 刘子宸 2026-04-04 22:39:22 +0800
  • 734f3f16e9 Changed the memory interface of `abstract_cpu` from `memory` to `memory_view`. 刘子宸 2025-09-12 13:29:36 +0800
  • 25280346db `memory_veiw` can have different position mapped to base address with source. 刘子宸 2025-08-09 00:58:41 +0800
  • 04ef9a2276 Added `memory_view`. 刘子宸 2025-08-06 01:48:02 +0800
  • 1894331c5b Addded example for a minimal RISC-V simulator. 刘子宸 2025-08-04 14:37:08 +0800
  • 594b4cb101 Moved emulator backend to namespace `riscv`. 刘子宸 2025-08-04 14:22:04 +0800
  • 4771a17e11 Refactored project layout. 刘子宸 2025-08-03 21:45:14 +0800
  • 4878dba4d5 Staged to new emulator. 刘子宸 2025-08-03 14:42:25 +0800
  • 521794ce51 RV64IM support. 刘子宸 2025-08-03 03:10:30 +0800
  • 723232645c Improved difftest logic. 刘子宸 2025-08-03 00:41:03 +0800
  • 4921bef5dc New RISC-V emulator with privileged operation support. 刘子宸 2025-08-03 00:38:42 +0800
  • ba585249ab Specialize SDB for difftest. 刘子宸 2025-08-02 17:14:37 +0800
  • 69edff820a New RISC-V simulator backends. 刘子宸 2025-08-02 17:14:06 +0800
  • 69ae644920 An unprivileged only RISC-V CPU fast emulator. 刘子宸 2025-07-30 22:04:14 +0800
  • 4a742b5420 Renamed source file. 刘子宸 2025-07-24 13:57:14 +0800
  • daf4a0588e `simple_difftest` now compares trap events. 刘子宸 2025-07-24 01:34:51 +0800
  • 22805f671d Migrate `rv32i_cpu_system` to a subclass of `riscv_cpu<uint32_t>`. 刘子宸 2025-07-24 01:33:50 +0800
  • 55ae688a79 Fixed display format of `event_t`. 刘子宸 2025-07-23 22:27:17 +0800
  • 30ac32dd8c An unprivileged only RISC-V CPU base class. 刘子宸 2025-07-23 22:26:34 +0800
  • 36f73c4cbe Fixed mistakes in difftest and the `trace` SDB command. 刘子宸 2025-07-23 18:44:49 +0800
  • b596e5df5c Migrate RISC-V constant definitions to static constexpr members of template structs. 刘子宸 2025-07-23 13:36:23 +0800
  • 385b84df89 中文文档 v1.0.0-rc1 刘子宸 2025-07-22 22:55:17 +0800
  • 5e3a189593 Fixed errors in README. 刘子宸 2025-07-22 22:18:01 +0800
  • 182c942a11 Update README to be aligned with new `libvio` API 刘子宸 2025-07-22 21:43:25 +0800
  • b0453f21b2 `simple_difftest` now copies the trace of the DUT into its buffer. 刘子宸 2025-07-22 21:28:32 +0800
  • 4d53e053b6 SDB command `trace`. 刘子宸 2025-07-22 11:26:33 +0800
  • 7fe30f62f2 Random access iterator for ringbuffer. 刘子宸 2025-07-22 04:54:21 +0800
  • a5864a9939 New `libvio` interface. 刘子宸 2025-07-22 04:53:29 +0800
  • 7b4413d32c Fixed compiling error on Windows venti 2025-07-20 20:50:44 +0800
  • 388f268d0f Added README 刘子宸 2025-07-20 18:32:17 +0800
  • b1eeb9d16d SDB commandline interface 刘子宸 2025-07-20 17:29:53 +0800
  • c7f48f9944 Fixed compiling error in MSVC. 刘子宸 2025-07-20 01:41:28 +0800
  • da0c8ed576 Starndard differencial testing interface. 刘子宸 2025-07-20 01:40:44 +0800
  • 5b4ffbb2fd Added changes that should have been commited. 刘子宸 2025-07-20 00:34:56 +0800
  • 2003baab28 SDB expression functions. 刘子宸 2025-07-20 00:32:07 +0800
  • 77464aaf38 MMIO bus implement 刘子宸 2025-07-13 11:26:25 +0800
  • 771f870627 MMIO mtime implement 刘子宸 2025-07-13 11:25:55 +0800
  • 309a0ffab2 MMIO console implement 刘子宸 2025-07-13 11:25:14 +0800
  • 1b001a4a09 base `libvio::frontend` implement 刘子宸 2025-07-13 11:22:11 +0800
  • f9c409341e `libvio` bus interface API freeze 刘子宸 2025-07-13 11:13:55 +0800
  • fe0c909db4 `libvio` frontend and backend API freeze 刘子宸 2025-07-13 05:15:17 +0800
  • a22ae48657 Added `libvio` as part of project 刘子宸 2025-07-13 05:14:44 +0800
  • 287b319697 Cache interface 刘子宸 2025-07-12 16:42:12 +0800
  • 0be3aa68ce New memory interface 刘子宸 2025-07-12 16:04:36 +0800
  • 023d5b5280 Project layout change 刘子宸 2025-07-12 00:18:35 +0800
  • 58c4f3573c RV64I realated definitions 刘子宸 2025-07-11 23:34:22 +0800
  • b0dbd415b3 API change 刘子宸 2025-07-11 23:32:58 +0800
  • 91ae75611f API change 刘子宸 2025-07-02 23:03:53 +0800
  • 20f0ce4535 Added API stopped 刘子宸 2025-07-01 01:14:41 +0800
  • e3b0c83bd1 Refactor RV32I to new interface 刘子宸 2025-06-30 22:46:44 +0800
  • 0c4576b5ec unified cpu interface 刘子宸 2025-06-30 22:45:46 +0800
  • 5dbc788a59 unified memory interface 刘子宸 2025-06-30 22:44:57 +0800
  • 382151d278 refactor project structure 刘子宸 2025-06-30 22:44:35 +0800
  • 1d22e78df3 add LICENSE 刘子宸 2025-03-29 11:02:37 +0800
  • e810bc6ce0 fixd initialization 刘子宸 2025-03-29 11:02:21 +0800
  • 216591ffbb difftest support 刘子宸 2025-03-28 18:03:53 +0800
  • 6b3df62d99 riscv32_cpu_nemu is a subclass of riscv32_cpu 刘子宸 2025-03-28 11:16:23 +0800
  • b6ce1d42b1 Port emulator from NEMU 刘子宸 2025-03-27 15:02:37 +0800