Brainfsck Interpreter in Chisel

This project implements a Brainfsck interpreter in Chisel with multiple simulation and hardware targets.

Project Structure

• src/main/scala: Chisel source code
  • Brainfsck.scala: Main Brainfsck interpreter core
  • DataMem.scala: Data memory implementation
  • SimulatedRom.scala: ROM for storing Brainfsck programs
  • UartRx.scala/UartTx.scala: UART transmitter/receiver
  • CrossBuffer.scala: Cross-domain buffer
  • PassthroughBuffer.scala: Passthrough buffer implementation
  • RandomDelay.scala: Random delay module for testing
  • FpgaTop.scala: Top-level module for FPGA implementation
  • NvboardTop.scala: Top-level module for NVBoard simulation
  • Simulate.scala: Simulation testbench
• src/main/cc: C++ source for NVBoard integration
• src/main/bf: Brainfsck example programs
• src/test/scala: Test suites

Targets

1. Simulation Target (SimulateTop)

Run simulation:

sbt "runMain brainfsck.Simulate"

2. FPGA Target (FpgaTop)

Generate Verilog for FPGA synthesis:

sbt "runMain brainfsck.FpgaTop"

This will:

• Generate SystemVerilog files in target/src/main/sv/
• Create memory initialization files in target/src/main/mi/

3. NVBoard Target (NvboardTop)

Generate Verilog for NVBoard simulation:

sbt "runMain brainfsck.NvboardTop"

This generates SystemVerilog files in target/src/main/sv/

NVBoard Integration

The project includes a C++ main file (src/main/cc/main.cc) for NVBoard integration. To use with NVBoard:

1. Generate the Verilog using the NVBoard target
2. Write a Makefile that:
   • Compiles the Verilog code with Verilator
   • Links with the NVBoard library
   • Uses the provided main.cc file for pin binding and simulation

The main.cc file handles:

• Pin binding for UART interface
• Clock and reset generation
• NVBoard initialization and update

Brainfsck Programs

The project includes several example programs:

• tolower.bf: Converts input to lowercase
• repeat.bf: Repeats one sentence based on user choice
• hello.bf: Hello world program

Testing

Run the test suites with:

sbt test

Tests cover:

• Data memory functionality
• Random delay module behavior
• Passthrough buffer correctness