331 lines
19 KiB
YAML
331 lines
19 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
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--- |
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; ModuleID = 'skip-vpt-debug.ll'
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source_filename = "skip-vpt-debug.c"
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-arm-none-eabihf"
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; Function Attrs: nofree norecurse nounwind optsize
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define hidden void @arm_max_no_idx_f32(float* nocapture readonly %pSrc, i32 %blockSize, float* nocapture %pResult) local_unnamed_addr #0 !dbg !13 {
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entry:
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call void @llvm.dbg.value(metadata float* %pSrc, metadata !24, metadata !DIExpression()), !dbg !29
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call void @llvm.dbg.value(metadata i32 %blockSize, metadata !25, metadata !DIExpression()), !dbg !29
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call void @llvm.dbg.value(metadata float* %pResult, metadata !26, metadata !DIExpression()), !dbg !29
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call void @llvm.dbg.value(metadata float 0x3810000000000000, metadata !27, metadata !DIExpression()), !dbg !29
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%cmp.not7 = icmp eq i32 %blockSize, 0, !dbg !30
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br i1 %cmp.not7, label %while.end, label %vector.ph, !dbg !31
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %blockSize, 3, !dbg !31
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%n.vec = and i32 %n.rnd.up, -4, !dbg !31
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%0 = add i32 %n.vec, -4, !dbg !31
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%1 = lshr i32 %0, 2, !dbg !31
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%2 = add nuw nsw i32 %1, 1, !dbg !31
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%3 = call i32 @llvm.start.loop.iterations.i32(i32 %2), !dbg !31
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br label %vector.body, !dbg !31
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv1 = phi float* [ %scevgep, %vector.body ], [ %pSrc, %vector.ph ]
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%vec.phi = phi <4 x float> [ <float 0x3810000000000000, float 0x3810000000000000, float 0x3810000000000000, float 0x3810000000000000>, %vector.ph ], [ %10, %vector.body ]
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%4 = phi i32 [ %3, %vector.ph ], [ %11, %vector.body ]
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%5 = phi i32 [ %blockSize, %vector.ph ], [ %7, %vector.body ]
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%lsr.iv12 = bitcast float* %lsr.iv1 to <4 x float>*
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%6 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %5)
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%7 = sub i32 %5, 4
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%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %lsr.iv12, i32 4, <4 x i1> %6, <4 x float> poison), !dbg !32, !tbaa !34
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%8 = fcmp nnan ninf nsz olt <4 x float> %vec.phi, %wide.masked.load, !dbg !38
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%9 = and <4 x i1> %6, %8, !dbg !40
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%10 = select <4 x i1> %9, <4 x float> %wide.masked.load, <4 x float> %vec.phi, !dbg !40
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%scevgep = getelementptr float, float* %lsr.iv1, i32 4
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%11 = call i32 @llvm.loop.decrement.reg.i32(i32 %4, i32 1)
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%12 = icmp ne i32 %11, 0
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br i1 %12, label %vector.body, label %middle.block, !llvm.loop !41
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middle.block: ; preds = %vector.body
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%13 = call nnan ninf nsz float @llvm.vector.reduce.fmax.v4f32(<4 x float> %10), !dbg !31
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br label %while.end, !dbg !45
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while.end: ; preds = %middle.block, %entry
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%maxValue.0.lcssa = phi float [ 0x3810000000000000, %entry ], [ %13, %middle.block ], !dbg !29
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store float %maxValue.0.lcssa, float* %pResult, align 4, !dbg !45, !tbaa !34
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ret void, !dbg !46
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}
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; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
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declare void @llvm.dbg.value(metadata, metadata, metadata) #1
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; Function Attrs: nofree nosync nounwind readnone willreturn
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declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #2
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; Function Attrs: argmemonly nofree nosync nounwind readonly willreturn
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declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #3
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; Function Attrs: nofree nosync nounwind readnone willreturn
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declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>) #2
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; Function Attrs: noduplicate nofree nosync nounwind willreturn
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declare i32 @llvm.start.loop.iterations.i32(i32) #4
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; Function Attrs: noduplicate nofree nosync nounwind willreturn
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declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #4
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; Function Attrs: nounwind readnone
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declare <4 x i1> @llvm.arm.mve.vctp32(i32) #5
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attributes #0 = { nofree norecurse nounwind optsize "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-dotprod,-fp16fml,-hwdiv-arm,-i8mm,-sb,-sha2" }
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attributes #1 = { nofree nosync nounwind readnone speculatable willreturn }
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attributes #2 = { nofree nosync nounwind readnone willreturn }
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attributes #3 = { argmemonly nofree nosync nounwind readonly willreturn }
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attributes #4 = { noduplicate nofree nosync nounwind willreturn }
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attributes #5 = { nounwind readnone }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!3, !4, !5, !6, !7, !8, !9, !10, !11}
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!llvm.ident = !{!12}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "Component: ARM Compiler 6.17.0.0 (permissive) Tool: armclang [00000000]", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
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!1 = !DIFile(filename: "skip-vpt-debug.c", directory: "/home/vicspe01")
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!2 = !{}
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!3 = !{i32 7, !"Dwarf Version", i32 4}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = !{i32 1, !"wchar_size", i32 4}
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!6 = !{i32 1, !"static_rwdata", i32 1}
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!7 = !{i32 1, !"enumsize_buildattr", i32 2}
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!8 = !{i32 1, !"armlib_unavailable", i32 0}
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!9 = !{i32 8, !"branch-target-enforcement", i32 0}
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!10 = !{i32 8, !"sign-return-address", i32 0}
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!11 = !{i32 8, !"sign-return-address-all", i32 0}
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!12 = !{!"Component: ARM Compiler 6.17.0.0 (permissive) Tool: armclang [00000000]"}
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!13 = distinct !DISubprogram(name: "arm_max_no_idx_f32", scope: !1, file: !1, line: 5, type: !14, scopeLine: 6, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !23)
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!14 = !DISubroutineType(types: !15)
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!15 = !{null, !16, !20, !22}
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!16 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !17, size: 32)
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!17 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !18)
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!18 = !DIDerivedType(tag: DW_TAG_typedef, name: "float32_t", file: !1, line: 1, baseType: !19)
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!19 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
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!20 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint32_t", file: !1, line: 2, baseType: !21)
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!21 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
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!22 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !18, size: 32)
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!23 = !{!24, !25, !26, !27, !28}
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!24 = !DILocalVariable(name: "pSrc", arg: 1, scope: !13, file: !1, line: 5, type: !16)
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!25 = !DILocalVariable(name: "blockSize", arg: 2, scope: !13, file: !1, line: 5, type: !20)
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!26 = !DILocalVariable(name: "pResult", arg: 3, scope: !13, file: !1, line: 6, type: !22)
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!27 = !DILocalVariable(name: "maxValue", scope: !13, file: !1, line: 7, type: !18)
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!28 = !DILocalVariable(name: "newVal", scope: !13, file: !1, line: 8, type: !18)
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!29 = !DILocation(line: 0, scope: !13)
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!30 = !DILocation(line: 10, column: 20, scope: !13)
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!31 = !DILocation(line: 10, column: 3, scope: !13)
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!32 = !DILocation(line: 11, column: 14, scope: !33)
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!33 = distinct !DILexicalBlock(scope: !13, file: !1, line: 10, column: 26)
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!34 = !{!35, !35, i64 0}
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!35 = !{!"float", !36, i64 0}
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!36 = !{!"omnipotent char", !37, i64 0}
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!37 = !{!"Simple C/C++ TBAA"}
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!38 = !DILocation(line: 12, column: 18, scope: !39)
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!39 = distinct !DILexicalBlock(scope: !33, file: !1, line: 12, column: 9)
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!40 = !DILocation(line: 12, column: 9, scope: !33)
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!41 = distinct !{!41, !31, !42, !43, !44}
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!42 = !DILocation(line: 15, column: 3, scope: !13)
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!43 = !{!"llvm.loop.mustprogress"}
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!44 = !{!"llvm.loop.isvectorized", i32 1}
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!45 = !DILocation(line: 16, column: 12, scope: !13)
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!46 = !DILocation(line: 17, column: 1, scope: !13)
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...
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---
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name: arm_max_no_idx_f32
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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debugValueSubstitutions: []
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constants:
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- id: 0
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value: float 0x3810000000000000
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alignment: 4
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isTargetSpecific: false
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: arm_max_no_idx_f32
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
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; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
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; CHECK: tCBZ renamable $r1, %bb.4, debug-location !31
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; CHECK: bb.1.vector.ph:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
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; CHECK: renamable $q0 = MVE_VMOVimmi32 1152, 0, $noreg, $noreg, undef renamable $q0
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1, debug-location !31
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; CHECK: bb.2.vector.body (align 4):
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; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK: liveins: $lr, $q0, $r0, $r2
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; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg, debug-location !32 :: (load (s128) from %ir.lsr.iv12, align 4, !tbaa !34)
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; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
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; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr, debug-location !40
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; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0, debug-location !40
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; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
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; CHECK: bb.3.middle.block:
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; CHECK: successors: %bb.5(0x80000000)
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; CHECK: liveins: $q0, $r2
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; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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; CHECK: renamable $s4 = nnan ninf nsz VFP_VMAXNMS renamable $s2, renamable $s3, debug-location !31
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; CHECK: renamable $s0 = nnan ninf nsz VFP_VMAXNMS killed renamable $s0, killed renamable $s1, implicit killed $q0, debug-location !31
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; CHECK: renamable $s0 = nnan ninf nsz VFP_VMAXNMS killed renamable $s0, killed renamable $s4, debug-location !31
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; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
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; CHECK: bb.4:
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; CHECK: successors: %bb.5(0x80000000)
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; CHECK: liveins: $r2
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; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
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; CHECK: renamable $s0 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
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; CHECK: bb.5.while.end:
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; CHECK: liveins: $r2, $s0
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; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
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; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg, debug-location !45 :: (store (s32) into %ir.pResult, !tbaa !34)
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; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, debug-location !46
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; CHECK: bb.6 (align 4):
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; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
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bb.0.entry:
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successors: %bb.4(0x30000000), %bb.1(0x50000000)
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liveins: $r0, $r1, $r2, $r7, $lr
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DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
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DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
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DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
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DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
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DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
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tCBZ renamable $r1, %bb.4, debug-location !31
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bb.1.vector.ph:
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successors: %bb.2(0x80000000)
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liveins: $r0, $r1, $r2
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DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
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DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
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DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
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renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg, debug-location !31
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renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !31
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renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg, debug-location !31
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renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !31
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renamable $q0 = MVE_VMOVimmi32 1152, 0, $noreg, $noreg, undef renamable $q0
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renamable $lr = t2DoLoopStartTP killed renamable $r3, renamable $r1, debug-location !31
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bb.2.vector.body (align 4):
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $lr, $q0, $r0, $r1, $r2
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DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
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DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
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renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
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MVE_VPST 2, implicit $vpr, debug-location !32
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renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg, debug-location !32 :: (load (s128) from %ir.lsr.iv12, align 4, !tbaa !34)
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DBG_VALUE $r0, $noreg, !24, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
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renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr, $noreg, debug-location !40
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renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0, debug-location !40
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renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
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|
DBG_VALUE $r1, $noreg, !25, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
|
|
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14 /* CC::al */, $noreg
|
|
|
|
bb.3.middle.block:
|
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successors: %bb.5(0x80000000)
|
|
liveins: $q0, $r2
|
|
|
|
DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
|
|
DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
|
|
renamable $s4 = nnan ninf nsz VFP_VMAXNMS renamable $s2, renamable $s3, debug-location !31
|
|
renamable $s0 = nnan ninf nsz VFP_VMAXNMS killed renamable $s0, killed renamable $s1, implicit $q0, debug-location !31
|
|
renamable $s0 = nnan ninf nsz VFP_VMAXNMS killed renamable $s0, killed renamable $s4, debug-location !31
|
|
tB %bb.5, 14 /* CC::al */, $noreg
|
|
|
|
bb.4:
|
|
successors: %bb.5(0x80000000)
|
|
liveins: $r2
|
|
|
|
DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
|
|
DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
|
|
DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
|
|
DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
|
|
renamable $s0 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
|
|
|
|
bb.5.while.end:
|
|
liveins: $r2, $s0
|
|
|
|
DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
|
|
DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
|
|
VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg, debug-location !45 :: (store (s32) into %ir.pResult, !tbaa !34)
|
|
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, debug-location !46
|
|
|
|
bb.6 (align 4):
|
|
CONSTPOOL_ENTRY 0, %const.0, 4
|
|
|
|
...
|