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llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops
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Simon Tatham e45cbf9923 [ARM,MVE] Update MVE_VMLA_qr for architecture change. 
In revision B.q and before of the Armv8-M architecture reference
manual, the vector/scalar forms of the `vmla` and `vmlas` instructions
came in signed and unsigned integer forms, such as `vmla.s8 q0,q1,r2`
or `vmlas.u32 q3,q4,r5`.

Revision B.r has changed this. There are no longer signed and unsigned
versions of these instructions, since they were functionally identical
anyway. Now there is just `vmla.i8` (or `i16` or `i32`, and similarly
for `vmlas`). Bit 28 of the instruction encoding, which was previously
0 for signed or 1 for unsigned, is now expected to be 0 always.

This change updates LLVM to the new version of the architecture. The
obsoleted encodings for unsigned integers are now decoding errors, and
only the still-valid encoding is ever emitted. This shouldn't break
any existing assembly code, because the old signed and unsigned
versions of the mnemonic are still accepted by the assembler (which is
standard practice anyway for all signedness-agnostic MVE integer
instructions).

Reviewed By: dmgreen, lenary

Differential Revision: https://reviews.llvm.org/D138827
 		2022-11-29 08:47:00 +00:00
..
add_reduce.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
arm_cmplx_dot_prod_f32.ll [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr 2022-10-01 12:41:37 +03:00
begin-vpt-without-inst.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
biquad-cascade-default.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
biquad-cascade-optsize-strd-lr.mir
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biquad-cascade-optsize.mir
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branch-targets.ll
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clear-maskedinsts.ll
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cmplx_cong.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
cond-mov.mir
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cond-vector-reduce-mve-codegen.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
constbound.ll [CodeGen] Improve SelectionDAGBuilder lowering code for get.active.lane.mask intrinsic 2021-12-10 13:39:38 +00:00
count_dominates_start.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
ctlz-non-zeros.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
disjoint-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
dont-ignore-vctp.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
dont-remove-loop-update.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
emptyblock.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
end-positive-offset.mir
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exitcount.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
extending-loads.ll
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extract-element.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
fast-fp-loops.ll [SCEV] Canonicalize X - urem X, Y patterns 2021-11-16 11:59:21 -08:00
incorrect-sub-8.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
incorrect-sub-16.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
incorrect-sub-32.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inlineasm.ll
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inloop-vpnot-1.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpnot-2.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpnot-3.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpsel-1.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpsel-2.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
invariant-qreg.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-chain-store.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-chain.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
it-block-itercount.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
it-block-mov.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
it-block-random.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
iv-two-vcmp-reordered.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
iv-two-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
iv-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
livereg-no-loop-def.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
loop-dec-copy-chain.mir
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loop-dec-copy-prev-iteration.mir
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loop-dec-liveout.mir
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loop-guards.ll
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lsr-profitable-chain.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
lstp-insertion-position.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
massive.mir
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matrix-debug.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
matrix.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
memcall.ll [MachineCSE] Allow PRE of instructions that read physical registers 2022-11-02 13:53:12 +00:00
minloop.ll
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mov-after-dls.mir
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mov-after-dlstp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mov-lr-terminator.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mov-operand.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
move-def-before-start.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
move-start-after-def.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
multi-block-cond-iter-count.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
multi-cond-iter-count.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
multiblock-massive.mir
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multiple-do-loops.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-float-loops.ll [SCEV] Canonicalize X - urem X, Y patterns 2021-11-16 11:59:21 -08:00
mve-tail-data-types.ll [ARM,MVE] Update MVE_VMLA_qr for architecture change. 2022-11-29 08:47:00 +00:00
nested.ll
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no-dec-cbnz.mir
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no-dec-le-simple.ll
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no-dec-reorder.mir
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no-dec.mir
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no-vpsel-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
non-masked-load.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
non-masked-store.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
out-of-range-cbz.mir
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predicated-invariant.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
predicated-liveout-unknown-lanes.ll
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predicated-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
reductions-vpt-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
reductions.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
remat-vctp.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
remove-elem-moves.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
revert-after-call.mir
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revert-after-read.mir
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revert-after-write.mir
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revert-non-header.mir
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revert-non-loop.mir
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revert-while.mir
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revertcallearly.mir
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safe-def-no-mov.mir
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safe-retaining.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
sibling-loops.ll
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size-limit.mir
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skip-debug.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
skip-vpt-debug.mir Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
spillingmove.ll [ARM,MVE] Update MVE_VMLA_qr for architecture change. 2022-11-29 08:47:00 +00:00
spillingmove.mir [ARM] Introduce a MQPRCopy 2021-10-07 12:52:12 +01:00
subreg-liveness.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
switch.mir
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tail-pred-basic.ll
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tail-pred-const.ll
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tail-pred-disabled-in-loloops.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
tail-pred-intrinsic-add-sat.ll
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tail-pred-intrinsic-fabs.ll
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tail-pred-intrinsic-round.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
tail-pred-intrinsic-sub-sat.ll
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tail-pred-narrow.ll
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tail-pred-pattern-fail.ll
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tail-pred-reduce.ll
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tail-pred-widen.ll
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tp-multiple-vpst.ll
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unpredicated-max.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
unpredload.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
unrolled-and-vector.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
unsafe-cpsr-loop-def.mir
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unsafe-cpsr-loop-use.mir
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unsafe-retaining.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
unsafe-use-after.mir
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vaddv.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
varying-outer-2d-reduction.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
vcmp-vpst-combination-across-blocks.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
vcmp-vpst-combination.ll
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vctp-add-operand-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-in-vpt-2.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-in-vpt.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-subi3.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-subri.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-subri12.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp16-reduce.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vector-arith-codegen.ll
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vector-reduce-mve-tail.ll
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vector-unroll.ll
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vector_spill_in_loop.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vmaxmin_vpred_r.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vmldava_in_vpt.mir [ARM,MVE] Update MVE_VMLA_qr for architecture change. 2022-11-29 08:47:00 +00:00
vpt-block-debug.mir [ARM] Skip debug info in recomputeVPTBlockMask 2021-09-28 14:58:13 +01:00
vpt-blocks.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
while-loops.ll [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. 2022-07-14 16:10:14 -07:00
while-negative-offset.mir
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while.mir
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wls-revert-placement.mir [ARM] Fix subtarget features for Thumb2 tests. NFC 2022-07-13 11:42:21 +01:00
wls-search-killed.mir
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wls-search-pred.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wlstp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wrong-liveout-lsr-shift.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wrong-vctp-opcode-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wrong-vctp-operand-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00