llvm-project/llvm/test/CodeGen/MIR/AMDGPU
Nicolai Hähnle b7f44f7cf9 AMDGPU: Remove ImagePSV and move images to addrspace 7
Following up on the removal of BufferPSV in commit 43b86bf992 ("AMDGPU:
Remove BufferPseudoSourceValue")

It is unclear what exactly the right address space for images should be.
They seem morally closest to buffers, so that's what I went with. In
practical terms, address space 7 is better than address space 0 because
it can't alias with LDS.

Differential Revision: https://reviews.llvm.org/D138949
2022-11-30 11:32:34 +01:00
..
custom-pseudo-source-values.ll AMDGPU: Remove ImagePSV and move images to addrspace 7 2022-11-30 11:32:34 +01:00
dead-flag-on-use-operand-parse-error.mir
empty-custom-regmask.mir MIR: Fix parse error on empty CustomRegMask 2022-06-27 08:50:35 -04:00
expected-target-index-name.mir
extra-imm-operand.mir
extra-reg-operand.mir
intrinsics.mir
invalid-frame-index-invalid-fixed-stack.mir
invalid-frame-index-invalid-stack.mir
invalid-frame-index-no-stack.mir
invalid-frame-index.mir
invalid-frame-index2.mir
invalid-target-index-operand.mir
killed-flag-on-def-parse-error.mir
lit.local.cfg
llc-target-cpu-attr-from-cmdline-ir.mir
llc-target-cpu-attr-from-cmdline.mir
machine-function-info-after-pei.ll
machine-function-info-dynlds-align-invalid-case.mir
machine-function-info-no-ir.mir [amdgpu] Implement lds kernel id intrinsic 2022-07-19 17:46:19 +01:00
machine-function-info-register-parse-error1.mir
machine-function-info-register-parse-error2.mir
machine-function-info.ll [amdgpu] Implement lds kernel id intrinsic 2022-07-19 17:46:19 +01:00
machine-metadata-error.mir
machine-metadata.mir
mfi-frame-offset-reg-class.mir
mfi-parse-error-frame-offset-reg.mir
mfi-parse-error-scratch-rsrc-reg.mir
mfi-parse-error-stack-ptr-offset-reg.mir
mfi-scratch-rsrc-reg-reg-class.mir
mfi-stack-ptr-offset-reg-class.mir
mir-canon-multi.mir [AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores. 2022-11-14 15:36:18 +00:00
mircanon-memoperands.mir [MIRVRegNamer] Avoid opcode hash collision 2022-11-02 13:53:12 +00:00
parse-order-reserved-regs.mir [AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores. 2022-11-14 15:36:18 +00:00
stack-id-assert.mir
stack-id.mir
subreg-def-is-not-ssa.mir
syncscopes.mir
target-flags.mir
target-index-operands.mir [AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores. 2022-11-14 15:36:18 +00:00
target-memoperands.mir
vgpr-for-agpr-copy-invalid-reg.mir
wwm-reserved-regs-invalid-reg.mir
wwm-reserved-regs-not-a-reg.mir
wwm-reserved-regs.mir