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llvm-project/llvm/test/CodeGen/MIR
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Nicolai Hähnle b7f44f7cf9 AMDGPU: Remove ImagePSV and move images to addrspace 7 
Following up on the removal of BufferPSV in commit 43b86bf992 ("AMDGPU:
Remove BufferPseudoSourceValue")

It is unclear what exactly the right address space for images should be.
They seem morally closest to buffers, so that's what I went with. In
practical terms, address space 7 is better than address space 0 because
it can't alias with LDS.

Differential Revision: https://reviews.llvm.org/D138949
 		2022-11-30 11:32:34 +01:00
..
AArch64 [AArch64] Mark all instructions that read/write FPCR as doing so 2022-11-16 12:29:50 +00:00
AMDGPU AMDGPU: Remove ImagePSV and move images to addrspace 7 2022-11-30 11:32:34 +01:00
ARM
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Generic Untangle the mess which is MachineBasicBlock::hasAddressTaken(). 2022-08-16 16:15:44 -07:00
Hexagon
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Mips
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NVPTX
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PowerPC
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RISCV [RISCV][NFC] Add missing lit.local.cfg in test/CodeGen/MIR/RISCV/ 2022-04-08 12:10:20 +08:00
WebAssembly
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X86 [MIRVRegNamer] Avoid opcode hash collision 2022-11-02 13:53:12 +00:00
README
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README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.