删除了脚本中一些无效注释

.gitignore

@@ -170,4 +170,4 @@ cython_debug/
 #  be found at https://github.com/github/gitignore/blob/main/Global/JetBrains.gitignore
 #  and can be added to the global gitignore or merged into this file.  For a more nuclear
 #  option (not recommended) you can uncomment the following to ignore the entire idea folder.
-#.idea/
+#.idea/

scripts/build_ut_frontend_ftb_entry_mem.py

@@ -0,0 +1,38 @@
+import os
+from comm import warning, info
+
+def build(cfg):
+    # import base modules
+    from toffee_test.markers import match_version
+    from comm import is_all_file_exist, get_rtl_dir, exe_cmd, get_root_dir
+    # check version
+    if not match_version(cfg.rtl.version, "openxiangshan-kmh-*"):
+        warning("frontend_ftq_redirect_mem: %s" % f"Unsupported RTL version {cfg.rtl.version}")
+        return False
+    # check files
+    module_name = "FtbEntryMem"
+    file_name ="SyncDataModuleTemplate__64entry_1.sv"
+    dp_file_names = [
+    "DataModule__16entry_4.sv", 
+    ]
+    dp_fpaths = [f"rtl/rtl/{dp_file_name}" for dp_file_name in dp_file_names]
+    dp_fpaths_after_get_root = [get_root_dir(dp_fpath) for dp_fpath in dp_fpaths]
+    fpath = f"rtl/{file_name}"
+    all_fpaths = dp_fpaths + [fpath]
+    ## internal signals is now not determined
+    internal_signals_path=""
+    f = is_all_file_exist(all_fpaths, get_rtl_dir(cfg=cfg))
+    #assert f is True, f"File {f} not found"
+    # build
+    # export SyncDataModuleTemplate__64entry_1.sv
+    if not os.path.exists(get_root_dir(f"dut/{module_name}")):
+        info(f"Exporting {file_name}.sv")
+        s,out,err = exe_cmd(f'picker export {get_rtl_dir(f"{fpath}",cfg = cfg)} --tname {module_name}\
+                            --lang python --tdir {get_root_dir("dut")}/ -w {module_name}.fst -c --fs ' + ' '.join(dp_fpaths_after_get_root))
+        assert s, f"Failed to export {file_name}.sv: %s\n%s" % (out, err)
+
+    return True
+
+## set coverage
+def line_coverage_files(cfg):
+    return ["FtbEntryMem.v"]

scripts/build_ut_frontend_ftq_meta_1r_sram.py

@@ -0,0 +1,44 @@
+import os
+from comm import warning, info
+
+def build(cfg):
+    # import base modules
+    from toffee_test.markers import match_version
+    from comm import is_all_file_exist, get_rtl_dir, exe_cmd, get_root_dir
+    # check version
+    if not match_version(cfg.rtl.version, "openxiangshan-kmh-*"):
+        warning("frontend_ftq_redirect_mem: %s" % f"Unsupported RTL version {cfg.rtl.version}")
+        return False
+    # check files
+    module_name = "FtqMetairSram"
+    file_name ="FtqNRSRAM.sv"
+    dp_file_names = [
+    "SRAMTemplate_65.sv", 
+    "array_0_0.sv",
+    "ClockGate.sv",
+    "MbistClockGateCell.sv",
+    "sram_array_2p64x576m192s1h0l1b_ftq.sv",
+    "array_8.sv",
+    "array_8_ext.v"
+    ]
+    dp_fpaths = [f"rtl/rtl/{dp_file_name}" for dp_file_name in dp_file_names]
+    dp_fpaths_after_get_root = [get_root_dir(dp_fpath) for dp_fpath in dp_fpaths]
+    fpath = f"rtl/{file_name}"
+    all_fpaths = dp_fpaths + [fpath]
+    ## internal signals is now not determined
+    internal_signals_path=""
+    f = is_all_file_exist(all_fpaths, get_rtl_dir(cfg=cfg))
+    #assert f is True, f"File {f} not found"
+    # build
+    # export SyncDataModuleTemplate__64entry.sv
+    if not os.path.exists(get_root_dir(f"dut/{module_name}")):
+        info(f"Exporting {file_name}.sv")
+        s,out,err = exe_cmd(f'picker export {get_rtl_dir(f"{fpath}",cfg = cfg)} --tname {module_name}\
+                            --lang python --tdir {get_root_dir("dut")}/ -w {module_name}.fst -c --fs ' + ' '.join(dp_fpaths_after_get_root))
+        assert s, f"Failed to export {file_name}.sv: %s\n%s" % (out, err)
+
+    return True
+
+## set coverage
+def line_coverage_files(cfg):
+    return ["FtqMetairSram.v"]

scripts/build_ut_frontend_ftq_pc_mem.py

@@ -0,0 +1,39 @@
+import os
+from comm import warning, info
+
+def build(cfg):
+    # import base modules
+    from toffee_test.markers import match_version
+    from comm import is_all_file_exist, get_rtl_dir, exe_cmd, get_root_dir
+    # check version
+    if not match_version(cfg.rtl.version, "openxiangshan-kmh-*"):
+        warning("frontend_ftq_redirect_mem: %s" % f"Unsupported RTL version {cfg.rtl.version}")
+        return False
+    # check files
+    module_name = "FtqPcMem"
+    file_name ="FtqPcMemWrapper.sv"
+    dp_file_names = [
+    "SyncDataModuleTemplate_FtqPC_64entry.sv", 
+    "DataModule_FtqPC_16entry.sv"
+    ]
+    dp_fpaths = [f"rtl/rtl/{dp_file_name}" for dp_file_name in dp_file_names]
+    dp_fpaths_after_get_root = [get_root_dir(dp_fpath) for dp_fpath in dp_fpaths]
+    fpath = f"rtl/{file_name}"
+    all_fpaths = dp_fpaths + [fpath]
+    ## internal signals is now not determined
+    internal_signals_path=""
+    f = is_all_file_exist(all_fpaths, get_rtl_dir(cfg=cfg))
+    #assert f is True, f"File {f} not found"
+    # build
+    # export SyncDataModuleTemplate__64entry.sv
+    if not os.path.exists(get_root_dir(f"dut/{module_name}")):
+        info(f"Exporting {file_name}.sv")
+        s,out,err = exe_cmd(f'picker export {get_rtl_dir(f"{fpath}",cfg = cfg)} --tname {module_name}\
+                            --lang python --tdir {get_root_dir("dut")}/ -w {module_name}.fst -c --fs ' + ' '.join(dp_fpaths_after_get_root))
+        assert s, f"Failed to export {file_name}.sv: %s\n%s" % (out, err)
+
+    return True
+
+## set coverage
+def line_coverage_files(cfg):
+    return ["FtqPcMem.v"]

scripts/build_ut_frontend_ftq_pd_mem.py

@@ -0,0 +1,38 @@
+import os
+from comm import warning, info
+
+def build(cfg):
+    # import base modules
+    from toffee_test.markers import match_version
+    from comm import is_all_file_exist, get_rtl_dir, exe_cmd, get_root_dir
+    # check version
+    if not match_version(cfg.rtl.version, "openxiangshan-kmh-*"):
+        warning("frontend_ftq_pd_mem: %s" % f"Unsupported RTL version {cfg.rtl.version}")
+        return False
+    # check files
+    module_name = "FtqPdMem"
+    file_name ="SyncDataModuleTemplate__64entry_2.sv"
+    dp_file_names = [
+    "DataModule__16entry_8.sv", 
+    ]
+    dp_fpaths = [f"rtl/rtl/{dp_file_name}" for dp_file_name in dp_file_names]
+    dp_fpaths_after_get_root = [get_root_dir(dp_fpath) for dp_fpath in dp_fpaths]
+    fpath = f"rtl/{file_name}"
+    all_fpaths = dp_fpaths + [fpath]
+    ## internal signals is now not determined
+    internal_signals_path=""
+    f = is_all_file_exist(all_fpaths, get_rtl_dir(cfg=cfg))
+    #assert f is True, f"File {f} not found"    ##some problem here
+    # build
+    # export SyncDataModuleTemplate__64_1entry.sv
+    if not os.path.exists(get_root_dir(f"dut/{module_name}")):
+        info(f"Exporting {file_name}.sv")
+        s,out,err = exe_cmd(f'picker export {get_rtl_dir(f"{fpath}",cfg = cfg)} --tname {module_name}\
+                            --lang python --tdir {get_root_dir("dut")}/ -w {module_name}.fst -c --fs ' + ' '.join(dp_fpaths_after_get_root))
+        assert s, f"Failed to export {file_name}.sv: %s\n%s" % (out, err)
+
+    return True
+
+## set coverage
+def line_coverage_files(cfg):
+    return ["FtqPdMem.v"]

scripts/build_ut_frontend_ftq_redirect_mem.py

@@ -0,0 +1,38 @@
+import os
+from comm import warning, info
+
+def build(cfg):
+    # import base modules
+    from toffee_test.markers import match_version
+    from comm import is_all_file_exist, get_rtl_dir, exe_cmd, get_root_dir
+    # check version
+    if not match_version(cfg.rtl.version, "openxiangshan-kmh-*"):
+        warning("frontend_ftq_redirect_mem: %s" % f"Unsupported RTL version {cfg.rtl.version}")
+        return False
+    # check files
+    module_name = "FtqRedirectMem"
+    file_name ="SyncDataModuleTemplate__64entry.sv"
+    dp_file_names = [
+    "DataModule__16entry.sv", 
+    ]
+    dp_fpaths = [f"rtl/rtl/{dp_file_name}" for dp_file_name in dp_file_names]
+    dp_fpaths_after_get_root = [get_root_dir(dp_fpath) for dp_fpath in dp_fpaths]
+    fpath = f"rtl/{file_name}"
+    all_fpaths = dp_fpaths + [fpath]
+    ## internal signals is now not determined
+    internal_signals_path=""
+    f = is_all_file_exist(all_fpaths, get_rtl_dir(cfg=cfg))
+    #assert f is True, f"File {f} not found"
+    # build
+    # export SyncDataModuleTemplate__64entry.sv
+    if not os.path.exists(get_root_dir(f"dut/{module_name}")):
+        info(f"Exporting {file_name}.sv")
+        s,out,err = exe_cmd(f'picker export {get_rtl_dir(f"{fpath}",cfg = cfg)} --tname {module_name}\
+                            --lang python --tdir {get_root_dir("dut")}/ -w {module_name}.fst -c --fs ' + ' '.join(dp_fpaths_after_get_root))
+        assert s, f"Failed to export {file_name}.sv: %s\n%s" % (out, err)
+
+    return True
+
+## set coverage
+def line_coverage_files(cfg):
+    return ["FtqRedirectMem.v"]

scripts/build_ut_frontend_ftq_top.py

@@ -0,0 +1,59 @@
+import os
+from comm import warning, info
+
+def build(cfg):
+    # import base modules
+    from toffee_test.markers import match_version
+    from comm import is_all_file_exist, get_rtl_dir, exe_cmd, get_root_dir
+    # check version
+    if not match_version(cfg.rtl.version, "openxiangshan-kmh-*"):
+        warning("frontend_ftq_top: %s" % f"Unsupported RTL version {cfg.rtl.version}")
+        return False
+    # check files 1
+    module_name = "FtqTop"
+    file_name ="Ftq.sv"
+    dp_file_names = [
+    "SyncDataModuleTemplate__64entry.sv", 
+    "SyncDataModuleTemplate__64entry_1.sv", 
+    "SyncDataModuleTemplate__64entry_2.sv", 
+    "SyncDataModuleTemplate__64entry_3.sv", 
+    "DataModule__16entry.sv", 
+    "DataModule__16entry_4.sv", 
+    "DataModule__16entry_8.sv", 
+    "DataModule__16entry_12.sv", 
+    "FTBEntryGen.sv", 
+    "FtqNRSRAM.sv", 
+    "FtqPcMemWrapper.sv", 
+    "SRAMTemplate_65.sv", 
+    "SyncDataModuleTemplate_FtqPC_64entry.sv", 
+    "DataModule_FtqPC_16entry.sv", 
+    "array_0_0.sv", 
+    "array_0_0_ext.v",
+    "ClockGate.sv",
+    "MbistClockGateCell.sv",
+    "sram_array_2p64x576m192s1h0l1b_ftq.sv",
+    "array_8.sv",
+    "array_8_ext.v",
+    "MbistPipeFtq.sv"
+    ]
+    dp_fpaths = [f"rtl/rtl/{dp_file_name}" for dp_file_name in dp_file_names]
+    dp_fpaths_after_get_root = [get_root_dir(dp_fpath) for dp_fpath in dp_fpaths]
+    fpath = f"rtl/{file_name}"
+    all_fpaths = dp_fpaths + [fpath]
+    ## internal signals is now not determined
+    internal_signals_path=""
+    f = is_all_file_exist(all_fpaths, get_rtl_dir(cfg=cfg))
+    #assert f is True, f"File {f} not found"
+    # build
+    # export ftq.sv
+    if not os.path.exists(get_root_dir(f"dut/{module_name}")):
+        info("Exporting Ftq.sv")
+        s,out,err = exe_cmd(f'picker export --cp_lib false {get_rtl_dir(f"{fpath}",cfg = cfg)} \
+                            --lang python --tdir {get_root_dir("dut")}/ -w {module_name}.fst -c --fs ' + ' '.join(dp_fpaths_after_get_root))
+        assert s, f"Failed to export Ftq.sv: %s\n%s" % (out, err)
+
+    return True
+
+## set coverage
+def line_coverage_files(cfg):
+    return ["Ftq.v"]

ut_frontend/ftq/ftq_redirect_mem/test/test_random.py

@@ -0,0 +1,279 @@
+try:
+    from dut.UT_FtqRedirectMem import *
+except:
+    try:
+        from dut.FtqRedirectMem import *
+    except:
+        from __init__ import *
+import random
+import pytest
+import time
+
+FtqSize = 64
+
+last_read = []
+
+# set write mode
+def set_write_mode_imm(dut):
+    dut.io_wen_0.AsImmWrite()
+    dut.io_waddr_0.AsImmWrite()
+    dut.io_wdata_0_histPtr_flag.AsImmWrite()
+    dut.io_wdata_0_histPtr_value.AsImmWrite()
+    dut.io_wdata_0_ssp.AsImmWrite()
+    dut.io_wdata_0_sctr.AsImmWrite()
+    dut.io_wdata_0_TOSW_flag.AsImmWrite()
+    dut.io_wdata_0_TOSW_value.AsImmWrite()
+    dut.io_wdata_0_TOSR_flag.AsImmWrite()
+    dut.io_wdata_0_TOSR_value.AsImmWrite()
+    dut.io_wdata_0_NOS_flag.AsImmWrite()
+    dut.io_wdata_0_NOS_value.AsImmWrite()
+    dut.io_wdata_0_topAddr.AsImmWrite()
+    dut.io_ren_0.AsImmWrite()
+    dut.io_ren_1.AsImmWrite()
+    dut.io_ren_2.AsImmWrite()
+
+
+
+
+@pytest.fixture()
+def init_ref():
+    #initialize the ref
+    print("init ref")
+    FtqRedirectMem = []
+    FtqRedirectMem_entry = {
+        "histPtr_flag": 0,
+        "histPtr_value": 0,
+        "ssp": 0,
+        "sctr": 0,
+        "TOSW_flag": 0,
+        "TOSW_value": 0,
+        "TOSR_flag": 0,
+        "TOSR_value": 0,
+        "NOS_flag": 0,
+        "NOS_value": 0,
+        "topAddr": 0
+    }
+    global FtqSize
+    for i in range(FtqSize):
+        FtqRedirectMem.append(FtqRedirectMem_entry.copy())
+
+    # init_ref_read(FtqRedirectMem)
+
+    return FtqRedirectMem
+
+@pytest.fixture()
+def init_dut():
+    # initialize the dut
+    print("init dut")
+    dut = DUTFtqRedirectMem()
+    
+    # init clock, set wave
+    dut.InitClock("clock")
+    dut.SetWaveform("test_random.fst")
+
+    # set_write mode
+    set_write_mode_imm(dut)
+
+    FtqRedirectMem_entry = {
+        "histPtr_flag": 0,
+        "histPtr_value": 0,
+        "ssp": 0,
+        "sctr": 0,
+        "TOSW_flag": 0,
+        "TOSW_value": 0,
+        "TOSR_flag": 0,
+        "TOSR_value": 0,
+        "NOS_flag": 0,
+        "NOS_value": 0,
+        "topAddr": 0
+    }
+    global FtqSize
+    for i in range(FtqSize):
+        dut.Step(1)
+        write_dut(dut=dut,wen=1,waddr=i,wdata=FtqRedirectMem_entry)
+        
+    return dut
+
+
+
+def reset_dut(dut):
+    dut.Step(1)
+    dut.reset.value = 0
+    dut.Step(1)
+
+def init_ref_last_read():
+    rdatas = []
+    rdata_0 = {}
+    rdata_1 = {}
+    rdata_2 = {}
+    rdatas.extend([rdata_0,rdata_1,rdata_2])
+    rdata_0["histPtr_flag"] = 0
+    rdata_0["histPtr_value"] = 0
+    rdata_0["ssp"] = 0
+    rdata_0["sctr"] = 0
+    rdata_0["TOSW_flag"] = 0
+    rdata_0["TOSW_value"] = 0
+    rdata_0["TOSR_flag"] = 0
+    rdata_0["TOSR_value"] = 0
+    rdata_0["NOS_flag"] = 0
+    rdata_0["NOS_value"] = 0
+    rdata_0["topAddr"] = 0
+
+    rdata_1["histPtr_flag"] = 0
+    rdata_1["histPtr_value"] = 0
+    rdata_1["ssp"] = 0
+    rdata_1["sctr"] = 0
+    rdata_1["TOSW_flag"] = 0
+    rdata_1["TOSW_value"] = 0
+    rdata_1["TOSR_flag"] = 0
+    rdata_1["TOSR_value"] = 0
+    rdata_1["NOS_flag"] = 0
+    rdata_1["NOS_value"] = 0
+
+    rdata_2["histPtr_value"] = 0
+
+    global last_read
+    last_read = rdatas
+
+def write_dut(dut, wen, wdata, waddr):
+        dut.io_wen_0.value = wen
+        dut.io_waddr_0.value = waddr
+        dut.io_wdata_0_histPtr_flag.value = wdata["histPtr_flag"]
+        dut.io_wdata_0_histPtr_value.value = wdata["histPtr_value"]
+        dut.io_wdata_0_ssp.value = wdata["ssp"]
+        dut.io_wdata_0_sctr.value = wdata["sctr"]
+        dut.io_wdata_0_TOSW_flag.value = wdata["TOSW_flag"]
+        dut.io_wdata_0_TOSW_value.value = wdata["TOSW_value"]
+        dut.io_wdata_0_TOSR_flag.value = wdata["TOSR_flag"]
+        dut.io_wdata_0_TOSR_value.value = wdata["TOSR_value"]
+        dut.io_wdata_0_NOS_flag.value = wdata["NOS_flag"]
+        dut.io_wdata_0_NOS_value.value = wdata["NOS_value"]
+        dut.io_wdata_0_topAddr.value = wdata["topAddr"]
+        
+        dut.Step(1)
+
+def write_ref(ref, wen, wdata, waddr):
+    if(wen):
+        ref[waddr] = wdata
+    # print("wirte data:",ref[waddr])
+    # print("wirte addr:",waddr)
+
+# must reset, it make sure that the last_read's element is given keys
+def read_dut(dut, ren, raddr):
+    rdatas = []
+    rdata_0 = {}
+    rdata_1 = {}
+    rdata_2 = {}
+    
+    #set ren
+    dut.io_ren_0.value = ren[0]
+    dut.io_ren_1.value = ren[1]
+    dut.io_ren_2.value = ren[2]
+    #input addr
+    dut.io_raddr_0.value = raddr[0]
+    dut.io_raddr_1.value = raddr[1]
+    dut.io_raddr_2.value = raddr[2]
+    
+    dut.Step(2)## some problem
+
+    # get result
+
+    rdata_0["histPtr_flag"] = dut.io_rdata_0_histPtr_flag.value
+    rdata_0["histPtr_value"] = dut.io_rdata_0_histPtr_value.value
+    rdata_0["ssp"] = dut.io_rdata_0_ssp.value
+    rdata_0["sctr"] = dut.io_rdata_0_sctr.value
+    rdata_0["TOSW_flag"] = dut.io_rdata_0_TOSW_flag.value
+    rdata_0["TOSW_value"] = dut.io_rdata_0_TOSW_value.value
+    rdata_0["TOSR_flag"] = dut.io_rdata_0_TOSR_flag.value
+    rdata_0["TOSR_value"] = dut.io_rdata_0_TOSR_value.value
+    rdata_0["NOS_flag"] = dut.io_rdata_0_NOS_flag.value
+    rdata_0["NOS_value"] = dut.io_rdata_0_NOS_value.value
+    rdata_0["topAddr"] = dut.io_rdata_0_topAddr.value
+
+  
+    rdata_1["histPtr_flag"] = dut.io_rdata_1_histPtr_flag.value
+    rdata_1["histPtr_value"] = dut.io_rdata_1_histPtr_value.value
+    rdata_1["ssp"] = dut.io_rdata_1_ssp.value
+    rdata_1["sctr"] = dut.io_rdata_1_sctr.value
+    rdata_1["TOSW_flag"] = dut.io_rdata_1_TOSW_flag.value
+    rdata_1["TOSW_value"] = dut.io_rdata_1_TOSW_value.value
+    rdata_1["TOSR_flag"] = dut.io_rdata_1_TOSR_flag.value
+    rdata_1["TOSR_value"] = dut.io_rdata_1_TOSR_value.value
+    rdata_1["NOS_flag"] = dut.io_rdata_1_NOS_flag.value
+    rdata_1["NOS_value"] = dut.io_rdata_1_NOS_value.value
+    # no top Addr
+    #rdata_1["topAddr"] = dut.io_rdata_1_topAddr.value
+
+    # only histptr
+    rdata_2["histPtr_value"] = dut.io_rdata_2_histPtr_value.value
+
+
+    rdatas.append(rdata_0)
+    rdatas.append(rdata_1)    
+    rdatas.append(rdata_2)
+    return rdatas
+
+def read_ref(ref,ren,raddr):
+    global last_read
+    rdatas = last_read
+    for i in range(3):
+        if(ren[i]):
+            for key in rdatas[i]:
+                    rdatas[i][key] = ref[raddr[i]][key]
+    last_read = rdatas
+    return rdatas
+
+def test_random(init_ref, init_dut):
+    # get init
+    ref = init_ref
+    dut = init_dut
+    
+    init_ref_last_read()
+
+    for i in range(20000):
+        print("round:",i)  
+        # genarate random wdata
+        wdata = {
+            "histPtr_flag": random.randint(0,1),
+            "histPtr_value": random.randint(0,2**8-1),
+            "ssp": random.randint(0,2**4-1),
+            "sctr": random.randint(0,2**3-1),
+            "TOSW_flag": random.randint(0,1),
+            "TOSW_value": random.randint(0,2**5-1),
+            "TOSR_flag": random.randint(0,1),
+            "TOSR_value": random.randint(0,2**5-1),
+            "NOS_flag": random.randint(0,1),
+            "NOS_value": random.randint(0,2**5-1),
+            "topAddr": random.randint(0,2**50-1),
+        }
+
+        dut.io_wen_0.value = 0
+        dut.Step(1)
+
+        #write
+        wen = random.randint(0,1)
+        global FtqSize
+        waddr = random.randint(0,FtqSize - 1)
+        # print("waddr:",waddr)
+        write_dut(dut, wen, wdata, waddr)
+        write_ref(ref, wen, wdata, waddr)
+
+        #read  
+        ren = [random.randint(0, 1) for i in range(3)]
+        raddr = [random.randint(0, FtqSize-1) for i in range(3)]
+        read_dut_result = read_dut(dut=dut, ren=ren, raddr=raddr)
+        read_ref_result = read_ref(ref=ref, ren=ren, raddr=raddr)
+
+        # test
+        # print("dut ren:", dut.io_ren_0.value,dut.io_ren_1.value,dut.io_ren_2.value)
+        # print(read_dut_result)
+        # print(ref[raddr[0]])
+        if ren[0] == 1:
+            assert read_dut_result[0] == read_ref_result[0], "read mismatch for port 0"
+        if ren[1] == 1:
+            assert read_dut_result[1] == read_ref_result[1], "read mismatch for port 1"
+        if ren[2] == 1:
+            assert read_dut_result[2] == read_ref_result[2], "read mismatch for port 2"
+    # test
+    print("Test Passed")
+    dut.Finish()

ut_frontend/ftq/ftq_top/ftq_top.yaml

@@ -0,0 +1 @@
+Ftq: