forked from OSchip/UnityChipVerification
272 lines
22 KiB
Systemverilog
272 lines
22 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module DelayNWithValid_1( // @[utility/src/main/scala/utility/Hold.scala:106:7]
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input clock, // @[utility/src/main/scala/utility/Hold.scala:106:7]
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input reset, // @[utility/src/main/scala/utility/Hold.scala:106:7]
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input io_in_bits_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input [3:0] io_in_bits_brSlots_0_offset, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input [11:0] io_in_bits_brSlots_0_lower, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input [1:0] io_in_bits_brSlots_0_tarStat, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_brSlots_0_sharing, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_brSlots_0_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input [3:0] io_in_bits_tailSlot_offset, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input [19:0] io_in_bits_tailSlot_lower, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input [1:0] io_in_bits_tailSlot_tarStat, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_tailSlot_sharing, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_tailSlot_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input [3:0] io_in_bits_pftAddr, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_carry, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_isCall, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_isRet, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_isJalr, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_last_may_be_rvi_call, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_always_taken_0, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_bits_always_taken_1, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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input io_in_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output [3:0] io_out_bits_brSlots_0_offset, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output [11:0] io_out_bits_brSlots_0_lower, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output [1:0] io_out_bits_brSlots_0_tarStat, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_brSlots_0_sharing, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_brSlots_0_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output [3:0] io_out_bits_tailSlot_offset, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output [19:0] io_out_bits_tailSlot_lower, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output [1:0] io_out_bits_tailSlot_tarStat, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_tailSlot_sharing, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_tailSlot_valid, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output [3:0] io_out_bits_pftAddr, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_carry, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_isCall, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_isRet, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_isJalr, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_last_may_be_rvi_call, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_always_taken_0, // @[utility/src/main/scala/utility/Hold.scala:107:14]
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output io_out_bits_always_taken_1 // @[utility/src/main/scala/utility/Hold.scala:107:14]
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);
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reg valid_REG; // @[utility/src/main/scala/utility/Hold.scala:117:25]
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reg data_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [3:0] data_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [11:0] data_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [1:0] data_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [3:0] data_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [19:0] data_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [1:0] data_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [3:0] data_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_carry; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_isCall; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_isRet; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_isJalr; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg data_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [3:0] res_bits_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [11:0] res_bits_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [1:0] res_bits_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [3:0] res_bits_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [19:0] res_bits_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [1:0] res_bits_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg [3:0] res_bits_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_carry; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_isCall; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_isRet; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_isJalr; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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reg res_bits_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/Hold.scala:106:7]
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if (reset) // @[utility/src/main/scala/utility/Hold.scala:106:7]
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valid_REG <= 1'h0; // @[utility/src/main/scala/utility/Hold.scala:117:25]
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else // @[utility/src/main/scala/utility/Hold.scala:106:7]
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valid_REG <= io_in_valid; // @[utility/src/main/scala/utility/Hold.scala:117:25]
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end // always @(posedge, posedge)
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always @(posedge clock) begin // @[utility/src/main/scala/utility/Hold.scala:106:7]
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if (io_in_valid) begin // @[utility/src/main/scala/utility/Hold.scala:107:14]
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data_valid <= io_in_bits_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_brSlots_0_offset <= io_in_bits_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_brSlots_0_lower <= io_in_bits_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_brSlots_0_tarStat <= io_in_bits_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_brSlots_0_sharing <= io_in_bits_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_brSlots_0_valid <= io_in_bits_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_tailSlot_offset <= io_in_bits_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_tailSlot_lower <= io_in_bits_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_tailSlot_tarStat <= io_in_bits_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_tailSlot_sharing <= io_in_bits_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_tailSlot_valid <= io_in_bits_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_pftAddr <= io_in_bits_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_carry <= io_in_bits_carry; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_isCall <= io_in_bits_isCall; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_isRet <= io_in_bits_isRet; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_isJalr <= io_in_bits_isJalr; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_last_may_be_rvi_call <= io_in_bits_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_always_taken_0 <= io_in_bits_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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data_always_taken_1 <= io_in_bits_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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end
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if (valid_REG) begin // @[utility/src/main/scala/utility/Hold.scala:117:25]
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res_bits_valid <= data_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_brSlots_0_offset <= data_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_brSlots_0_lower <= data_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_brSlots_0_tarStat <= data_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_brSlots_0_sharing <= data_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_brSlots_0_valid <= data_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_tailSlot_offset <= data_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_tailSlot_lower <= data_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_tailSlot_tarStat <= data_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_tailSlot_sharing <= data_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_tailSlot_valid <= data_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_pftAddr <= data_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_carry <= data_carry; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_isCall <= data_isCall; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_isRet <= data_isRet; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_isJalr <= data_isJalr; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_last_may_be_rvi_call <= data_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_always_taken_0 <= data_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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res_bits_always_taken_1 <= data_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:121:27]
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end
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/Hold.scala:106:7]
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`ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7]
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`FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7]
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:3]; // @[utility/src/main/scala/utility/Hold.scala:106:7]
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initial begin // @[utility/src/main/scala/utility/Hold.scala:106:7]
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`ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:106:7]
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`INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:106:7]
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/Hold.scala:106:7]
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for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
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_RANDOM[i[1:0]] = `RANDOM; // @[utility/src/main/scala/utility/Hold.scala:106:7]
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end // @[utility/src/main/scala/utility/Hold.scala:106:7]
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valid_REG = _RANDOM[2'h0][0]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25]
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data_valid = _RANDOM[2'h0][1]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27]
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data_brSlots_0_offset = _RANDOM[2'h0][5:2]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27]
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data_brSlots_0_lower = _RANDOM[2'h0][17:6]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27]
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data_brSlots_0_tarStat = _RANDOM[2'h0][19:18]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27]
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data_brSlots_0_sharing = _RANDOM[2'h0][20]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27]
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data_brSlots_0_valid = _RANDOM[2'h0][21]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27]
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data_tailSlot_offset = _RANDOM[2'h0][25:22]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27]
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data_tailSlot_lower = {_RANDOM[2'h0][31:26], _RANDOM[2'h1][13:0]}; // @[utility/src/main/scala/utility/Hold.scala:106:7, :117:25, :121:27]
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data_tailSlot_tarStat = _RANDOM[2'h1][15:14]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_tailSlot_sharing = _RANDOM[2'h1][16]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_tailSlot_valid = _RANDOM[2'h1][17]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_pftAddr = _RANDOM[2'h1][21:18]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_carry = _RANDOM[2'h1][22]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_isCall = _RANDOM[2'h1][23]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_isRet = _RANDOM[2'h1][24]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_isJalr = _RANDOM[2'h1][25]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_last_may_be_rvi_call = _RANDOM[2'h1][26]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_always_taken_0 = _RANDOM[2'h1][27]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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data_always_taken_1 = _RANDOM[2'h1][28]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_valid = _RANDOM[2'h1][30]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_brSlots_0_offset = {_RANDOM[2'h1][31], _RANDOM[2'h2][2:0]}; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_brSlots_0_lower = _RANDOM[2'h2][14:3]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_brSlots_0_tarStat = _RANDOM[2'h2][16:15]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_brSlots_0_sharing = _RANDOM[2'h2][17]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_brSlots_0_valid = _RANDOM[2'h2][18]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_tailSlot_offset = _RANDOM[2'h2][22:19]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_tailSlot_lower = {_RANDOM[2'h2][31:23], _RANDOM[2'h3][10:0]}; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_tailSlot_tarStat = _RANDOM[2'h3][12:11]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_tailSlot_sharing = _RANDOM[2'h3][13]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_tailSlot_valid = _RANDOM[2'h3][14]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_pftAddr = _RANDOM[2'h3][18:15]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_carry = _RANDOM[2'h3][19]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_isCall = _RANDOM[2'h3][20]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_isRet = _RANDOM[2'h3][21]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_isJalr = _RANDOM[2'h3][22]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_last_may_be_rvi_call = _RANDOM[2'h3][23]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_always_taken_0 = _RANDOM[2'h3][24]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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res_bits_always_taken_1 = _RANDOM[2'h3][25]; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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`endif // RANDOMIZE_REG_INIT
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if (reset) // @[utility/src/main/scala/utility/Hold.scala:106:7]
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valid_REG = 1'h0; // @[utility/src/main/scala/utility/Hold.scala:117:25]
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7]
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`FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:106:7]
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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assign io_out_bits_valid = res_bits_valid; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_brSlots_0_offset = res_bits_brSlots_0_offset; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_brSlots_0_lower = res_bits_brSlots_0_lower; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_brSlots_0_tarStat = res_bits_brSlots_0_tarStat; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_brSlots_0_sharing = res_bits_brSlots_0_sharing; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_brSlots_0_valid = res_bits_brSlots_0_valid; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_tailSlot_offset = res_bits_tailSlot_offset; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_tailSlot_lower = res_bits_tailSlot_lower; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_tailSlot_tarStat = res_bits_tailSlot_tarStat; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_tailSlot_sharing = res_bits_tailSlot_sharing; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_tailSlot_valid = res_bits_tailSlot_valid; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_pftAddr = res_bits_pftAddr; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_carry = res_bits_carry; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_isCall = res_bits_isCall; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_isRet = res_bits_isRet; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_isJalr = res_bits_isJalr; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_last_may_be_rvi_call = res_bits_last_may_be_rvi_call; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_always_taken_0 = res_bits_always_taken_0; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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assign io_out_bits_always_taken_1 = res_bits_always_taken_1; // @[utility/src/main/scala/utility/Hold.scala:106:7, :121:27]
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endmodule
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