forked from OSchip/UnityChipVerification
189 lines
12 KiB
Systemverilog
189 lines
12 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module TageBTable( // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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input clock, // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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input reset, // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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output io_req_ready, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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input io_req_valid, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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input [40:0] io_req_bits, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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output [1:0] io_s1_cnt_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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output [1:0] io_s1_cnt_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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input [1:0] io_update_cnt_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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input [1:0] io_update_cnt_1, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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input io_update_takens_1 // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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);
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wire [1:0] newCtrs_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:213:8]
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wire [1:0] newCtrs_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:213:8]
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wire _wrbypass_io_hit; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24]
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wire _wrbypass_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24]
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wire [1:0] _wrbypass_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24]
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wire _wrbypass_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24]
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wire [1:0] _wrbypass_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24]
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wire [1:0] _bt_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:154:18]
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wire [1:0] _bt_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:154:18]
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reg doing_reset; // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28]
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reg [10:0] resetRow; // @[src/main/scala/xiangshan/frontend/Tage.scala:167:25]
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reg [10:0] s1_idx; // @[src/main/scala/xiangshan/frontend/Tage.scala:181:25]
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wire _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:193:45]
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wire [1:0] oldCtrs_0 =
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_wrbypass_io_hit
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& (io_update_pc[1] ? _wrbypass_io_hit_data_1_valid : _wrbypass_io_hit_data_0_valid)
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? (io_update_pc[1] ? _wrbypass_io_hit_data_1_bits : _wrbypass_io_hit_data_0_bits)
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: io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27}]
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wire [1:0] oldCtrs_1 =
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_wrbypass_io_hit
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& (io_update_pc[1] ? _wrbypass_io_hit_data_0_valid : _wrbypass_io_hit_data_1_valid)
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? (io_update_pc[1] ? _wrbypass_io_hit_data_0_bits : _wrbypass_io_hit_data_1_bits)
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: io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27}]
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wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21]
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assign newCtrs_0 =
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(&oldCtrs_0) & _GEN
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? 2'h3
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: oldCtrs_0 == 2'h0 & ~_GEN
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? 2'h0
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: _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1); // @[src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36]
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wire _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21]
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assign newCtrs_1 =
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(&oldCtrs_1) & _GEN_0
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? 2'h3
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: oldCtrs_1 == 2'h0 & ~_GEN_0
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? 2'h0
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: _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1); // @[src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36]
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always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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if (reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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doing_reset <= 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28]
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resetRow <= 11'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:167:25]
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end
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else begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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doing_reset <= resetRow != 11'h7FF & doing_reset; // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :169:{18,36,50}]
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resetRow <= 11'(resetRow + {10'h0, doing_reset}); // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :168:24]
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end
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end // always @(posedge, posedge)
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always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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if (io_req_valid) // @[src/main/scala/xiangshan/frontend/Tage.scala:138:14]
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s1_idx <= io_req_bits[11:1]; // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65, src/main/scala/xiangshan/frontend/Tage.scala:181:25]
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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`ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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`FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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initial begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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`ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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`INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28]
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resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1]; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :167:25]
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s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12]; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :181:25]
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`endif // RANDOMIZE_REG_INIT
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if (reset) begin // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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doing_reset = 1'h1; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28]
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resetRow = 11'h0; // @[src/main/scala/xiangshan/frontend/Tage.scala:167:25]
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end
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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`FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7]
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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FoldedSRAMTemplate_20 bt ( // @[src/main/scala/xiangshan/frontend/Tage.scala:154:18]
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.clock (clock),
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.reset (reset),
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.io_r_req_valid (io_req_valid),
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.io_r_req_bits_setIdx (io_req_bits[11:1]), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65]
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.io_r_resp_data_0 (_bt_io_r_resp_data_0),
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.io_r_resp_data_1 (_bt_io_r_resp_data_1),
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.io_w_req_valid (_wrbypass_io_wen_T | doing_reset), // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :193:45, :231:41]
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.io_w_req_bits_setIdx (doing_reset ? resetRow : io_update_pc[11:1]), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65, src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :233:17]
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.io_w_req_bits_data_0 (doing_reset ? 2'h2 : newCtrs_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36}]
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.io_w_req_bits_data_1 (doing_reset ? 2'h2 : newCtrs_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36}]
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.io_w_req_bits_waymask
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(doing_reset
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? 2'h3
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: {io_update_mask_0 & io_update_pc[1] | io_update_mask_1 & ~(io_update_pc[1]),
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io_update_mask_0 & ~(io_update_pc[1]) | io_update_mask_1 & io_update_pc[1]}) // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :166:28, :211:27, :226:{26,55}, :227:15, :228:6, :234:18]
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);
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WrBypass_32 wrbypass ( // @[src/main/scala/xiangshan/frontend/Tage.scala:192:24]
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.clock (clock),
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.reset (reset),
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.io_wen (_wrbypass_io_wen_T), // @[src/main/scala/xiangshan/frontend/Tage.scala:193:45]
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.io_write_idx (io_update_pc[11:1]), // @[src/main/scala/xiangshan/frontend/FrontendBundle.scala:400:65]
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.io_write_data_0 (io_update_pc[1] ? newCtrs_1 : newCtrs_0), // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8]
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.io_write_data_1 (io_update_pc[1] ? newCtrs_0 : newCtrs_1), // @[src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8]
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.io_write_way_mask_0 (io_update_mask_0),
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.io_write_way_mask_1 (io_update_mask_1),
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.io_hit (_wrbypass_io_hit),
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.io_hit_data_0_valid (_wrbypass_io_hit_data_0_valid),
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.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits),
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.io_hit_data_1_valid (_wrbypass_io_hit_data_1_valid),
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.io_hit_data_1_bits (_wrbypass_io_hit_data_1_bits)
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);
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assign io_req_ready = ~doing_reset; // @[src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :172:19]
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assign io_s1_cnt_0 =
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(s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36]
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assign io_s1_cnt_1 =
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(s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36]
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endmodule
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