forked from OSchip/UnityChipVerification
245 lines
18 KiB
Systemverilog
245 lines
18 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
|
|
// Standard header to adapt well known macros for register randomization.
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_MEM_INIT
|
|
`endif // not def RANDOMIZE
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_REG_INIT
|
|
`endif // not def RANDOMIZE
|
|
|
|
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif // not def RANDOM
|
|
|
|
// Users can define INIT_RANDOM as general code that gets injected into the
|
|
// initializer block for modules with registers.
|
|
`ifndef INIT_RANDOM
|
|
`define INIT_RANDOM
|
|
`endif // not def INIT_RANDOM
|
|
|
|
// If using random initialization, you can also define RANDOMIZE_DELAY to
|
|
// customize the delay used, otherwise 0.002 is used.
|
|
`ifndef RANDOMIZE_DELAY
|
|
`define RANDOMIZE_DELAY 0.002
|
|
`endif // not def RANDOMIZE_DELAY
|
|
|
|
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
|
|
`ifndef INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE
|
|
`ifdef VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
|
|
`else // VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
|
|
`endif // VERILATOR
|
|
`else // RANDOMIZE
|
|
`define INIT_RANDOM_PROLOG_
|
|
`endif // RANDOMIZE
|
|
`endif // not def INIT_RANDOM_PROLOG_
|
|
|
|
// Include register initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_REG_
|
|
`define ENABLE_INITIAL_REG_
|
|
`endif // not def ENABLE_INITIAL_REG_
|
|
`endif // not def SYNTHESIS
|
|
|
|
// Include rmemory initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_MEM_
|
|
`define ENABLE_INITIAL_MEM_
|
|
`endif // not def ENABLE_INITIAL_MEM_
|
|
`endif // not def SYNTHESIS
|
|
|
|
module SCTable( // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
input clock, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
input reset, // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
input io_req_valid, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input [40:0] io_req_bits_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
output [5:0] io_resp_ctrs_0_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
output [5:0] io_resp_ctrs_0_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
output [5:0] io_resp_ctrs_1_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
output [5:0] io_resp_ctrs_1_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input [40:0] io_update_pc, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input io_update_mask_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input io_update_mask_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input [5:0] io_update_oldCtrs_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input [5:0] io_update_oldCtrs_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input io_update_tagePreds_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input io_update_tagePreds_1, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input io_update_takens_0, // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
input io_update_takens_1 // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
);
|
|
|
|
wire _wrbypasses_1_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire _wrbypasses_1_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire _wrbypasses_1_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire _wrbypasses_0_io_hit; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire _wrbypasses_0_io_hit_data_0_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire _wrbypasses_0_io_hit_data_1_valid; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
wire [5:0] _table_io_r_resp_data_0; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21]
|
|
wire [5:0] _table_io_r_resp_data_1; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21]
|
|
wire [5:0] _table_io_r_resp_data_2; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21]
|
|
wire [5:0] _table_io_r_resp_data_3; // @[src/main/scala/xiangshan/frontend/SC.scala:71:21]
|
|
reg [40:0] s1_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24]
|
|
wire updateWayMask_0 =
|
|
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
|
|
& io_update_pc[1] & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
wire updateWayMask_1 =
|
|
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
|
|
& io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
wire updateWayMask_2 =
|
|
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
|
|
& ~(io_update_pc[1]) & ~io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92]
|
|
wire updateWayMask_3 =
|
|
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
|
|
& ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92]
|
|
wire ctrPos =
|
|
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
wire [5:0] oldCtr =
|
|
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
|
|
& (ctrPos
|
|
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
|
|
& _wrbypasses_1_io_hit_data_1_valid
|
|
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
|
|
& _wrbypasses_1_io_hit_data_0_valid)
|
|
? (ctrPos
|
|
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
|
|
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
|
|
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
|
|
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
|
|
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
|
|
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
wire taken =
|
|
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
wire [5:0] update_wdata_0 =
|
|
oldCtr == 6'h1F & taken
|
|
? 6'h1F
|
|
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21]
|
|
wire ctrPos_1 =
|
|
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92]
|
|
wire [5:0] oldCtr_1 =
|
|
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
|
|
& (ctrPos_1
|
|
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
|
|
& _wrbypasses_1_io_hit_data_1_valid
|
|
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
|
|
& _wrbypasses_1_io_hit_data_0_valid)
|
|
? (ctrPos_1
|
|
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
|
|
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
|
|
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
|
|
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
|
|
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
|
|
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92]
|
|
wire taken_1 =
|
|
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92]
|
|
wire [5:0] update_wdata_1 =
|
|
oldCtr_1 == 6'h1F & taken_1
|
|
? 6'h1F
|
|
: oldCtr_1 == 6'h20 & ~taken_1
|
|
? 6'h20
|
|
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:103:27, :104:30, :105:{8,21}, :106:{10,26,29}, :107:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21]
|
|
wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:105:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
if (io_req_valid) // @[src/main/scala/xiangshan/frontend/SC.scala:68:14]
|
|
s1_pc <= io_req_bits_pc; // @[src/main/scala/xiangshan/frontend/SC.scala:99:24]
|
|
end // always @(posedge)
|
|
`ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
`ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
`FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:1]; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
initial begin // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
`ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
`INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
|
|
_RANDOM[i[0]] = `RANDOM; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
end // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]}; // @[src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24]
|
|
`endif // RANDOMIZE_REG_INIT
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
`FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/SC.scala:66:7]
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
SRAMTemplate_35 table_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:71:21]
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_r_req_valid (io_req_valid),
|
|
.io_r_req_bits_setIdx (io_req_bits_pc[8:1]), // @[src/main/scala/xiangshan/frontend/SC.scala:89:{11,29}]
|
|
.io_r_resp_data_0 (_table_io_r_resp_data_0),
|
|
.io_r_resp_data_1 (_table_io_r_resp_data_1),
|
|
.io_r_resp_data_2 (_table_io_r_resp_data_2),
|
|
.io_r_resp_data_3 (_table_io_r_resp_data_3),
|
|
.io_w_req_valid (io_update_mask_0 | io_update_mask_1), // @[src/main/scala/xiangshan/frontend/SC.scala:130:36]
|
|
.io_w_req_bits_setIdx (io_update_pc[8:1]), // @[src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42]
|
|
.io_w_req_bits_data_0 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8]
|
|
.io_w_req_bits_data_1 (update_wdata_0), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8]
|
|
.io_w_req_bits_data_2 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8]
|
|
.io_w_req_bits_data_3 (update_wdata_1), // @[src/main/scala/xiangshan/frontend/BPU.scala:105:8]
|
|
.io_w_req_bits_waymask
|
|
({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0}) // @[src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29]
|
|
);
|
|
WrBypass_33 wrbypasses_0 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_0),
|
|
.io_write_idx (io_update_pc[8:1]), // @[src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42]
|
|
.io_write_data_0 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73]
|
|
.io_write_data_1 (_GEN | _GEN_0), // @[src/main/scala/chisel3/util/Mux.scala:30:73]
|
|
.io_write_way_mask_0
|
|
(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
.io_write_way_mask_1
|
|
(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
.io_hit (_wrbypasses_0_io_hit),
|
|
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
|
|
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
|
|
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
|
|
);
|
|
WrBypass_33 wrbypasses_1 ( // @[src/main/scala/xiangshan/frontend/SC.scala:139:42]
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_1),
|
|
.io_write_idx (io_update_pc[8:1]), // @[src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42]
|
|
.io_write_data_0 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73]
|
|
.io_write_data_1 (_GEN_1 | _GEN_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73]
|
|
.io_write_way_mask_0
|
|
(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92]
|
|
.io_write_way_mask_1
|
|
(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3), // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92]
|
|
.io_hit (_wrbypasses_1_io_hit),
|
|
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
|
|
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
|
|
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
|
|
);
|
|
assign io_resp_ctrs_0_0 =
|
|
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
|
|
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
assign io_resp_ctrs_0_1 =
|
|
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
|
|
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
assign io_resp_ctrs_1_0 =
|
|
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
|
|
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
assign io_resp_ctrs_1_1 =
|
|
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
|
|
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42]
|
|
endmodule
|
|
|