forked from OSchip/UnityChipVerification
1270 lines
127 KiB
Systemverilog
1270 lines
127 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
|
|
// Standard header to adapt well known macros for register randomization.
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_MEM_INIT
|
|
`endif // not def RANDOMIZE
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_REG_INIT
|
|
`endif // not def RANDOMIZE
|
|
|
|
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif // not def RANDOM
|
|
|
|
// Users can define INIT_RANDOM as general code that gets injected into the
|
|
// initializer block for modules with registers.
|
|
`ifndef INIT_RANDOM
|
|
`define INIT_RANDOM
|
|
`endif // not def INIT_RANDOM
|
|
|
|
// If using random initialization, you can also define RANDOMIZE_DELAY to
|
|
// customize the delay used, otherwise 0.002 is used.
|
|
`ifndef RANDOMIZE_DELAY
|
|
`define RANDOMIZE_DELAY 0.002
|
|
`endif // not def RANDOMIZE_DELAY
|
|
|
|
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
|
|
`ifndef INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE
|
|
`ifdef VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
|
|
`else // VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
|
|
`endif // VERILATOR
|
|
`else // RANDOMIZE
|
|
`define INIT_RANDOM_PROLOG_
|
|
`endif // RANDOMIZE
|
|
`endif // not def INIT_RANDOM_PROLOG_
|
|
|
|
// Include register initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_REG_
|
|
`define ENABLE_INITIAL_REG_
|
|
`endif // not def ENABLE_INITIAL_REG_
|
|
`endif // not def SYNTHESIS
|
|
|
|
// Include rmemory initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_MEM_
|
|
`define ENABLE_INITIAL_MEM_
|
|
`endif // not def ENABLE_INITIAL_MEM_
|
|
`endif // not def SYNTHESIS
|
|
|
|
module ITTage( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
input clock, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
input reset, // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
input [40:0] io_in_bits_s0_pc_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s2_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_s3_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s2_full_pred_0_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s2_full_pred_0_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s2_full_pred_1_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s2_full_pred_1_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s2_full_pred_2_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s2_full_pred_2_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s2_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s2_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s2_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s2_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_0_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_0_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_0_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_0_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_0_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_0_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_0_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_0_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_0_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_0_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_0_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_1_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_1_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_1_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_1_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_1_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_1_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_1_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_1_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_1_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_1_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_1_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_2_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_2_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_2_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_2_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_is_jalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_is_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_is_ret, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_2_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_3_br_taken_mask_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_3_br_taken_mask_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_3_slot_valids_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_3_slot_valids_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_3_targets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_3_targets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_3_jalr_target, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s3_full_pred_3_offsets_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_s3_full_pred_3_offsets_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [40:0] io_out_s3_full_pred_3_fallThroughAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_3_fallThroughErr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_3_is_br_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_s3_full_pred_3_hit, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [222:0] io_out_last_stage_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_brSlots_0_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output [3:0] io_out_last_stage_ftb_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_carry, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_isCall, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
output io_out_last_stage_ftb_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_s0_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_s1_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_s2_fire_0, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_s2_fire_1, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_s2_fire_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_s2_fire_3, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_update_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_update_bits_pc, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_update_bits_ftb_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_update_bits_ftb_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_update_bits_ftb_entry_isRet, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_update_bits_ftb_entry_isJalr, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_update_bits_cfi_idx_valid, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [3:0] io_update_bits_cfi_idx_bits, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_update_bits_jmp_taken, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input io_update_bits_mispred_mask_2, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [222:0] io_update_bits_meta, // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
input [40:0] io_update_bits_full_target // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
);
|
|
|
|
reg [2:0] resp_meta_allocate_bits_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:510:40]
|
|
reg resp_meta_allocate_valid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:509:40]
|
|
wire resp_meta_altDiffers; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:492:50]
|
|
wire _tables_4_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_4_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_4_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [40:0] _tables_4_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire _tables_3_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_3_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_3_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [40:0] _tables_3_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire _tables_2_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_2_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_2_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [40:0] _tables_2_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire _tables_1_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_1_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_1_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [40:0] _tables_1_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire _tables_0_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_0_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [1:0] _tables_0_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
wire [40:0] _tables_0_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
reg [7:0] tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24]
|
|
reg s2_resps_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_0_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_0_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [40:0] s2_resps_0_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg s2_resps_1_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_1_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_1_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [40:0] s2_resps_1_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg s2_resps_2_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_2_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_2_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [40:0] s2_resps_2_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg s2_resps_3_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_3_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_3_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [40:0] s2_resps_3_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg s2_resps_4_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_4_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [1:0] s2_resps_4_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg [40:0] s2_resps_4_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27]
|
|
reg s3_tageTaken_dup_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59]
|
|
reg s3_tageTaken_dup_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59]
|
|
reg s3_tageTaken_dup_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59]
|
|
reg s3_tageTaken_dup_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59]
|
|
reg [40:0] s3_tageTarget_dup_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59]
|
|
reg [40:0] s3_tageTarget_dup_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59]
|
|
reg [40:0] s3_tageTarget_dup_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59]
|
|
reg [40:0] s3_tageTarget_dup_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59]
|
|
reg [40:0] s3_providerTarget; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:390:39]
|
|
reg [40:0] s3_altProviderTarget; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:391:39]
|
|
reg s3_provided; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:392:39]
|
|
reg [2:0] s3_provider; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:393:39]
|
|
reg s3_altProvided; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:394:39]
|
|
reg [2:0] s3_altProvider; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:395:39]
|
|
reg s3_finalAltPred; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39]
|
|
reg s3_providerU; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:397:39]
|
|
reg [1:0] s3_providerCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39]
|
|
reg [1:0] s3_altProviderCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39]
|
|
wire updateValid =
|
|
io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isJalr
|
|
& ~(io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isRet)
|
|
& io_update_valid & ~io_update_bits_ftb_entry_tailSlot_sharing
|
|
& io_update_bits_jmp_taken & io_update_bits_cfi_idx_valid
|
|
& io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/FrontendBundle.scala:656:41, src/main/scala/xiangshan/frontend/ITTAGE.scala:410:23, :411:{46,69}]
|
|
assign resp_meta_altDiffers = s3_finalAltPred != s3_tageTaken_dup_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59, :396:39, :492:50]
|
|
reg [63:0] s2_allocLFSR_lfsr; // @[utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
wire _GEN =
|
|
updateValid & io_update_bits_mispred_mask_2
|
|
& ~(io_update_bits_meta[100]
|
|
& io_update_bits_meta[81:41] == io_update_bits_full_target
|
|
& io_update_bits_meta[90:89] == 2'h0); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :411:46, :415:40, :550:80, :551:47, :552:{38,41,59}]
|
|
reg tables_0_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
reg tables_0_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
reg tables_0_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
reg [40:0] tables_0_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
reg [40:0] tables_0_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
reg tables_0_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
reg [1:0] tables_0_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
reg tables_0_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
reg tables_0_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
reg [40:0] tables_0_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
reg [3:0] tables_0_io_update_folded_hist_r_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
reg tables_1_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
reg tables_1_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
reg tables_1_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
reg [40:0] tables_1_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
reg [40:0] tables_1_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
reg tables_1_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
reg [1:0] tables_1_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
reg tables_1_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
reg tables_1_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
reg [40:0] tables_1_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
reg [7:0] tables_1_io_update_folded_hist_r_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
reg tables_2_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
reg tables_2_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
reg tables_2_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
reg [40:0] tables_2_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
reg [40:0] tables_2_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
reg tables_2_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
reg [1:0] tables_2_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
reg tables_2_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
reg tables_2_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
reg [40:0] tables_2_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
reg [8:0] tables_2_io_update_folded_hist_r_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
reg [7:0] tables_2_io_update_folded_hist_r_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
reg tables_3_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
reg tables_3_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
reg tables_3_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
reg [40:0] tables_3_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
reg [40:0] tables_3_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
reg tables_3_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
reg [1:0] tables_3_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
reg tables_3_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
reg tables_3_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
reg [40:0] tables_3_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
reg [8:0] tables_3_io_update_folded_hist_r_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
reg [7:0] tables_3_io_update_folded_hist_r_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
reg tables_4_io_update_valid_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
reg tables_4_io_update_reset_u_REG; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
reg tables_4_io_update_correct_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
reg [40:0] tables_4_io_update_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
reg [40:0] tables_4_io_update_old_target_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
reg tables_4_io_update_alloc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
reg [1:0] tables_4_io_update_oldCtr_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
reg tables_4_io_update_uValid_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
reg tables_4_io_update_u_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
reg [40:0] tables_4_io_update_pc_r; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
reg [8:0] tables_4_io_update_folded_hist_r_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
reg [7:0] tables_4_io_update_folded_hist_r_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
if (reset) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
tickCtr <= 8'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24]
|
|
s2_allocLFSR_lfsr <= 64'h1234567887654321; // @[utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
end
|
|
else begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
if (&tickCtr) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17]
|
|
tickCtr <= 8'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24]
|
|
else if (_GEN) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:552:38]
|
|
if ((&tickCtr) & ~(io_update_bits_meta[86])) // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, :97:21, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :415:40, :554:46]
|
|
tickCtr <= 8'hFF; // @[src/main/scala/xiangshan/frontend/BPU.scala:95:27, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24]
|
|
else if (tickCtr == 8'h0 & io_update_bits_meta[86]) // @[src/main/scala/xiangshan/frontend/BPU.scala:96:30, :98:26, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :415:40]
|
|
tickCtr <= 8'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24]
|
|
else if (io_update_bits_meta[86]) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40]
|
|
tickCtr <= 8'(tickCtr - 8'h1); // @[src/main/scala/xiangshan/frontend/BPU.scala:99:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24]
|
|
else // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40]
|
|
tickCtr <= 8'(tickCtr + 8'h1); // @[src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:99:24, src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24]
|
|
end
|
|
if (s2_allocLFSR_lfsr == 64'h0) // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24]
|
|
s2_allocLFSR_lfsr <= 64'h1; // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18]
|
|
else // @[utility/src/main/scala/utility/LFSR64.scala:31:24]
|
|
s2_allocLFSR_lfsr <=
|
|
{s2_allocLFSR_lfsr[0] ^ s2_allocLFSR_lfsr[1] ^ s2_allocLFSR_lfsr[3]
|
|
^ s2_allocLFSR_lfsr[4],
|
|
s2_allocLFSR_lfsr[63:1]}; // @[utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51}]
|
|
end
|
|
end // always @(posedge, posedge)
|
|
wire [2:0] selectedInfo_res_1_first_tableIdx = {2'h0, s2_resps_1_valid}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
wire [2:0] selectedInfo_res_2_first_tableIdx =
|
|
s2_resps_2_valid ? 3'h2 : selectedInfo_res_1_first_tableIdx; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, :444:24, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
wire selectedInfo_res_hasOne = s2_resps_4_valid | s2_resps_3_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16]
|
|
wire selectedInfo_res_hasTwo = s2_resps_4_valid & s2_resps_3_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:146:40]
|
|
wire selectedInfo_res_1_hasOne = s2_resps_1_valid | s2_resps_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16]
|
|
wire [1:0] selectedInfo_res_1_first_ctr =
|
|
s2_resps_1_valid ? s2_resps_1_bits_ctr : s2_resps_0_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
wire [40:0] selectedInfo_res_1_first_target =
|
|
s2_resps_1_valid ? s2_resps_1_bits_target : s2_resps_0_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
wire selectedInfo_res_2_hasOne = s2_resps_2_valid | selectedInfo_res_1_hasOne; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16]
|
|
wire [1:0] selectedInfo_res_2_first_ctr =
|
|
s2_resps_2_valid ? s2_resps_2_bits_ctr : selectedInfo_res_1_first_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
wire [40:0] selectedInfo_res_2_first_target =
|
|
s2_resps_2_valid ? s2_resps_2_bits_target : selectedInfo_res_1_first_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
wire selectedInfo_hasOne = selectedInfo_res_hasOne | selectedInfo_res_2_hasOne; // @[utility/src/main/scala/utility/ParallelMux.scala:145:16]
|
|
wire selectedInfo_hasTwo =
|
|
selectedInfo_res_hasTwo | s2_resps_1_valid & s2_resps_0_valid | s2_resps_2_valid
|
|
& selectedInfo_res_1_hasOne | selectedInfo_res_hasOne & selectedInfo_res_2_hasOne; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:{28,40}]
|
|
wire [1:0] selectedInfo_first_ctr =
|
|
selectedInfo_res_hasOne
|
|
? (s2_resps_4_valid ? s2_resps_4_bits_ctr : s2_resps_3_bits_ctr)
|
|
: selectedInfo_res_2_first_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10]
|
|
wire [40:0] selectedInfo_first_target =
|
|
selectedInfo_res_hasOne
|
|
? (s2_resps_4_valid ? s2_resps_4_bits_target : s2_resps_3_bits_target)
|
|
: selectedInfo_res_2_first_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10]
|
|
wire _selectedInfo_T_91 = selectedInfo_res_hasOne & ~selectedInfo_res_hasTwo; // @[utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :150:{19,22}]
|
|
wire [40:0] selectedInfo_second_target =
|
|
(selectedInfo_res_hasOne
|
|
? 41'h0
|
|
: (s2_resps_2_valid
|
|
? 41'h0
|
|
: (s2_resps_1_valid ? 41'h0 : s2_resps_0_bits_target)
|
|
| (s2_resps_1_valid ? s2_resps_0_bits_target : 41'h0))
|
|
| (s2_resps_2_valid ? selectedInfo_res_1_first_target : 41'h0))
|
|
| (_selectedInfo_T_91 ? selectedInfo_res_2_first_target : 41'h0)
|
|
| (selectedInfo_res_hasTwo
|
|
? (s2_resps_4_valid ? 41'h0 : s2_resps_3_bits_target)
|
|
| (s2_resps_4_valid ? s2_resps_3_bits_target : 41'h0)
|
|
: 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19]
|
|
wire providerNull = selectedInfo_first_ctr == 2'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :453:39, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
wire _s2_tageTarget_T = providerNull & selectedInfo_hasTwo; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:453:39, :459:33, utility/src/main/scala/utility/ParallelMux.scala:146:28]
|
|
wire _s2_tageTarget_T_3 = selectedInfo_hasTwo & providerNull; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:453:39, :460:18, utility/src/main/scala/utility/ParallelMux.scala:146:28]
|
|
wire _s2_tageTaken_T_9 =
|
|
selectedInfo_hasOne & ~_s2_tageTarget_T | _s2_tageTarget_T_3 | ~selectedInfo_hasOne; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:459:{15,18,33}, :460:18, :461:6, utility/src/main/scala/utility/ParallelMux.scala:145:16]
|
|
wire [40:0] _s2_tageTarget_T_12 =
|
|
(selectedInfo_hasOne & ~_s2_tageTarget_T ? selectedInfo_first_target : 41'h0)
|
|
| (_s2_tageTarget_T_3 ? selectedInfo_second_target : 41'h0)
|
|
| (~selectedInfo_hasOne | providerNull & ~selectedInfo_hasTwo
|
|
? io_in_bits_resp_in_0_s2_full_pred_3_jalr_target
|
|
: 41'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :453:39, :459:33, :460:18, :461:6, :464:{15,18}, :466:{16,32,35}, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:28, :147:10]
|
|
wire _GEN_0 =
|
|
io_update_bits_meta[96] & io_update_bits_meta[90:89] == 2'h0
|
|
& io_update_bits_mispred_mask_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :415:40, :519:80, :520:25]
|
|
wire _GEN_1 = io_update_bits_meta[99:97] == 3'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :415:40, :533:30]
|
|
wire _GEN_2 = updateValid & io_update_bits_meta[100]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:411:46, :415:40, :417:33, :514:22, :515:38, :533:30]
|
|
wire _GEN_3 = io_update_bits_meta[99:97] == 3'h1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :533:30]
|
|
wire _GEN_4 = io_update_bits_meta[99:97] == 3'h2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :533:30]
|
|
wire _GEN_5 = io_update_bits_meta[99:97] == 3'h3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :533:30]
|
|
wire _GEN_6 = io_update_bits_meta[99:97] == 3'h4; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :533:30]
|
|
wire _updateU_T_2 =
|
|
io_update_bits_meta[92] ? ~io_update_bits_mispred_mask_2 : io_update_bits_meta[91]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :539:{31,78}]
|
|
wire _updateCorrect_T = io_update_bits_meta[81:41] == io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :540:61]
|
|
wire _GEN_7 = io_update_bits_meta[85:83] == 3'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :415:40, :557:34]
|
|
wire _GEN_8 = _GEN & io_update_bits_meta[86] & _GEN_7; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34]
|
|
wire updateMask_0 =
|
|
_GEN_8 | _GEN_2 & (_GEN_1 | _GEN_0 & io_update_bits_meta[95:93] == 3'h0); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :415:40, :417:33, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34]
|
|
wire _GEN_9 = io_update_bits_meta[85:83] == 3'h1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :557:34]
|
|
wire _GEN_10 = _GEN & io_update_bits_meta[86] & _GEN_9; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34]
|
|
wire updateMask_1 =
|
|
_GEN_10 | _GEN_2 & (_GEN_3 | _GEN_0 & io_update_bits_meta[95:93] == 3'h1); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :417:33, :444:24, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34]
|
|
wire _GEN_11 = io_update_bits_meta[85:83] == 3'h2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :557:34]
|
|
wire _GEN_12 = _GEN & io_update_bits_meta[86] & _GEN_11; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34]
|
|
wire updateMask_2 =
|
|
_GEN_12 | _GEN_2 & (_GEN_4 | _GEN_0 & io_update_bits_meta[95:93] == 3'h2); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :417:33, :444:24, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34]
|
|
wire _GEN_13 = io_update_bits_meta[85:83] == 3'h3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :557:34]
|
|
wire _GEN_14 = _GEN & io_update_bits_meta[86] & _GEN_13; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34]
|
|
wire updateMask_3 =
|
|
_GEN_14 | _GEN_2 & (_GEN_5 | _GEN_0 & io_update_bits_meta[95:93] == 3'h3); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :417:33, :444:24, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34]
|
|
wire _GEN_15 = io_update_bits_meta[85:83] == 3'h4; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :444:24, :557:34]
|
|
wire _GEN_16 = _GEN & io_update_bits_meta[86] & _GEN_15; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :557:34]
|
|
wire updateMask_4 =
|
|
_GEN_16 | _GEN_2 & (_GEN_6 | _GEN_0 & io_update_bits_meta[95:93] == 3'h4); // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :417:33, :444:24, :514:22, :515:38, :520:{25,43}, :523:36, :533:30, :552:79, :555:27, :557:34]
|
|
wire _GEN_17 = _GEN & io_update_bits_meta[86]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :514:22, :552:{38,79}, :555:27, :560:34]
|
|
wire [2:0] selectedInfo_first_tableIdx =
|
|
selectedInfo_res_hasOne
|
|
? (s2_resps_4_valid ? 3'h4 : 3'h3)
|
|
: selectedInfo_res_2_first_tableIdx; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, :444:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10]
|
|
wire [1:0] selectedInfo_second_ctr =
|
|
(selectedInfo_res_hasOne
|
|
? 2'h0
|
|
: (s2_resps_2_valid
|
|
? 2'h0
|
|
: (s2_resps_1_valid ? 2'h0 : s2_resps_0_bits_ctr)
|
|
| (s2_resps_1_valid ? s2_resps_0_bits_ctr : 2'h0))
|
|
| (s2_resps_2_valid ? selectedInfo_res_1_first_ctr : 2'h0))
|
|
| (_selectedInfo_T_91 ? selectedInfo_res_2_first_ctr : 2'h0)
|
|
| (selectedInfo_res_hasTwo
|
|
? (s2_resps_4_valid ? 2'h0 : s2_resps_3_bits_ctr)
|
|
| (s2_resps_4_valid ? s2_resps_3_bits_ctr : 2'h0)
|
|
: 2'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19]
|
|
wire [7:0] _s2_allocatableSlots_T_17 = 8'h1 << selectedInfo_first_tableIdx; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
wire [4:0] _GEN_18 = _s2_allocatableSlots_T_17[4:0] | _s2_allocatableSlots_T_17[5:1]; // @[src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53]
|
|
wire [4:0] _GEN_19 =
|
|
~({_GEN_18[4] | selectedInfo_first_tableIdx == 3'h6 | (&selectedInfo_first_tableIdx),
|
|
_GEN_18[3:0] | _s2_allocatableSlots_T_17[5:2] | _s2_allocatableSlots_T_17[6:3]
|
|
| _s2_allocatableSlots_T_17[7:4]} & {5{selectedInfo_hasOne}})
|
|
& {~s2_resps_4_valid & s2_resps_4_bits_u == 2'h0,
|
|
~s2_resps_3_valid & s2_resps_3_bits_u == 2'h0,
|
|
~s2_resps_2_valid & s2_resps_2_bits_u == 2'h0,
|
|
~s2_resps_1_valid & s2_resps_1_bits_u == 2'h0,
|
|
~s2_resps_0_valid & s2_resps_0_bits_u == 2'h0}; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, :503:{55,64,67,79,86}, :504:{5,55,61}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :145:16, :147:10]
|
|
wire [4:0] _GEN_20 = _GEN_19 & s2_allocLFSR_lfsr[4:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:503:86, :505:32, :507:60, utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
wire [2:0] s2_maskedEntry =
|
|
_GEN_20[0]
|
|
? 3'h0
|
|
: _GEN_20[1]
|
|
? 3'h1
|
|
: _GEN_20[2] ? 3'h2 : _GEN_20[3] ? 3'h3 : _GEN_20[4] ? 3'h4 : 3'h7; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :444:24, :507:60]
|
|
wire [7:0] _s2_allocEntry_T = {3'h0, _GEN_19} >> s2_maskedEntry; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :503:86, :508:47]
|
|
always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
if (io_s1_fire_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
s2_resps_0_valid <= _tables_0_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_0_bits_ctr <= _tables_0_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_0_bits_u <= _tables_0_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_0_bits_target <= _tables_0_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_1_valid <= _tables_1_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_1_bits_ctr <= _tables_1_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_1_bits_u <= _tables_1_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_1_bits_target <= _tables_1_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_2_valid <= _tables_2_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_2_bits_ctr <= _tables_2_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_2_bits_u <= _tables_2_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_2_bits_target <= _tables_2_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_3_valid <= _tables_3_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_3_bits_ctr <= _tables_3_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_3_bits_u <= _tables_3_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_3_bits_target <= _tables_3_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_4_valid <= _tables_4_io_resp_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_4_bits_ctr <= _tables_4_io_resp_bits_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_4_bits_u <= _tables_4_io_resp_bits_u; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
s2_resps_4_bits_target <= _tables_4_io_resp_bits_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21, :369:27]
|
|
end
|
|
if (io_s2_fire_0) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
s3_tageTaken_dup_0 <= _s2_tageTaken_T_9; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59]
|
|
s3_tageTarget_dup_0 <= _s2_tageTarget_T_12; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59]
|
|
end
|
|
if (io_s2_fire_1) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
s3_tageTaken_dup_1 <= _s2_tageTaken_T_9; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59]
|
|
s3_tageTarget_dup_1 <= _s2_tageTarget_T_12; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59]
|
|
end
|
|
if (io_s2_fire_2) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
s3_tageTaken_dup_2 <= _s2_tageTaken_T_9; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59]
|
|
s3_tageTarget_dup_2 <= _s2_tageTarget_T_12; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59]
|
|
end
|
|
if (io_s2_fire_3) begin // @[src/main/scala/xiangshan/frontend/BPU.scala:172:14]
|
|
s3_tageTaken_dup_3 <= _s2_tageTaken_T_9; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:388:59]
|
|
s3_tageTarget_dup_3 <= _s2_tageTarget_T_12; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:389:59]
|
|
s3_providerTarget <= selectedInfo_first_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:390:39, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
s3_altProviderTarget <= selectedInfo_second_target; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:391:39]
|
|
s3_provided <= selectedInfo_hasOne; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:392:39, utility/src/main/scala/utility/ParallelMux.scala:145:16]
|
|
s3_provider <= selectedInfo_first_tableIdx; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:393:39, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
s3_altProvided <= selectedInfo_hasTwo; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:394:39, utility/src/main/scala/utility/ParallelMux.scala:146:28]
|
|
s3_altProvider <=
|
|
(selectedInfo_res_hasOne | ~s2_resps_2_valid
|
|
? 3'h0
|
|
: selectedInfo_res_1_first_tableIdx)
|
|
| (_selectedInfo_T_91 ? selectedInfo_res_2_first_tableIdx : 3'h0)
|
|
| (selectedInfo_res_hasTwo
|
|
? (s2_resps_4_valid ? 3'h0 : 3'h3) | (s2_resps_4_valid ? 3'h3 : 3'h0)
|
|
: 3'h0); // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :369:27, :395:39, :444:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19]
|
|
s3_finalAltPred <= ~selectedInfo_hasTwo | selectedInfo_second_ctr[1]; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39, :468:{25,58}, utility/src/main/scala/utility/ParallelMux.scala:146:28]
|
|
s3_providerU <=
|
|
selectedInfo_res_hasOne
|
|
? (s2_resps_4_valid ? s2_resps_4_bits_u[0] : s2_resps_3_bits_u[0])
|
|
: s2_resps_2_valid
|
|
? s2_resps_2_bits_u[0]
|
|
: s2_resps_1_valid ? s2_resps_1_bits_u[0] : s2_resps_0_bits_u[0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:369:27, :397:39, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10]
|
|
s3_providerCtr <= selectedInfo_first_ctr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39, utility/src/main/scala/utility/ParallelMux.scala:147:10]
|
|
s3_altProviderCtr <= selectedInfo_second_ctr; // @[src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39]
|
|
resp_meta_allocate_valid_r <= |_GEN_19; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:503:86, :509:{40,61}]
|
|
resp_meta_allocate_bits_r <=
|
|
_s2_allocEntry_T[0]
|
|
? s2_maskedEntry
|
|
: _GEN_19[0]
|
|
? 3'h0
|
|
: _GEN_19[1]
|
|
? 3'h1
|
|
: _GEN_19[2] ? 3'h2 : _GEN_19[3] ? 3'h3 : _GEN_19[4] ? 3'h4 : 3'h7; // @[src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:349:40, :444:24, :503:86, :508:{27,47}, :510:40]
|
|
end
|
|
tables_0_io_update_valid_REG <= updateMask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41]
|
|
tables_0_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43]
|
|
if (updateMask_0) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34]
|
|
tables_0_io_update_correct_r <= _GEN_8 | _GEN_1 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45]
|
|
tables_0_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
tables_0_io_update_old_target_r <=
|
|
_GEN_1 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48]
|
|
tables_0_io_update_alloc_r <= _GEN_17 & _GEN_7; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43]
|
|
tables_0_io_update_oldCtr_r <=
|
|
_GEN_1 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44]
|
|
tables_0_io_update_uValid_r <= _GEN_8 | _GEN_2 & _GEN_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44]
|
|
tables_0_io_update_u_r <= ~_GEN_8 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39]
|
|
tables_0_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
tables_0_io_update_folded_hist_r_hist_12_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_12_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
end
|
|
tables_1_io_update_valid_REG <= updateMask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41]
|
|
tables_1_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43]
|
|
if (updateMask_1) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34]
|
|
tables_1_io_update_correct_r <= _GEN_10 | _GEN_3 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45]
|
|
tables_1_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
tables_1_io_update_old_target_r <=
|
|
_GEN_3 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48]
|
|
tables_1_io_update_alloc_r <= _GEN_17 & _GEN_9; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43]
|
|
tables_1_io_update_oldCtr_r <=
|
|
_GEN_3 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44]
|
|
tables_1_io_update_uValid_r <= _GEN_10 | _GEN_2 & _GEN_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44]
|
|
tables_1_io_update_u_r <= ~_GEN_10 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39]
|
|
tables_1_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
tables_1_io_update_folded_hist_r_hist_14_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_14_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
end
|
|
tables_2_io_update_valid_REG <= updateMask_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41]
|
|
tables_2_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43]
|
|
if (updateMask_2) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34]
|
|
tables_2_io_update_correct_r <= _GEN_12 | _GEN_4 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45]
|
|
tables_2_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
tables_2_io_update_old_target_r <=
|
|
_GEN_4 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48]
|
|
tables_2_io_update_alloc_r <= _GEN_17 & _GEN_11; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43]
|
|
tables_2_io_update_oldCtr_r <=
|
|
_GEN_4 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44]
|
|
tables_2_io_update_uValid_r <= _GEN_12 | _GEN_2 & _GEN_4; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44]
|
|
tables_2_io_update_u_r <= ~_GEN_12 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39]
|
|
tables_2_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
tables_2_io_update_folded_hist_r_hist_13_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_13_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
tables_2_io_update_folded_hist_r_hist_4_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_4_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
end
|
|
tables_3_io_update_valid_REG <= updateMask_3; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41]
|
|
tables_3_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43]
|
|
if (updateMask_3) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34]
|
|
tables_3_io_update_correct_r <= _GEN_14 | _GEN_5 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45]
|
|
tables_3_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
tables_3_io_update_old_target_r <=
|
|
_GEN_5 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48]
|
|
tables_3_io_update_alloc_r <= _GEN_17 & _GEN_13; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43]
|
|
tables_3_io_update_oldCtr_r <=
|
|
_GEN_5 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44]
|
|
tables_3_io_update_uValid_r <= _GEN_14 | _GEN_2 & _GEN_5; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44]
|
|
tables_3_io_update_u_r <= ~_GEN_14 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39]
|
|
tables_3_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
tables_3_io_update_folded_hist_r_hist_6_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_6_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
tables_3_io_update_folded_hist_r_hist_2_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_2_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
end
|
|
tables_4_io_update_valid_REG <= updateMask_4; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :576:41]
|
|
tables_4_io_update_reset_u_REG <= &tickCtr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24, :566:17, :577:43]
|
|
if (updateMask_4) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34]
|
|
tables_4_io_update_correct_r <= _GEN_16 | _GEN_6 & _updateCorrect_T; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :520:43, :533:30, :540:{32,61}, :552:79, :555:27, :557:34, :558:36, :578:45]
|
|
tables_4_io_update_target_r <= io_update_bits_full_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
tables_4_io_update_old_target_r <=
|
|
_GEN_6 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :542:33, :580:48]
|
|
tables_4_io_update_alloc_r <= _GEN_17 & _GEN_15; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :552:79, :555:27, :557:34, :560:34, :581:43]
|
|
tables_4_io_update_oldCtr_r <=
|
|
_GEN_6 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:415:40, :520:43, :533:30, :543:30, :582:44]
|
|
tables_4_io_update_uValid_r <= _GEN_16 | _GEN_2 & _GEN_6; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:417:33, :418:33, :514:22, :515:38, :533:30, :534:30, :552:79, :555:27, :557:34, :561:34, :584:44]
|
|
tables_4_io_update_u_r <= ~_GEN_16 & _updateU_T_2; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:514:22, :539:31, :552:79, :555:27, :557:34, :562:30, :585:39]
|
|
tables_4_io_update_pc_r <= io_update_bits_pc; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
tables_4_io_update_folded_hist_r_hist_10_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_10_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
tables_4_io_update_folded_hist_r_hist_3_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_3_folded_hist; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
end
|
|
end // always @(posedge)
|
|
`ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
`ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
`FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:79]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
initial begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
`ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
`INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
for (logic [6:0] i = 7'h0; i < 7'h50; i += 7'h1) begin
|
|
_RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
end // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
tickCtr = _RANDOM[7'hF][25:18]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24]
|
|
s2_resps_0_valid = _RANDOM[7'hF][26]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24, :369:27]
|
|
s2_resps_0_bits_ctr = _RANDOM[7'hF][28:27]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24, :369:27]
|
|
s2_resps_0_bits_u = _RANDOM[7'hF][30:29]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24, :369:27]
|
|
s2_resps_0_bits_target = {_RANDOM[7'hF][31], _RANDOM[7'h10], _RANDOM[7'h11][7:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :364:24, :369:27]
|
|
s2_resps_1_valid = _RANDOM[7'h11][8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_1_bits_ctr = _RANDOM[7'h11][10:9]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_1_bits_u = _RANDOM[7'h11][12:11]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_1_bits_target = {_RANDOM[7'h11][31:13], _RANDOM[7'h12][21:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_2_valid = _RANDOM[7'h12][22]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_2_bits_ctr = _RANDOM[7'h12][24:23]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_2_bits_u = _RANDOM[7'h12][26:25]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_2_bits_target =
|
|
{_RANDOM[7'h12][31:27], _RANDOM[7'h13], _RANDOM[7'h14][3:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_3_valid = _RANDOM[7'h14][4]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_3_bits_ctr = _RANDOM[7'h14][6:5]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_3_bits_u = _RANDOM[7'h14][8:7]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_3_bits_target = {_RANDOM[7'h14][31:9], _RANDOM[7'h15][17:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_4_valid = _RANDOM[7'h15][18]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_4_bits_ctr = _RANDOM[7'h15][20:19]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_4_bits_u = _RANDOM[7'h15][22:21]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s2_resps_4_bits_target = {_RANDOM[7'h15][31:23], _RANDOM[7'h16]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :369:27]
|
|
s3_tageTaken_dup_0 = _RANDOM[7'h1A][27]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59]
|
|
s3_tageTaken_dup_1 = _RANDOM[7'h1A][28]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59]
|
|
s3_tageTaken_dup_2 = _RANDOM[7'h1A][29]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59]
|
|
s3_tageTaken_dup_3 = _RANDOM[7'h1A][30]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59]
|
|
s3_tageTarget_dup_0 = {_RANDOM[7'h1A][31], _RANDOM[7'h1B], _RANDOM[7'h1C][7:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59]
|
|
s3_tageTarget_dup_1 = {_RANDOM[7'h1C][31:8], _RANDOM[7'h1D][16:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :389:59]
|
|
s3_tageTarget_dup_2 = {_RANDOM[7'h1D][31:17], _RANDOM[7'h1E][25:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :389:59]
|
|
s3_tageTarget_dup_3 =
|
|
{_RANDOM[7'h1E][31:26], _RANDOM[7'h1F], _RANDOM[7'h20][2:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :389:59]
|
|
s3_providerTarget = {_RANDOM[7'h20][31:3], _RANDOM[7'h21][11:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :389:59, :390:39]
|
|
s3_altProviderTarget = {_RANDOM[7'h21][31:12], _RANDOM[7'h22][20:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :390:39, :391:39]
|
|
s3_provided = _RANDOM[7'h22][21]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :392:39]
|
|
s3_provider = _RANDOM[7'h22][24:22]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :393:39]
|
|
s3_altProvided = _RANDOM[7'h22][25]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :394:39]
|
|
s3_altProvider = _RANDOM[7'h22][28:26]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :395:39]
|
|
s3_finalAltPred = _RANDOM[7'h22][29]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :396:39]
|
|
s3_providerU = _RANDOM[7'h22][30]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :397:39]
|
|
s3_providerCtr = {_RANDOM[7'h22][31], _RANDOM[7'h23][0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :391:39, :398:39]
|
|
s3_altProviderCtr = _RANDOM[7'h23][2:1]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :398:39, :399:39]
|
|
s2_allocLFSR_lfsr = {_RANDOM[7'h23][31:3], _RANDOM[7'h24], _RANDOM[7'h25][2:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :398:39, utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
resp_meta_allocate_valid_r = _RANDOM[7'h25][3]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :509:40, utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
resp_meta_allocate_bits_r = _RANDOM[7'h25][6:4]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :510:40, utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
tables_0_io_update_valid_REG = _RANDOM[7'h25][7]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
tables_0_io_update_reset_u_REG = _RANDOM[7'h25][8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :577:43, utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
tables_0_io_update_correct_r = _RANDOM[7'h25][9]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :578:45, utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
tables_0_io_update_target_r = {_RANDOM[7'h25][31:10], _RANDOM[7'h26][18:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
tables_0_io_update_old_target_r = {_RANDOM[7'h26][31:19], _RANDOM[7'h27][27:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48]
|
|
tables_0_io_update_alloc_r = _RANDOM[7'h27][28]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43]
|
|
tables_0_io_update_oldCtr_r = _RANDOM[7'h27][30:29]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44]
|
|
tables_0_io_update_uValid_r = _RANDOM[7'h27][31]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44]
|
|
tables_0_io_update_u_r = _RANDOM[7'h28][0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :585:39]
|
|
tables_0_io_update_pc_r = {_RANDOM[7'h28][31:1], _RANDOM[7'h29][9:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :585:39, :586:40]
|
|
tables_0_io_update_folded_hist_r_hist_12_folded_hist = _RANDOM[7'h2A][27:24]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49]
|
|
tables_1_io_update_valid_REG = _RANDOM[7'h2D][30]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41]
|
|
tables_1_io_update_reset_u_REG = _RANDOM[7'h2D][31]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :577:43]
|
|
tables_1_io_update_correct_r = _RANDOM[7'h2E][0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :578:45]
|
|
tables_1_io_update_target_r = {_RANDOM[7'h2E][31:1], _RANDOM[7'h2F][9:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :578:45, :579:44]
|
|
tables_1_io_update_old_target_r = {_RANDOM[7'h2F][31:10], _RANDOM[7'h30][18:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48]
|
|
tables_1_io_update_alloc_r = _RANDOM[7'h30][19]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43]
|
|
tables_1_io_update_oldCtr_r = _RANDOM[7'h30][21:20]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44]
|
|
tables_1_io_update_uValid_r = _RANDOM[7'h30][22]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44]
|
|
tables_1_io_update_u_r = _RANDOM[7'h30][23]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :585:39]
|
|
tables_1_io_update_pc_r =
|
|
{_RANDOM[7'h30][31:24], _RANDOM[7'h31], _RANDOM[7'h32][0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :586:40]
|
|
tables_1_io_update_folded_hist_r_hist_14_folded_hist =
|
|
{_RANDOM[7'h32][31:30], _RANDOM[7'h33][5:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :586:40, :588:49]
|
|
tables_2_io_update_valid_REG = _RANDOM[7'h36][21]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41]
|
|
tables_2_io_update_reset_u_REG = _RANDOM[7'h36][22]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :577:43]
|
|
tables_2_io_update_correct_r = _RANDOM[7'h36][23]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :578:45]
|
|
tables_2_io_update_target_r =
|
|
{_RANDOM[7'h36][31:24], _RANDOM[7'h37], _RANDOM[7'h38][0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :579:44]
|
|
tables_2_io_update_old_target_r = {_RANDOM[7'h38][31:1], _RANDOM[7'h39][9:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48]
|
|
tables_2_io_update_alloc_r = _RANDOM[7'h39][10]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43]
|
|
tables_2_io_update_oldCtr_r = _RANDOM[7'h39][12:11]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44]
|
|
tables_2_io_update_uValid_r = _RANDOM[7'h39][13]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44]
|
|
tables_2_io_update_u_r = _RANDOM[7'h39][14]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :585:39]
|
|
tables_2_io_update_pc_r = {_RANDOM[7'h39][31:15], _RANDOM[7'h3A][23:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :586:40]
|
|
tables_2_io_update_folded_hist_r_hist_13_folded_hist =
|
|
{_RANDOM[7'h3B][31:29], _RANDOM[7'h3C][5:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49]
|
|
tables_2_io_update_folded_hist_r_hist_4_folded_hist = _RANDOM[7'h3E][8:1]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49]
|
|
tables_3_io_update_valid_REG = _RANDOM[7'h3F][12]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41]
|
|
tables_3_io_update_reset_u_REG = _RANDOM[7'h3F][13]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :577:43]
|
|
tables_3_io_update_correct_r = _RANDOM[7'h3F][14]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :578:45]
|
|
tables_3_io_update_target_r = {_RANDOM[7'h3F][31:15], _RANDOM[7'h40][23:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :579:44]
|
|
tables_3_io_update_old_target_r =
|
|
{_RANDOM[7'h40][31:24], _RANDOM[7'h41], _RANDOM[7'h42][0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48]
|
|
tables_3_io_update_alloc_r = _RANDOM[7'h42][1]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43]
|
|
tables_3_io_update_oldCtr_r = _RANDOM[7'h42][3:2]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44]
|
|
tables_3_io_update_uValid_r = _RANDOM[7'h42][4]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44]
|
|
tables_3_io_update_u_r = _RANDOM[7'h42][5]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :585:39]
|
|
tables_3_io_update_pc_r = {_RANDOM[7'h42][31:6], _RANDOM[7'h43][14:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :586:40]
|
|
tables_3_io_update_folded_hist_r_hist_6_folded_hist = _RANDOM[7'h46][16:8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49]
|
|
tables_3_io_update_folded_hist_r_hist_2_folded_hist = _RANDOM[7'h47][15:8]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49]
|
|
tables_4_io_update_valid_REG = _RANDOM[7'h48][3]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41]
|
|
tables_4_io_update_reset_u_REG = _RANDOM[7'h48][4]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :577:43]
|
|
tables_4_io_update_correct_r = _RANDOM[7'h48][5]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :578:45]
|
|
tables_4_io_update_target_r = {_RANDOM[7'h48][31:6], _RANDOM[7'h49][14:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :576:41, :579:44]
|
|
tables_4_io_update_old_target_r = {_RANDOM[7'h49][31:15], _RANDOM[7'h4A][23:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :579:44, :580:48]
|
|
tables_4_io_update_alloc_r = _RANDOM[7'h4A][24]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :581:43]
|
|
tables_4_io_update_oldCtr_r = _RANDOM[7'h4A][26:25]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :582:44]
|
|
tables_4_io_update_uValid_r = _RANDOM[7'h4A][27]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :584:44]
|
|
tables_4_io_update_u_r = _RANDOM[7'h4A][28]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :585:39]
|
|
tables_4_io_update_pc_r =
|
|
{_RANDOM[7'h4A][31:29], _RANDOM[7'h4B], _RANDOM[7'h4C][5:0]}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :580:48, :586:40]
|
|
tables_4_io_update_folded_hist_r_hist_10_folded_hist = _RANDOM[7'h4E][8:0]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49]
|
|
tables_4_io_update_folded_hist_r_hist_3_folded_hist = _RANDOM[7'h4F][30:23]; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :588:49]
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
tickCtr = 8'h0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:364:24]
|
|
s2_allocLFSR_lfsr = 64'h1234567887654321; // @[utility/src/main/scala/utility/LFSR64.scala:27:33]
|
|
end
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
`FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
ITTageTable tables_0 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_12_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_12_folded_hist),
|
|
.io_resp_valid (_tables_0_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_0_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_0_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_0_io_resp_bits_target),
|
|
.io_update_pc (tables_0_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
.io_update_folded_hist_hist_12_folded_hist
|
|
(tables_0_io_update_folded_hist_r_hist_12_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
.io_update_valid (tables_0_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
.io_update_correct (tables_0_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
.io_update_alloc (tables_0_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
.io_update_oldCtr (tables_0_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
.io_update_uValid (tables_0_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
.io_update_u (tables_0_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
.io_update_reset_u (tables_0_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
.io_update_target (tables_0_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
.io_update_old_target (tables_0_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
);
|
|
ITTageTable_1 tables_1 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_14_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_14_folded_hist),
|
|
.io_resp_valid (_tables_1_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_1_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_1_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_1_io_resp_bits_target),
|
|
.io_update_pc (tables_1_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
.io_update_folded_hist_hist_14_folded_hist
|
|
(tables_1_io_update_folded_hist_r_hist_14_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
.io_update_valid (tables_1_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
.io_update_correct (tables_1_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
.io_update_alloc (tables_1_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
.io_update_oldCtr (tables_1_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
.io_update_uValid (tables_1_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
.io_update_u (tables_1_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
.io_update_reset_u (tables_1_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
.io_update_target (tables_1_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
.io_update_old_target (tables_1_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
);
|
|
ITTageTable_2 tables_2 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_13_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_13_folded_hist),
|
|
.io_req_bits_folded_hist_hist_4_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_4_folded_hist),
|
|
.io_resp_valid (_tables_2_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_2_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_2_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_2_io_resp_bits_target),
|
|
.io_update_pc (tables_2_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
.io_update_folded_hist_hist_13_folded_hist
|
|
(tables_2_io_update_folded_hist_r_hist_13_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
.io_update_folded_hist_hist_4_folded_hist
|
|
(tables_2_io_update_folded_hist_r_hist_4_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
.io_update_valid (tables_2_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
.io_update_correct (tables_2_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
.io_update_alloc (tables_2_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
.io_update_oldCtr (tables_2_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
.io_update_uValid (tables_2_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
.io_update_u (tables_2_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
.io_update_reset_u (tables_2_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
.io_update_target (tables_2_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
.io_update_old_target (tables_2_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
);
|
|
ITTageTable_3 tables_3 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_6_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_6_folded_hist),
|
|
.io_req_bits_folded_hist_hist_2_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_2_folded_hist),
|
|
.io_resp_valid (_tables_3_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_3_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_3_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_3_io_resp_bits_target),
|
|
.io_update_pc (tables_3_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
.io_update_folded_hist_hist_6_folded_hist
|
|
(tables_3_io_update_folded_hist_r_hist_6_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
.io_update_folded_hist_hist_2_folded_hist
|
|
(tables_3_io_update_folded_hist_r_hist_2_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
.io_update_valid (tables_3_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
.io_update_correct (tables_3_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
.io_update_alloc (tables_3_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
.io_update_oldCtr (tables_3_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
.io_update_uValid (tables_3_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
.io_update_u (tables_3_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
.io_update_reset_u (tables_3_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
.io_update_target (tables_3_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
.io_update_old_target (tables_3_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
);
|
|
ITTageTable_4 tables_4 ( // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:354:21]
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_10_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_10_folded_hist),
|
|
.io_req_bits_folded_hist_hist_3_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_3_folded_hist),
|
|
.io_resp_valid (_tables_4_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_4_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_4_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_4_io_resp_bits_target),
|
|
.io_update_pc (tables_4_io_update_pc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:586:40]
|
|
.io_update_folded_hist_hist_10_folded_hist
|
|
(tables_4_io_update_folded_hist_r_hist_10_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
.io_update_folded_hist_hist_3_folded_hist
|
|
(tables_4_io_update_folded_hist_r_hist_3_folded_hist), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:588:49]
|
|
.io_update_valid (tables_4_io_update_valid_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:576:41]
|
|
.io_update_correct (tables_4_io_update_correct_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:578:45]
|
|
.io_update_alloc (tables_4_io_update_alloc_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:581:43]
|
|
.io_update_oldCtr (tables_4_io_update_oldCtr_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:582:44]
|
|
.io_update_uValid (tables_4_io_update_uValid_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:584:44]
|
|
.io_update_u (tables_4_io_update_u_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:585:39]
|
|
.io_update_reset_u (tables_4_io_update_reset_u_REG), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:577:43]
|
|
.io_update_target (tables_4_io_update_target_r), // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:579:44]
|
|
.io_update_old_target (tables_4_io_update_old_target_r) // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:580:48]
|
|
);
|
|
assign io_out_s2_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_targets_1 = io_in_bits_resp_in_0_s2_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_jalr_target =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_jalr_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_targets_1 = io_in_bits_resp_in_0_s2_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_jalr_target =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_jalr_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_jalr_target =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_jalr_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_is_jalr = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_is_call = io_in_bits_resp_in_0_s2_full_pred_2_is_call; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_is_ret = io_in_bits_resp_in_0_s2_full_pred_2_is_ret; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_last_may_be_rvi_call =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_targets_1 = io_in_bits_resp_in_0_s2_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_jalr_target =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_jalr_target; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_fallThroughErr =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_targets_1 = io_in_bits_resp_in_0_s3_full_pred_0_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_jalr_target =
|
|
s3_tageTaken_dup_0
|
|
? s3_tageTarget_dup_0
|
|
: io_in_bits_resp_in_0_s3_full_pred_0_jalr_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59, :484:26, :485:24]
|
|
assign io_out_s3_full_pred_0_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_fallThroughErr =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_is_br_sharing =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_targets_1 = io_in_bits_resp_in_0_s3_full_pred_1_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_jalr_target =
|
|
s3_tageTaken_dup_1
|
|
? s3_tageTarget_dup_1
|
|
: io_in_bits_resp_in_0_s3_full_pred_1_jalr_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59, :484:26, :485:24]
|
|
assign io_out_s3_full_pred_1_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_fallThroughErr =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_is_br_sharing =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_jalr_target =
|
|
s3_tageTaken_dup_2
|
|
? s3_tageTarget_dup_2
|
|
: io_in_bits_resp_in_0_s3_full_pred_2_jalr_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59, :484:26, :485:24]
|
|
assign io_out_s3_full_pred_2_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_fallThroughErr =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_is_jalr = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_is_call = io_in_bits_resp_in_0_s3_full_pred_2_is_call; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_is_ret = io_in_bits_resp_in_0_s3_full_pred_2_is_ret; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_is_br_sharing =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_targets_1 = io_in_bits_resp_in_0_s3_full_pred_3_targets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_jalr_target =
|
|
s3_tageTaken_dup_3
|
|
? s3_tageTarget_dup_3
|
|
: io_in_bits_resp_in_0_s3_full_pred_3_jalr_target; // @[src/main/scala/xiangshan/frontend/BPU.scala:174:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :389:59, :484:26, :485:24]
|
|
assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_fallThroughErr =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_is_br_sharing =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_meta =
|
|
{122'h0,
|
|
s3_provided,
|
|
s3_provider,
|
|
s3_altProvided,
|
|
s3_altProvider,
|
|
resp_meta_altDiffers,
|
|
s3_providerU,
|
|
s3_providerCtr,
|
|
s3_altProviderCtr,
|
|
resp_meta_allocate_valid_r,
|
|
resp_meta_allocate_bits_r,
|
|
s3_tageTaken_dup_3,
|
|
s3_providerTarget,
|
|
s3_altProviderTarget}; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7, :388:59, :390:39, :391:39, :392:39, :393:39, :394:39, :395:39, :397:39, :398:39, :399:39, :404:26, :492:50, :509:40, :510:40]
|
|
assign io_out_last_stage_ftb_entry_valid =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_brSlots_0_offset =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_brSlots_0_lower =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_brSlots_0_sharing =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_brSlots_0_valid =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_tailSlot_offset =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_tailSlot_lower =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_tailSlot_tarStat =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_tailSlot_sharing =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_tailSlot_valid =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_pftAddr =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_carry =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_carry; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_isCall =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_isRet =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_isJalr =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_always_taken_0 =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
assign io_out_last_stage_ftb_entry_always_taken_1 =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/ITTAGE.scala:348:7]
|
|
endmodule
|
|
|