forked from xuos/xiuos
413 lines
16 KiB
C
413 lines
16 KiB
C
/*
|
|
* Copyright 2017 NXP
|
|
* All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
/**
|
|
* @file board.c
|
|
* @brief relative configure for xidatong
|
|
* @version 2.0
|
|
* @author AIIT XUOS Lab
|
|
* @date 2022.03.15
|
|
*/
|
|
|
|
/*************************************************
|
|
File name: board.c
|
|
Description: support imxrt1052-board init function
|
|
Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
|
|
History:
|
|
1. Date: 2022-03-15
|
|
Author: AIIT XUOS Lab
|
|
Modification:
|
|
1. support imxrt1052-board MPU、clock、memory init
|
|
2. support imxrt1052-board uart、sdio driver init
|
|
*************************************************/
|
|
|
|
#include "fsl_common.h"
|
|
#include "board.h"
|
|
#include "pin_mux.h"
|
|
|
|
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
|
#include "fsl_lpi2c.h"
|
|
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
|
#include "fsl_iomuxc.h"
|
|
#include "fsl_gpio.h"
|
|
#include "fsl_lpuart.h"
|
|
|
|
#ifdef BSP_USING_GPIO
|
|
#include <connect_gpio.h>
|
|
#endif
|
|
|
|
#ifdef BSP_USING_LPUART
|
|
#include <connect_uart.h>
|
|
#endif
|
|
|
|
#ifdef BSP_USING_I2C
|
|
#include <connect_i2c.h>
|
|
#endif
|
|
|
|
#ifdef BSP_USING_CH438
|
|
#include <connect_ch438.h>
|
|
#endif
|
|
|
|
#ifdef BSP_USING_SDIO
|
|
#include <connect_sdio.h>
|
|
#endif
|
|
|
|
#ifdef BSP_USING_USB
|
|
#include <connect_usb.h>
|
|
#endif
|
|
|
|
#ifdef BSP_USING_WDT
|
|
#include <connect_wdt.h>
|
|
#endif
|
|
|
|
#ifdef BSP_USING_SEMC
|
|
extern status_t BOARD_InitSEMC(void);
|
|
#ifdef BSP_USING_EXTSRAM
|
|
extern int ExtSramInit(void);
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_LWIP
|
|
extern int ETH_BSP_Config();
|
|
#endif
|
|
|
|
#ifdef BSP_USING_LCD
|
|
extern int Imxrt1052HwLcdInit(void);
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TOUCH
|
|
extern int HwTouchInit();
|
|
#endif
|
|
|
|
void ImxrtMsDelay(uint32 ms)
|
|
{
|
|
uint64 ticks = 0;
|
|
uint32 told, tnow, tcnt = 0;
|
|
uint32 reload = SysTick->LOAD;
|
|
|
|
ticks = ((uint64)ms * ((uint64)reload + 1) * TICK_PER_SECOND) / 1000;
|
|
told = SysTick->VAL;
|
|
|
|
//KPrintf("%s reload %u ms %u ticks %u told %u\n", __func__, reload, ms, ticks, told);
|
|
|
|
while (1) {
|
|
tnow = SysTick->VAL;
|
|
if (tnow != told) {
|
|
if (tnow < told) {
|
|
tcnt += told - tnow;
|
|
} else {
|
|
tcnt += reload - tnow + told;
|
|
}
|
|
told = tnow;
|
|
if (tcnt >= ticks) {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
|
|
{
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
}
|
|
|
|
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
|
|
{
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7,
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
|
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
|
}
|
|
|
|
/* MPU configuration. */
|
|
void BOARD_ConfigMPU(void)
|
|
{
|
|
/* Disable I cache and D cache */
|
|
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
|
|
{
|
|
SCB_DisableICache();
|
|
}
|
|
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
|
|
{
|
|
SCB_DisableDCache();
|
|
}
|
|
|
|
/* Disable MPU */
|
|
ARM_MPU_Disable();
|
|
|
|
/* MPU configure:
|
|
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
|
|
* SubRegionDisable, Size)
|
|
* API in mpu_armv7.h.
|
|
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
|
|
* disabled.
|
|
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
|
|
* Privileged mode.
|
|
* Use MACROS defined in mpu_armv7.h:
|
|
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
|
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
|
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
|
|
* 0 x 0 0 Strongly Ordered shareable
|
|
* 0 x 0 1 Device shareable
|
|
* 0 0 1 0 Normal not shareable Outer and inner write
|
|
* through no write allocate
|
|
* 0 0 1 1 Normal not shareable Outer and inner write
|
|
* back no write allocate
|
|
* 0 1 1 0 Normal shareable Outer and inner write
|
|
* through no write allocate
|
|
* 0 1 1 1 Normal shareable Outer and inner write
|
|
* back no write allocate
|
|
* 1 0 0 0 Normal not shareable outer and inner
|
|
* noncache
|
|
* 1 1 0 0 Normal shareable outer and inner
|
|
* noncache
|
|
* 1 0 1 1 Normal not shareable outer and inner write
|
|
* back write/read acllocate
|
|
* 1 1 1 1 Normal shareable outer and inner write
|
|
* back write/read acllocate
|
|
* 2 x 0 0 Device not shareable
|
|
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
|
|
* policy.
|
|
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
|
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
|
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
|
|
* mpu_armv7.h.
|
|
*/
|
|
|
|
/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
|
|
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
|
|
|
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
|
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
|
|
|
/* Region 2 setting */
|
|
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
|
/* Setting Memory with Normal type, not shareable, outer/inner write back. */
|
|
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
|
|
#else
|
|
/* Setting Memory with Device type, not shareable, non-cacheable. */
|
|
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64MB);
|
|
#endif
|
|
|
|
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
|
|
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
|
|
|
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
|
|
|
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
|
|
|
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
|
|
|
/* The define sets the cacheable memory to shareable,
|
|
* this suggestion is referred from chapter 2.2.1 Memory regions,
|
|
* types and attributes in Cortex-M7 Devices, Generic User Guide */
|
|
#if defined(SDRAM_IS_SHAREABLE)
|
|
/* Region 7 setting: Memory with Normal type, shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
|
#else
|
|
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
|
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
|
#endif
|
|
|
|
/* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
|
|
* accessed by cache can be put here */
|
|
/* Memory with Normal type, not shareable, non-cacheable */
|
|
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
|
|
|
|
/* Enable MPU */
|
|
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
|
|
|
/* Enable I cache and D cache */
|
|
SCB_EnableDCache();
|
|
SCB_EnableICache();
|
|
}
|
|
|
|
/* This is the timer interrupt service routine. */
|
|
void SysTick_Handler(int irqn, void *arg)
|
|
{
|
|
TickAndTaskTimesliceUpdate();
|
|
}
|
|
|
|
struct InitSequenceDesc _board_init[] =
|
|
{
|
|
#ifdef BSP_USING_GPIO
|
|
{ "hw_pin", Imxrt1052HwGpioInit },
|
|
#endif
|
|
|
|
#ifdef BSP_USING_CH438
|
|
{"ch438", Imxrt1052HwCh438Init()},
|
|
#endif
|
|
|
|
#ifdef BSP_USING_SDIO
|
|
{ "sdio", Imxrt1052HwSdioInit },
|
|
#endif
|
|
|
|
#ifdef BSP_USING_USB
|
|
#ifdef BSP_USING_NXP_USBH
|
|
{ "nxp hw usb", Imxrt1052HwUsbHostInit },
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_I2C
|
|
{ "hw_i2c", Imxrt1052HwI2cInit },
|
|
#endif
|
|
|
|
#ifdef BSP_USING_LCD
|
|
{ "hw_lcd", Imxrt1052HwLcdInit },
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TOUCH
|
|
{"touch", HwTouchInit },
|
|
#endif
|
|
|
|
#ifdef BSP_USING_LWIP
|
|
{"ETH_BSP", ETH_BSP_Config},
|
|
#endif
|
|
|
|
#ifdef BSP_USING_WDT
|
|
{ "hw_wdt", Imxrt1052HwWdgInit },
|
|
#endif
|
|
{ " NONE ",NONE },
|
|
};
|
|
|
|
/**
|
|
* This function will initial imxrt1050 board.
|
|
*/
|
|
void InitBoardHardware()
|
|
{
|
|
int i = 0;
|
|
int ret = 0;
|
|
|
|
BOARD_ConfigMPU();
|
|
BOARD_InitPins();
|
|
BOARD_BootClockRUN();
|
|
|
|
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
|
|
|
|
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
|
|
|
|
#ifdef BSP_USING_SEMC
|
|
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
|
|
/* Set semc clock to 163.86 MHz */
|
|
CLOCK_SetMux(kCLOCK_SemcMux, 1);
|
|
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
|
|
|
|
if (BOARD_InitSEMC() != kStatus_Success) {
|
|
KPrintf("\r\n SEMC Init Failed\r\n");
|
|
}
|
|
#ifdef MEM_EXTERN_SRAM
|
|
else {
|
|
ExtSramInit();
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_LPUART
|
|
Imxrt1052HwUartInit();
|
|
#endif
|
|
|
|
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
|
KPrintf("\nconsole init completed.\n");
|
|
KPrintf("board initialization......\n");
|
|
|
|
for(i = 0; _board_init[i].fn != NONE; i++) {
|
|
ret = _board_init[i].fn();
|
|
KPrintf("initialize %s %s\n",_board_init[i].fn_name, ret == 0 ? "success" : "failed");
|
|
}
|
|
KPrintf("board init done.\n");
|
|
KPrintf("start kernel...\n");
|
|
}
|
|
|