forked from xuos/xiuos
57 lines
1.2 KiB
Plaintext
57 lines
1.2 KiB
Plaintext
FSP Configuration
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Board "RZ/V2L Evaluation Kit (SMARC)"
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R9A07G054L23GBG_CM33
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part_number: R9A07G054L23GBG_CM33
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rom_size_bytes: 0
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ram_size_bytes: 131072
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package_style: LFBGA
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package_pins: 456
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RZV2L
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series: 2
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RZV2L Family
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RZ/V2L Common
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Secure stack size (bytes): 0x200
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Main stack size (bytes): 0x200
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Heap size (bytes): 0
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MCU Vcc (mV): 3300
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Parameter checking: Disabled
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Assert Failures: Return FSP_ERR_ASSERTION
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Error Log: No Error Log
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PFS Protect: Enabled
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C Runtime Initialization : Enabled
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Clocks
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OSC 24000000Hz
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ICLK 1200000000Hz
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I2CLK 200000000Hz
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GCLK 500000000Hz
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S0CLK 12000Hz
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SPI0CLK 200000000Hz
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SPI1CLK 100000000Hz
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SD0CLK 533000000Hz
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SD1CLK 533000000Hz
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M0CLK 200000000Hz
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M1CLK 3000000000Hz
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M2CLK 266500000Hz
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M3CLK 3000000000Hz
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M4CLK 16656000Hz
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HPCLK 250000000Hz
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TSUCLK 80000000Hz
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ZTCLK 100000000Hz
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P0CLK 100000000Hz
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P1CLK 200000000Hz
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P2CLK 100000000Hz
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ATCLK 400000000Hz
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User Events
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Module "I/O Port Driver on r_ioport"
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Parameter Checking: Default (BSP)
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HAL
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Instance "g_ioport I/O Port Driver on r_ioport"
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Name: g_ioport
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