forked from xuos/xiuos
62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-09-09 WCH the first version
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*/
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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/* bytes of register width */
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//#define ARCH_RISCV_FPU
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#define ARCH_RISCV_FPU_S
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#ifdef ARCH_CPU_64BIT
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#define STORE sd
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#define LOAD ld
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#define StoreDS "sd"
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#define LoadDS "ld"
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#define REGBYTES 8
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#define RegLength 8
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#define RegLengthS "8"
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#else
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#define STORE sw
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#define LOAD lw
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#define StoreDS "sw"
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#define LoadDS "lw"
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#define RegLength 4
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#define REGBYTES 4
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#define RegLengthS "4"
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#endif
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/* FPU */
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#ifdef ARCH_RISCV_FPU
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#ifdef ARCH_RISCV_FPU_D
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#define FSTORE fsd
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#define FLOAD fld
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#define FREGBYTES 8
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#endif
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#ifdef ARCH_RISCV_FPU_S
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#define FSTORE fsw
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#define FLOAD flw
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#define FREGBYTES 4
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#endif
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#endif
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#endif
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