xiuos/Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/include/regsiomuxc.h

/*
 * Copyright (c) 2012, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_IOMUXC_REGISTERS_H__
#define __HW_IOMUXC_REGISTERS_H__

#include "regs.h"
#include "soc_memory_map.h"

/*
 * i.MX6DQ IOMUXC
 *
 * IOMUXC
 *
 * Registers defined in this header file:
 * - HW_IOMUXC_GPR0 - GPR
 * - HW_IOMUXC_GPR1 - GPR
 * - HW_IOMUXC_GPR2 - GPR
 * - HW_IOMUXC_GPR3 - GPR
 * - HW_IOMUXC_GPR4 - GPR
 * - HW_IOMUXC_GPR5 - GPR
 * - HW_IOMUXC_GPR6 - GPR
 * - HW_IOMUXC_GPR7 - GPR
 * - HW_IOMUXC_GPR8 - GPR
 * - HW_IOMUXC_GPR9 - GPR
 * - HW_IOMUXC_GPR10 - GPR
 * - HW_IOMUXC_GPR11 - GPR
 * - HW_IOMUXC_GPR12 - GPR
 * - HW_IOMUXC_GPR13 - GPR
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD - Pad Mux Register
 * - HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 - Pad Mux Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 - Pad Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_B7DS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_B0DS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_B1DS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_B2DS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_B3DS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_B4DS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_B5DS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_B6DS - Pad Group Control Register
 * - HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM - Pad Group Control Register
 * - HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_SDO0_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_SDO1_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_KEY_COL5_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_KEY_COL6_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_KEY_COL7_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_KEY_ROW5_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_KEY_ROW6_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_KEY_ROW7_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_USB_OTG_OC_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_USB_H1_OC_SELECT_INPUT - Select Input Register
 * - HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT - Select Input Register
 *
 * - hw_iomuxc_t - Struct containing all module registers.
 */

//! @name Module base addresses
//@{
#ifndef REGS_IOMUXC_BASE
#define HW_IOMUXC_INSTANCE_COUNT (1) //!< Number of instances of the IOMUXC module.
#define REGS_IOMUXC_BASE USERLAND_MMIO_P2V(0x020e0000) //!< Base address for IOMUXC.
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR0 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR0 - GPR (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_gpr0
{
    reg32_t U;
    struct _hw_iomuxc_gpr0_bitfields
    {
        unsigned DMAREQ_MUX_SEL0 : 1; //!< [0] Selects between two possible sources for SDMA_EVENT[2]:
        unsigned DMAREQ_MUX_SEL1 : 1; //!< [1] Selects between two possible sources for SDMA_EVENT[3]:
        unsigned DMAREQ_MUX_SEL2 : 1; //!< [2] Selects between two possible sources for SDMA_EVENT[4]:
        unsigned DMAREQ_MUX_SEL3 : 1; //!< [3] Selects between two possible sources for SDMA_EVENT[5]:
        unsigned DMAREQ_MUX_SEL4 : 1; //!< [4] Selects between two possible sources for SDMA_EVENT[10]:
        unsigned DMAREQ_MUX_SEL5 : 1; //!< [5] Selects between two possible sources for SDMA_EVENT[9]:
        unsigned DMAREQ_MUX_SEL6 : 1; //!< [6] Selects between two possible sources for SDMA_EVENT[23]:
        unsigned DMAREQ_MUX_SEL7 : 1; //!< [7] Selects between two possible sources for SDMA_EVENT[14]:
        unsigned AUDIO_VIDEO_MUXING : 6; //!< [13:8] See section (TBD) for details.
        unsigned TX_CLK2_MUX_SEL : 2; //!< [15:14] Selects the source of tx_clk2 in SPDIF according to ASRC clock muxing scheme:
        unsigned CLOCK_1_MUX_SEL : 2; //!< [17:16] Selects the source of asrck_clock_1 in ASRC according to clock muxing scheme:
        unsigned CLOCK_9_MUX_SEL : 2; //!< [19:18] Selects the source of asrck_clock_9 in ASRC according to clock muxing scheme:
        unsigned CLOCK_2_MUX_SEL : 2; //!< [21:20] Selects the source of asrck_clock_2 in ASRC according to clock muxing scheme:
        unsigned CLOCK_A_MUX_SEL : 2; //!< [23:22] Selects the source of asrck_clock_a in ASRC according to clock muxing scheme:
        unsigned CLOCK_3_MUX_SEL : 2; //!< [25:24] Selects the source of asrck_clock_3 in ASRC according to clock muxing scheme:
        unsigned CLOCK_B_MUX_SEL : 2; //!< [27:26] Selects the source of asrck_clock_b in ASRC according to clock muxing scheme:
        unsigned CLOCK_0_MUX_SEL : 2; //!< [29:28] Selects the source of asrck_clock_0 in ASRC according to clock muxing scheme:
        unsigned CLOCK_8_MUX_SEL : 2; //!< [31:30] Selects the source of asrck_clock_8 in ASRC according to clock muxing scheme
    } B;
} hw_iomuxc_gpr0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR0 register
 */
//@{
#define HW_IOMUXC_GPR0_ADDR      (REGS_IOMUXC_BASE + 0x0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR0           (*(volatile hw_iomuxc_gpr0_t *) HW_IOMUXC_GPR0_ADDR)
#define HW_IOMUXC_GPR0_RD()      (HW_IOMUXC_GPR0.U)
#define HW_IOMUXC_GPR0_WR(v)     (HW_IOMUXC_GPR0.U = (v))
#define HW_IOMUXC_GPR0_SET(v)    (HW_IOMUXC_GPR0_WR(HW_IOMUXC_GPR0_RD() |  (v)))
#define HW_IOMUXC_GPR0_CLR(v)    (HW_IOMUXC_GPR0_WR(HW_IOMUXC_GPR0_RD() & ~(v)))
#define HW_IOMUXC_GPR0_TOG(v)    (HW_IOMUXC_GPR0_WR(HW_IOMUXC_GPR0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR0 bitfields
 */

/*! @name Register IOMUXC_GPR0, field DMAREQ_MUX_SEL0[0] (RW)
 *
 * Selects between two possible sources for SDMA_EVENT[2]:
 *
 * Values:
 * - 0 - ipu1.ipu_sdma_event
 * - 1 - hdmi_tx.hdmi_tx_ophydtb[0]
 */
//@{
#define BP_IOMUXC_GPR0_DMAREQ_MUX_SEL0      (0)      //!< Bit position for IOMUXC_GPR0_DMAREQ_MUX_SEL0.
#define BM_IOMUXC_GPR0_DMAREQ_MUX_SEL0      (0x00000001)  //!< Bit mask for IOMUXC_GPR0_DMAREQ_MUX_SEL0.

//! @brief Get value of IOMUXC_GPR0_DMAREQ_MUX_SEL0 from a register value.
#define BG_IOMUXC_GPR0_DMAREQ_MUX_SEL0(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL0) >> BP_IOMUXC_GPR0_DMAREQ_MUX_SEL0)

//! @brief Format value for bitfield IOMUXC_GPR0_DMAREQ_MUX_SEL0.
#define BF_IOMUXC_GPR0_DMAREQ_MUX_SEL0(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_DMAREQ_MUX_SEL0) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DMAREQ_MUX_SEL0 field to a new value.
#define BW_IOMUXC_GPR0_DMAREQ_MUX_SEL0(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_DMAREQ_MUX_SEL0) | BF_IOMUXC_GPR0_DMAREQ_MUX_SEL0(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field DMAREQ_MUX_SEL1[1] (RW)
 *
 * Selects between two possible sources for SDMA_EVENT[3]:
 *
 * Values:
 * - 0 - ecspi1.ipd_req_cspi_rdma_b
 * - 1 - i2c3.ipi_int_b
 */
//@{
#define BP_IOMUXC_GPR0_DMAREQ_MUX_SEL1      (1)      //!< Bit position for IOMUXC_GPR0_DMAREQ_MUX_SEL1.
#define BM_IOMUXC_GPR0_DMAREQ_MUX_SEL1      (0x00000002)  //!< Bit mask for IOMUXC_GPR0_DMAREQ_MUX_SEL1.

//! @brief Get value of IOMUXC_GPR0_DMAREQ_MUX_SEL1 from a register value.
#define BG_IOMUXC_GPR0_DMAREQ_MUX_SEL1(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL1) >> BP_IOMUXC_GPR0_DMAREQ_MUX_SEL1)

//! @brief Format value for bitfield IOMUXC_GPR0_DMAREQ_MUX_SEL1.
#define BF_IOMUXC_GPR0_DMAREQ_MUX_SEL1(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_DMAREQ_MUX_SEL1) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DMAREQ_MUX_SEL1 field to a new value.
#define BW_IOMUXC_GPR0_DMAREQ_MUX_SEL1(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_DMAREQ_MUX_SEL1) | BF_IOMUXC_GPR0_DMAREQ_MUX_SEL1(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field DMAREQ_MUX_SEL2[2] (RW)
 *
 * Selects between two possible sources for SDMA_EVENT[4]:
 *
 * Values:
 * - 0 - ecspi1.ipd_req_cspi_tdma_b
 * - 1 - i2c2.ipi_int_b
 */
//@{
#define BP_IOMUXC_GPR0_DMAREQ_MUX_SEL2      (2)      //!< Bit position for IOMUXC_GPR0_DMAREQ_MUX_SEL2.
#define BM_IOMUXC_GPR0_DMAREQ_MUX_SEL2      (0x00000004)  //!< Bit mask for IOMUXC_GPR0_DMAREQ_MUX_SEL2.

//! @brief Get value of IOMUXC_GPR0_DMAREQ_MUX_SEL2 from a register value.
#define BG_IOMUXC_GPR0_DMAREQ_MUX_SEL2(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL2) >> BP_IOMUXC_GPR0_DMAREQ_MUX_SEL2)

//! @brief Format value for bitfield IOMUXC_GPR0_DMAREQ_MUX_SEL2.
#define BF_IOMUXC_GPR0_DMAREQ_MUX_SEL2(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_DMAREQ_MUX_SEL2) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DMAREQ_MUX_SEL2 field to a new value.
#define BW_IOMUXC_GPR0_DMAREQ_MUX_SEL2(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_DMAREQ_MUX_SEL2) | BF_IOMUXC_GPR0_DMAREQ_MUX_SEL2(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field DMAREQ_MUX_SEL3[3] (RW)
 *
 * Selects between two possible sources for SDMA_EVENT[5]:
 *
 * Values:
 * - 0 - ecspi2.ipd_req_cspi_rdma_b
 * - 1 - i2c1.ipi_int_b
 */
//@{
#define BP_IOMUXC_GPR0_DMAREQ_MUX_SEL3      (3)      //!< Bit position for IOMUXC_GPR0_DMAREQ_MUX_SEL3.
#define BM_IOMUXC_GPR0_DMAREQ_MUX_SEL3      (0x00000008)  //!< Bit mask for IOMUXC_GPR0_DMAREQ_MUX_SEL3.

//! @brief Get value of IOMUXC_GPR0_DMAREQ_MUX_SEL3 from a register value.
#define BG_IOMUXC_GPR0_DMAREQ_MUX_SEL3(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL3) >> BP_IOMUXC_GPR0_DMAREQ_MUX_SEL3)

//! @brief Format value for bitfield IOMUXC_GPR0_DMAREQ_MUX_SEL3.
#define BF_IOMUXC_GPR0_DMAREQ_MUX_SEL3(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_DMAREQ_MUX_SEL3) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL3)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DMAREQ_MUX_SEL3 field to a new value.
#define BW_IOMUXC_GPR0_DMAREQ_MUX_SEL3(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_DMAREQ_MUX_SEL3) | BF_IOMUXC_GPR0_DMAREQ_MUX_SEL3(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field DMAREQ_MUX_SEL4[4] (RW)
 *
 * Selects between two possible sources for SDMA_EVENT[10]:
 *
 * Values:
 * - 0 - ecspi4.ipd_req_cspi_tdma_b
 * - 1 - i2c1.ipi_int_b
 */
//@{
#define BP_IOMUXC_GPR0_DMAREQ_MUX_SEL4      (4)      //!< Bit position for IOMUXC_GPR0_DMAREQ_MUX_SEL4.
#define BM_IOMUXC_GPR0_DMAREQ_MUX_SEL4      (0x00000010)  //!< Bit mask for IOMUXC_GPR0_DMAREQ_MUX_SEL4.

//! @brief Get value of IOMUXC_GPR0_DMAREQ_MUX_SEL4 from a register value.
#define BG_IOMUXC_GPR0_DMAREQ_MUX_SEL4(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL4) >> BP_IOMUXC_GPR0_DMAREQ_MUX_SEL4)

//! @brief Format value for bitfield IOMUXC_GPR0_DMAREQ_MUX_SEL4.
#define BF_IOMUXC_GPR0_DMAREQ_MUX_SEL4(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_DMAREQ_MUX_SEL4) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL4)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DMAREQ_MUX_SEL4 field to a new value.
#define BW_IOMUXC_GPR0_DMAREQ_MUX_SEL4(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_DMAREQ_MUX_SEL4) | BF_IOMUXC_GPR0_DMAREQ_MUX_SEL4(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field DMAREQ_MUX_SEL5[5] (RW)
 *
 * Selects between two possible sources for SDMA_EVENT[9]:
 *
 * Values:
 * - 0 - ecspi4.ipd_req_cspi_rdma_b
 * - 1 - epit2.ipi_int_epit_oc
 */
//@{
#define BP_IOMUXC_GPR0_DMAREQ_MUX_SEL5      (5)      //!< Bit position for IOMUXC_GPR0_DMAREQ_MUX_SEL5.
#define BM_IOMUXC_GPR0_DMAREQ_MUX_SEL5      (0x00000020)  //!< Bit mask for IOMUXC_GPR0_DMAREQ_MUX_SEL5.

//! @brief Get value of IOMUXC_GPR0_DMAREQ_MUX_SEL5 from a register value.
#define BG_IOMUXC_GPR0_DMAREQ_MUX_SEL5(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL5) >> BP_IOMUXC_GPR0_DMAREQ_MUX_SEL5)

//! @brief Format value for bitfield IOMUXC_GPR0_DMAREQ_MUX_SEL5.
#define BF_IOMUXC_GPR0_DMAREQ_MUX_SEL5(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_DMAREQ_MUX_SEL5) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL5)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DMAREQ_MUX_SEL5 field to a new value.
#define BW_IOMUXC_GPR0_DMAREQ_MUX_SEL5(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_DMAREQ_MUX_SEL5) | BF_IOMUXC_GPR0_DMAREQ_MUX_SEL5(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field DMAREQ_MUX_SEL6[6] (RW)
 *
 * Selects between two possible sources for SDMA_EVENT[23]:
 *
 * Values:
 * - 0 - esai.
 * - 1 - i2c3.ipi_int_b
 */
//@{
#define BP_IOMUXC_GPR0_DMAREQ_MUX_SEL6      (6)      //!< Bit position for IOMUXC_GPR0_DMAREQ_MUX_SEL6.
#define BM_IOMUXC_GPR0_DMAREQ_MUX_SEL6      (0x00000040)  //!< Bit mask for IOMUXC_GPR0_DMAREQ_MUX_SEL6.

//! @brief Get value of IOMUXC_GPR0_DMAREQ_MUX_SEL6 from a register value.
#define BG_IOMUXC_GPR0_DMAREQ_MUX_SEL6(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL6) >> BP_IOMUXC_GPR0_DMAREQ_MUX_SEL6)

//! @brief Format value for bitfield IOMUXC_GPR0_DMAREQ_MUX_SEL6.
#define BF_IOMUXC_GPR0_DMAREQ_MUX_SEL6(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_DMAREQ_MUX_SEL6) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL6)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DMAREQ_MUX_SEL6 field to a new value.
#define BW_IOMUXC_GPR0_DMAREQ_MUX_SEL6(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_DMAREQ_MUX_SEL6) | BF_IOMUXC_GPR0_DMAREQ_MUX_SEL6(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field DMAREQ_MUX_SEL7[7] (RW)
 *
 * Selects between two possible sources for SDMA_EVENT[14]:
 *
 * Values:
 * - 0 - spdif.drq0_spdif_b
 * - 1 - iomux.sdma_ext_events[1] - External DMA Request via DISP0_DAT17 or GPIO_18
 */
//@{
#define BP_IOMUXC_GPR0_DMAREQ_MUX_SEL7      (7)      //!< Bit position for IOMUXC_GPR0_DMAREQ_MUX_SEL7.
#define BM_IOMUXC_GPR0_DMAREQ_MUX_SEL7      (0x00000080)  //!< Bit mask for IOMUXC_GPR0_DMAREQ_MUX_SEL7.

//! @brief Get value of IOMUXC_GPR0_DMAREQ_MUX_SEL7 from a register value.
#define BG_IOMUXC_GPR0_DMAREQ_MUX_SEL7(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL7) >> BP_IOMUXC_GPR0_DMAREQ_MUX_SEL7)

//! @brief Format value for bitfield IOMUXC_GPR0_DMAREQ_MUX_SEL7.
#define BF_IOMUXC_GPR0_DMAREQ_MUX_SEL7(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_DMAREQ_MUX_SEL7) & BM_IOMUXC_GPR0_DMAREQ_MUX_SEL7)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DMAREQ_MUX_SEL7 field to a new value.
#define BW_IOMUXC_GPR0_DMAREQ_MUX_SEL7(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_DMAREQ_MUX_SEL7) | BF_IOMUXC_GPR0_DMAREQ_MUX_SEL7(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field AUDIO_VIDEO_MUXING[13:8] (RW)
 *
 * See section (TBD) for details.
 */
//@{
#define BP_IOMUXC_GPR0_AUDIO_VIDEO_MUXING      (8)      //!< Bit position for IOMUXC_GPR0_AUDIO_VIDEO_MUXING.
#define BM_IOMUXC_GPR0_AUDIO_VIDEO_MUXING      (0x00003f00)  //!< Bit mask for IOMUXC_GPR0_AUDIO_VIDEO_MUXING.

//! @brief Get value of IOMUXC_GPR0_AUDIO_VIDEO_MUXING from a register value.
#define BG_IOMUXC_GPR0_AUDIO_VIDEO_MUXING(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_AUDIO_VIDEO_MUXING) >> BP_IOMUXC_GPR0_AUDIO_VIDEO_MUXING)

//! @brief Format value for bitfield IOMUXC_GPR0_AUDIO_VIDEO_MUXING.
#define BF_IOMUXC_GPR0_AUDIO_VIDEO_MUXING(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_AUDIO_VIDEO_MUXING) & BM_IOMUXC_GPR0_AUDIO_VIDEO_MUXING)

#ifndef __LANGUAGE_ASM__
//! @brief Set the AUDIO_VIDEO_MUXING field to a new value.
#define BW_IOMUXC_GPR0_AUDIO_VIDEO_MUXING(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_AUDIO_VIDEO_MUXING) | BF_IOMUXC_GPR0_AUDIO_VIDEO_MUXING(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field TX_CLK2_MUX_SEL[15:14] (RW)
 *
 * Selects the source of tx_clk2 in SPDIF according to ASRC clock muxing scheme:
 *
 * Values:
 * - 00 - same source as for asrc.asrck_clock_1
 * - 01 - same source as for asrc.asrck_clock_2
 * - 10 - same source as for asrc.asrck_clock_3
 * - 11 - Reserved
 */
//@{
#define BP_IOMUXC_GPR0_TX_CLK2_MUX_SEL      (14)      //!< Bit position for IOMUXC_GPR0_TX_CLK2_MUX_SEL.
#define BM_IOMUXC_GPR0_TX_CLK2_MUX_SEL      (0x0000c000)  //!< Bit mask for IOMUXC_GPR0_TX_CLK2_MUX_SEL.

//! @brief Get value of IOMUXC_GPR0_TX_CLK2_MUX_SEL from a register value.
#define BG_IOMUXC_GPR0_TX_CLK2_MUX_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_TX_CLK2_MUX_SEL) >> BP_IOMUXC_GPR0_TX_CLK2_MUX_SEL)

//! @brief Format value for bitfield IOMUXC_GPR0_TX_CLK2_MUX_SEL.
#define BF_IOMUXC_GPR0_TX_CLK2_MUX_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_TX_CLK2_MUX_SEL) & BM_IOMUXC_GPR0_TX_CLK2_MUX_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TX_CLK2_MUX_SEL field to a new value.
#define BW_IOMUXC_GPR0_TX_CLK2_MUX_SEL(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_TX_CLK2_MUX_SEL) | BF_IOMUXC_GPR0_TX_CLK2_MUX_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field CLOCK_1_MUX_SEL[17:16] (RW)
 *
 * Selects the source of asrck_clock_1 in ASRC according to clock muxing scheme:
 *
 * Values:
 * - 00 - audmux.amx_output_rxclk_p1 muxed with ssi1.ssi_srck
 * - 01 - audmux.amx_output_rxclk_p1
 * - 10 - ssi1.ssi_srck
 * - 11 - ssi1.rx_bit_clk
 */
//@{
#define BP_IOMUXC_GPR0_CLOCK_1_MUX_SEL      (16)      //!< Bit position for IOMUXC_GPR0_CLOCK_1_MUX_SEL.
#define BM_IOMUXC_GPR0_CLOCK_1_MUX_SEL      (0x00030000)  //!< Bit mask for IOMUXC_GPR0_CLOCK_1_MUX_SEL.

//! @brief Get value of IOMUXC_GPR0_CLOCK_1_MUX_SEL from a register value.
#define BG_IOMUXC_GPR0_CLOCK_1_MUX_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_CLOCK_1_MUX_SEL) >> BP_IOMUXC_GPR0_CLOCK_1_MUX_SEL)

//! @brief Format value for bitfield IOMUXC_GPR0_CLOCK_1_MUX_SEL.
#define BF_IOMUXC_GPR0_CLOCK_1_MUX_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_CLOCK_1_MUX_SEL) & BM_IOMUXC_GPR0_CLOCK_1_MUX_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_1_MUX_SEL field to a new value.
#define BW_IOMUXC_GPR0_CLOCK_1_MUX_SEL(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_CLOCK_1_MUX_SEL) | BF_IOMUXC_GPR0_CLOCK_1_MUX_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field CLOCK_9_MUX_SEL[19:18] (RW)
 *
 * Selects the source of asrck_clock_9 in ASRC according to clock muxing scheme:
 *
 * Values:
 * - 00 - audmux.amx_output_txclk_p1 muxed with ssi1.ssi_stck
 * - 01 - audmux.amx_output_txclk_p1
 * - 10 - ssi1.ssi_stck
 * - 11 - ssi1.tx_bit_clk
 */
//@{
#define BP_IOMUXC_GPR0_CLOCK_9_MUX_SEL      (18)      //!< Bit position for IOMUXC_GPR0_CLOCK_9_MUX_SEL.
#define BM_IOMUXC_GPR0_CLOCK_9_MUX_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_GPR0_CLOCK_9_MUX_SEL.

//! @brief Get value of IOMUXC_GPR0_CLOCK_9_MUX_SEL from a register value.
#define BG_IOMUXC_GPR0_CLOCK_9_MUX_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_CLOCK_9_MUX_SEL) >> BP_IOMUXC_GPR0_CLOCK_9_MUX_SEL)

//! @brief Format value for bitfield IOMUXC_GPR0_CLOCK_9_MUX_SEL.
#define BF_IOMUXC_GPR0_CLOCK_9_MUX_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_CLOCK_9_MUX_SEL) & BM_IOMUXC_GPR0_CLOCK_9_MUX_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_9_MUX_SEL field to a new value.
#define BW_IOMUXC_GPR0_CLOCK_9_MUX_SEL(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_CLOCK_9_MUX_SEL) | BF_IOMUXC_GPR0_CLOCK_9_MUX_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field CLOCK_2_MUX_SEL[21:20] (RW)
 *
 * Selects the source of asrck_clock_2 in ASRC according to clock muxing scheme:
 *
 * Values:
 * - 00 - audmux.amx_output_rxclk_p2 muxed with ssi2.ssi_srck
 * - 01 - audmux.amx_output_rxclk_p2
 * - 10 - ssi2.ssi_srck
 * - 11 - ssi2.rx_bit_clk
 */
//@{
#define BP_IOMUXC_GPR0_CLOCK_2_MUX_SEL      (20)      //!< Bit position for IOMUXC_GPR0_CLOCK_2_MUX_SEL.
#define BM_IOMUXC_GPR0_CLOCK_2_MUX_SEL      (0x00300000)  //!< Bit mask for IOMUXC_GPR0_CLOCK_2_MUX_SEL.

//! @brief Get value of IOMUXC_GPR0_CLOCK_2_MUX_SEL from a register value.
#define BG_IOMUXC_GPR0_CLOCK_2_MUX_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_CLOCK_2_MUX_SEL) >> BP_IOMUXC_GPR0_CLOCK_2_MUX_SEL)

//! @brief Format value for bitfield IOMUXC_GPR0_CLOCK_2_MUX_SEL.
#define BF_IOMUXC_GPR0_CLOCK_2_MUX_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_CLOCK_2_MUX_SEL) & BM_IOMUXC_GPR0_CLOCK_2_MUX_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_2_MUX_SEL field to a new value.
#define BW_IOMUXC_GPR0_CLOCK_2_MUX_SEL(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_CLOCK_2_MUX_SEL) | BF_IOMUXC_GPR0_CLOCK_2_MUX_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field CLOCK_A_MUX_SEL[23:22] (RW)
 *
 * Selects the source of asrck_clock_a in ASRC according to clock muxing scheme:
 *
 * Values:
 * - 00 - audmux.amx_output_txclk_p2 muxed with ssi2.ssi_stck
 * - 01 - audmux.amx_output_txclk_p2
 * - 10 - ssi2.ssi_stck
 * - 11 - ssi2.tx_bit_clk
 */
//@{
#define BP_IOMUXC_GPR0_CLOCK_A_MUX_SEL      (22)      //!< Bit position for IOMUXC_GPR0_CLOCK_A_MUX_SEL.
#define BM_IOMUXC_GPR0_CLOCK_A_MUX_SEL      (0x00c00000)  //!< Bit mask for IOMUXC_GPR0_CLOCK_A_MUX_SEL.

//! @brief Get value of IOMUXC_GPR0_CLOCK_A_MUX_SEL from a register value.
#define BG_IOMUXC_GPR0_CLOCK_A_MUX_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_CLOCK_A_MUX_SEL) >> BP_IOMUXC_GPR0_CLOCK_A_MUX_SEL)

//! @brief Format value for bitfield IOMUXC_GPR0_CLOCK_A_MUX_SEL.
#define BF_IOMUXC_GPR0_CLOCK_A_MUX_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_CLOCK_A_MUX_SEL) & BM_IOMUXC_GPR0_CLOCK_A_MUX_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_A_MUX_SEL field to a new value.
#define BW_IOMUXC_GPR0_CLOCK_A_MUX_SEL(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_CLOCK_A_MUX_SEL) | BF_IOMUXC_GPR0_CLOCK_A_MUX_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field CLOCK_3_MUX_SEL[25:24] (RW)
 *
 * Selects the source of asrck_clock_3 in ASRC according to clock muxing scheme:
 *
 * Values:
 * - 00 - audmux.amx_output_rxclk_p7 muxed with ssi3.ssi_srck
 * - 01 - audmux.amx_output_rxclk_p7
 * - 10 - ssi3.ssi_srck
 * - 11 - ssi3.rx_bit_clk
 */
//@{
#define BP_IOMUXC_GPR0_CLOCK_3_MUX_SEL      (24)      //!< Bit position for IOMUXC_GPR0_CLOCK_3_MUX_SEL.
#define BM_IOMUXC_GPR0_CLOCK_3_MUX_SEL      (0x03000000)  //!< Bit mask for IOMUXC_GPR0_CLOCK_3_MUX_SEL.

//! @brief Get value of IOMUXC_GPR0_CLOCK_3_MUX_SEL from a register value.
#define BG_IOMUXC_GPR0_CLOCK_3_MUX_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_CLOCK_3_MUX_SEL) >> BP_IOMUXC_GPR0_CLOCK_3_MUX_SEL)

//! @brief Format value for bitfield IOMUXC_GPR0_CLOCK_3_MUX_SEL.
#define BF_IOMUXC_GPR0_CLOCK_3_MUX_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_CLOCK_3_MUX_SEL) & BM_IOMUXC_GPR0_CLOCK_3_MUX_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_3_MUX_SEL field to a new value.
#define BW_IOMUXC_GPR0_CLOCK_3_MUX_SEL(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_CLOCK_3_MUX_SEL) | BF_IOMUXC_GPR0_CLOCK_3_MUX_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field CLOCK_B_MUX_SEL[27:26] (RW)
 *
 * Selects the source of asrck_clock_b in ASRC according to clock muxing scheme:
 *
 * Values:
 * - 00 - audmux.amx_output_txclk_p7 muxed with ssi3.ssi_stck
 * - 01 - audmux.amx_output_txclk_p7
 * - 10 - ssi3.ssi_stck
 * - 11 - ssi3.tx_bit_clk
 */
//@{
#define BP_IOMUXC_GPR0_CLOCK_B_MUX_SEL      (26)      //!< Bit position for IOMUXC_GPR0_CLOCK_B_MUX_SEL.
#define BM_IOMUXC_GPR0_CLOCK_B_MUX_SEL      (0x0c000000)  //!< Bit mask for IOMUXC_GPR0_CLOCK_B_MUX_SEL.

//! @brief Get value of IOMUXC_GPR0_CLOCK_B_MUX_SEL from a register value.
#define BG_IOMUXC_GPR0_CLOCK_B_MUX_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_CLOCK_B_MUX_SEL) >> BP_IOMUXC_GPR0_CLOCK_B_MUX_SEL)

//! @brief Format value for bitfield IOMUXC_GPR0_CLOCK_B_MUX_SEL.
#define BF_IOMUXC_GPR0_CLOCK_B_MUX_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_CLOCK_B_MUX_SEL) & BM_IOMUXC_GPR0_CLOCK_B_MUX_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_B_MUX_SEL field to a new value.
#define BW_IOMUXC_GPR0_CLOCK_B_MUX_SEL(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_CLOCK_B_MUX_SEL) | BF_IOMUXC_GPR0_CLOCK_B_MUX_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field CLOCK_0_MUX_SEL[29:28] (RW)
 *
 * Selects the source of asrck_clock_0 in ASRC according to clock muxing scheme:
 *
 * Values:
 * - 00 - esai.ipp_ind_sckr muxed with esai.ipp_do_sckr
 * - 01 - esai.ipp_ind_sckr
 * - 10 - esai.ipp_do_sckr
 * - 11 - Reserved
 */
//@{
#define BP_IOMUXC_GPR0_CLOCK_0_MUX_SEL      (28)      //!< Bit position for IOMUXC_GPR0_CLOCK_0_MUX_SEL.
#define BM_IOMUXC_GPR0_CLOCK_0_MUX_SEL      (0x30000000)  //!< Bit mask for IOMUXC_GPR0_CLOCK_0_MUX_SEL.

//! @brief Get value of IOMUXC_GPR0_CLOCK_0_MUX_SEL from a register value.
#define BG_IOMUXC_GPR0_CLOCK_0_MUX_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_CLOCK_0_MUX_SEL) >> BP_IOMUXC_GPR0_CLOCK_0_MUX_SEL)

//! @brief Format value for bitfield IOMUXC_GPR0_CLOCK_0_MUX_SEL.
#define BF_IOMUXC_GPR0_CLOCK_0_MUX_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_CLOCK_0_MUX_SEL) & BM_IOMUXC_GPR0_CLOCK_0_MUX_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_0_MUX_SEL field to a new value.
#define BW_IOMUXC_GPR0_CLOCK_0_MUX_SEL(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_CLOCK_0_MUX_SEL) | BF_IOMUXC_GPR0_CLOCK_0_MUX_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR0, field CLOCK_8_MUX_SEL[31:30] (RW)
 *
 * Selects the source of asrck_clock_8 in ASRC according to clock muxing scheme
 *
 * Values:
 * - 00 - audmux.amx_output_rxclk_p7 muxed with ssi3.ssi_srck
 * - 01 - audmux.amx_output_rxclk_p7
 * - 10 - ssi3.ssi_srck
 * - 11 - ssi3.rx_bit_clk
 */
//@{
#define BP_IOMUXC_GPR0_CLOCK_8_MUX_SEL      (30)      //!< Bit position for IOMUXC_GPR0_CLOCK_8_MUX_SEL.
#define BM_IOMUXC_GPR0_CLOCK_8_MUX_SEL      (0xc0000000)  //!< Bit mask for IOMUXC_GPR0_CLOCK_8_MUX_SEL.

//! @brief Get value of IOMUXC_GPR0_CLOCK_8_MUX_SEL from a register value.
#define BG_IOMUXC_GPR0_CLOCK_8_MUX_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR0_CLOCK_8_MUX_SEL) >> BP_IOMUXC_GPR0_CLOCK_8_MUX_SEL)

//! @brief Format value for bitfield IOMUXC_GPR0_CLOCK_8_MUX_SEL.
#define BF_IOMUXC_GPR0_CLOCK_8_MUX_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR0_CLOCK_8_MUX_SEL) & BM_IOMUXC_GPR0_CLOCK_8_MUX_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLOCK_8_MUX_SEL field to a new value.
#define BW_IOMUXC_GPR0_CLOCK_8_MUX_SEL(v)   (HW_IOMUXC_GPR0_WR((HW_IOMUXC_GPR0_RD() & ~BM_IOMUXC_GPR0_CLOCK_8_MUX_SEL) | BF_IOMUXC_GPR0_CLOCK_8_MUX_SEL(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR1 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR1 - GPR (RW)
 *
 * Reset value: 0x48400005
 */
typedef union _hw_iomuxc_gpr1
{
    reg32_t U;
    struct _hw_iomuxc_gpr1_bitfields
    {
        unsigned ACT_CS0 : 1; //!< [0] See description for ADDRS3[10]
        unsigned ADDRS0 : 2; //!< [2:1] See description for ADDRS3[10]
        unsigned ACT_CS1 : 1; //!< [3] See description for ADDRS3[10]
        unsigned ADDRS1 : 2; //!< [5:4] See description for ADDRS3[10]
        unsigned ACT_CS2 : 1; //!< [6] See description for ADDRS3[10]
        unsigned ADDRS2 : 2; //!< [8:7] See description for ADDRS3[10]
        unsigned ACT_CS3 : 1; //!< [9] See description for ADDRS3[10]
        unsigned ADDRS3 : 2; //!< [11:10] Active Chip Select and Address Space.
        unsigned GINT : 1; //!< [12] Global interrupt "0" bit (connected to ARM IRQ#0 and GPC)
        unsigned USB_OTG_ID_SEL : 1; //!< [13] ''usb_otg_id' pin iomux select control.
        unsigned SYS_INT : 1; //!< [14] PCIe_CTL - When SYS_INT goes from low to high, the core generates an Assert_INTx Message.
        unsigned USB_EXP_MODE : 1; //!< [15] USB Exposure mode
        unsigned REF_SSP_EN : 1; //!< [16] PCIe_PHY - Reference Clock Enable for SS function.
        unsigned IPU_VPU_MUX : 1; //!< [17] IPU-1/IPU-2 to VPU signals control.
        unsigned TEST_POWERDOWN : 1; //!< [18] PCIe_PHY - All Circuits Power-Down Control Function: Powers down all circuitry in the PHY for IDDQ testing.
        unsigned MIPI_IPU1_MUX : 1; //!< [19] MIPI sensor to IPU-1 mux control
        unsigned MIPI_IPU2_MUX : 1; //!< [20] MIPI sensor to IPU-2 mux control
        unsigned ENET_CLK_SEL : 1; //!< [21] ENET TX reference clock
        unsigned EXC_MON : 1; //!< [22] Exclusive monitor response select of illegal command (of lal gaskets, except MMDC)
        unsigned RESERVED0 : 1; //!< [23] Reserved
        unsigned MIPI_DPI_OFF : 1; //!< [24] MIPI DPI shutdown request
        unsigned MIPI_COLOR_SW : 1; //!< [25] MIPI color switch control
        unsigned APP_REQ_ENTR_L1 : 1; //!< [26] PCIe_CTL - Application Request to Enter L1.
        unsigned APP_READY_ENTR_L23 : 1; //!< [27] PCIe_CTL - Application Ready to Enter L23.
        unsigned APP_REQ_EXIT_L1 : 1; //!< [28] PCIe_CTL - Application Request to Exit L1.
        unsigned RESERVED1 : 1; //!< [29] Reserved
        unsigned APP_CLK_REQ_N : 1; //!< [30] PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Indicates that application logic is ready to have reference clock removed.
        unsigned CFG_L1_CLK_REMOVAL_EN : 1; //!< [31] PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Enable the reference clock removal in L1 state.
    } B;
} hw_iomuxc_gpr1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR1 register
 */
//@{
#define HW_IOMUXC_GPR1_ADDR      (REGS_IOMUXC_BASE + 0x4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR1           (*(volatile hw_iomuxc_gpr1_t *) HW_IOMUXC_GPR1_ADDR)
#define HW_IOMUXC_GPR1_RD()      (HW_IOMUXC_GPR1.U)
#define HW_IOMUXC_GPR1_WR(v)     (HW_IOMUXC_GPR1.U = (v))
#define HW_IOMUXC_GPR1_SET(v)    (HW_IOMUXC_GPR1_WR(HW_IOMUXC_GPR1_RD() |  (v)))
#define HW_IOMUXC_GPR1_CLR(v)    (HW_IOMUXC_GPR1_WR(HW_IOMUXC_GPR1_RD() & ~(v)))
#define HW_IOMUXC_GPR1_TOG(v)    (HW_IOMUXC_GPR1_WR(HW_IOMUXC_GPR1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR1 bitfields
 */

/*! @name Register IOMUXC_GPR1, field ACT_CS0[0] (RW)
 *
 * See description for ADDRS3[10]
 */
//@{
#define BP_IOMUXC_GPR1_ACT_CS0      (0)      //!< Bit position for IOMUXC_GPR1_ACT_CS0.
#define BM_IOMUXC_GPR1_ACT_CS0      (0x00000001)  //!< Bit mask for IOMUXC_GPR1_ACT_CS0.

//! @brief Get value of IOMUXC_GPR1_ACT_CS0 from a register value.
#define BG_IOMUXC_GPR1_ACT_CS0(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_ACT_CS0) >> BP_IOMUXC_GPR1_ACT_CS0)

//! @brief Format value for bitfield IOMUXC_GPR1_ACT_CS0.
#define BF_IOMUXC_GPR1_ACT_CS0(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_ACT_CS0) & BM_IOMUXC_GPR1_ACT_CS0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ACT_CS0 field to a new value.
#define BW_IOMUXC_GPR1_ACT_CS0(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_ACT_CS0) | BF_IOMUXC_GPR1_ACT_CS0(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field ADDRS0[2:1] (RW)
 *
 * See description for ADDRS3[10]
 */
//@{
#define BP_IOMUXC_GPR1_ADDRS0      (1)      //!< Bit position for IOMUXC_GPR1_ADDRS0.
#define BM_IOMUXC_GPR1_ADDRS0      (0x00000006)  //!< Bit mask for IOMUXC_GPR1_ADDRS0.

//! @brief Get value of IOMUXC_GPR1_ADDRS0 from a register value.
#define BG_IOMUXC_GPR1_ADDRS0(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_ADDRS0) >> BP_IOMUXC_GPR1_ADDRS0)

//! @brief Format value for bitfield IOMUXC_GPR1_ADDRS0.
#define BF_IOMUXC_GPR1_ADDRS0(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_ADDRS0) & BM_IOMUXC_GPR1_ADDRS0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ADDRS0 field to a new value.
#define BW_IOMUXC_GPR1_ADDRS0(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_ADDRS0) | BF_IOMUXC_GPR1_ADDRS0(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field ACT_CS1[3] (RW)
 *
 * See description for ADDRS3[10]
 */
//@{
#define BP_IOMUXC_GPR1_ACT_CS1      (3)      //!< Bit position for IOMUXC_GPR1_ACT_CS1.
#define BM_IOMUXC_GPR1_ACT_CS1      (0x00000008)  //!< Bit mask for IOMUXC_GPR1_ACT_CS1.

//! @brief Get value of IOMUXC_GPR1_ACT_CS1 from a register value.
#define BG_IOMUXC_GPR1_ACT_CS1(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_ACT_CS1) >> BP_IOMUXC_GPR1_ACT_CS1)

//! @brief Format value for bitfield IOMUXC_GPR1_ACT_CS1.
#define BF_IOMUXC_GPR1_ACT_CS1(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_ACT_CS1) & BM_IOMUXC_GPR1_ACT_CS1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ACT_CS1 field to a new value.
#define BW_IOMUXC_GPR1_ACT_CS1(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_ACT_CS1) | BF_IOMUXC_GPR1_ACT_CS1(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field ADDRS1[5:4] (RW)
 *
 * See description for ADDRS3[10]
 */
//@{
#define BP_IOMUXC_GPR1_ADDRS1      (4)      //!< Bit position for IOMUXC_GPR1_ADDRS1.
#define BM_IOMUXC_GPR1_ADDRS1      (0x00000030)  //!< Bit mask for IOMUXC_GPR1_ADDRS1.

//! @brief Get value of IOMUXC_GPR1_ADDRS1 from a register value.
#define BG_IOMUXC_GPR1_ADDRS1(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_ADDRS1) >> BP_IOMUXC_GPR1_ADDRS1)

//! @brief Format value for bitfield IOMUXC_GPR1_ADDRS1.
#define BF_IOMUXC_GPR1_ADDRS1(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_ADDRS1) & BM_IOMUXC_GPR1_ADDRS1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ADDRS1 field to a new value.
#define BW_IOMUXC_GPR1_ADDRS1(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_ADDRS1) | BF_IOMUXC_GPR1_ADDRS1(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field ACT_CS2[6] (RW)
 *
 * See description for ADDRS3[10]
 */
//@{
#define BP_IOMUXC_GPR1_ACT_CS2      (6)      //!< Bit position for IOMUXC_GPR1_ACT_CS2.
#define BM_IOMUXC_GPR1_ACT_CS2      (0x00000040)  //!< Bit mask for IOMUXC_GPR1_ACT_CS2.

//! @brief Get value of IOMUXC_GPR1_ACT_CS2 from a register value.
#define BG_IOMUXC_GPR1_ACT_CS2(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_ACT_CS2) >> BP_IOMUXC_GPR1_ACT_CS2)

//! @brief Format value for bitfield IOMUXC_GPR1_ACT_CS2.
#define BF_IOMUXC_GPR1_ACT_CS2(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_ACT_CS2) & BM_IOMUXC_GPR1_ACT_CS2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ACT_CS2 field to a new value.
#define BW_IOMUXC_GPR1_ACT_CS2(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_ACT_CS2) | BF_IOMUXC_GPR1_ACT_CS2(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field ADDRS2[8:7] (RW)
 *
 * See description for ADDRS3[10]
 */
//@{
#define BP_IOMUXC_GPR1_ADDRS2      (7)      //!< Bit position for IOMUXC_GPR1_ADDRS2.
#define BM_IOMUXC_GPR1_ADDRS2      (0x00000180)  //!< Bit mask for IOMUXC_GPR1_ADDRS2.

//! @brief Get value of IOMUXC_GPR1_ADDRS2 from a register value.
#define BG_IOMUXC_GPR1_ADDRS2(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_ADDRS2) >> BP_IOMUXC_GPR1_ADDRS2)

//! @brief Format value for bitfield IOMUXC_GPR1_ADDRS2.
#define BF_IOMUXC_GPR1_ADDRS2(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_ADDRS2) & BM_IOMUXC_GPR1_ADDRS2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ADDRS2 field to a new value.
#define BW_IOMUXC_GPR1_ADDRS2(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_ADDRS2) | BF_IOMUXC_GPR1_ADDRS2(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field ACT_CS3[9] (RW)
 *
 * See description for ADDRS3[10]
 */
//@{
#define BP_IOMUXC_GPR1_ACT_CS3      (9)      //!< Bit position for IOMUXC_GPR1_ACT_CS3.
#define BM_IOMUXC_GPR1_ACT_CS3      (0x00000200)  //!< Bit mask for IOMUXC_GPR1_ACT_CS3.

//! @brief Get value of IOMUXC_GPR1_ACT_CS3 from a register value.
#define BG_IOMUXC_GPR1_ACT_CS3(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_ACT_CS3) >> BP_IOMUXC_GPR1_ACT_CS3)

//! @brief Format value for bitfield IOMUXC_GPR1_ACT_CS3.
#define BF_IOMUXC_GPR1_ACT_CS3(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_ACT_CS3) & BM_IOMUXC_GPR1_ACT_CS3)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ACT_CS3 field to a new value.
#define BW_IOMUXC_GPR1_ACT_CS3(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_ACT_CS3) | BF_IOMUXC_GPR1_ACT_CS3(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field ADDRS3[11:10] (RW)
 *
 * Active Chip Select and Address Space. Each of the ACT_CSx represents one of the four chip selects
 * of the EIM. When ACT_CSx=1'b1, the corresponding chip select is active and has a valid address
 * space according to its address space configuration determined by ADDRSx[10] bits ADDRSx[10] is
 * setting the space for each chip select which is active. The address space of the first active
 * chip select must be the largest one, the following active chip select address spaces may be equal
 * or smaller. Total address space size is 128 MByte. The supported configurations are: CS0(128M),
 * CS1 (0M), CS2 (0M), CS3(0M) [default configuration] CS0(64M), CS1(64M), CS2(0M), CS3(0M)
 * CS0(64M), CS1(32M), CS2(32M), CS3(0M) CS0(32M), CS1(32M), CS2(32M), CS3(32M) Address Space
 * Configuration options (ADDRSx[10]):
 *
 * Values:
 * - 00 - 32 MByte
 * - 01 - 64 MByte
 * - 10 - 128 MByte
 * - 11 - Reserved
 */
//@{
#define BP_IOMUXC_GPR1_ADDRS3      (10)      //!< Bit position for IOMUXC_GPR1_ADDRS3.
#define BM_IOMUXC_GPR1_ADDRS3      (0x00000c00)  //!< Bit mask for IOMUXC_GPR1_ADDRS3.

//! @brief Get value of IOMUXC_GPR1_ADDRS3 from a register value.
#define BG_IOMUXC_GPR1_ADDRS3(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_ADDRS3) >> BP_IOMUXC_GPR1_ADDRS3)

//! @brief Format value for bitfield IOMUXC_GPR1_ADDRS3.
#define BF_IOMUXC_GPR1_ADDRS3(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_ADDRS3) & BM_IOMUXC_GPR1_ADDRS3)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ADDRS3 field to a new value.
#define BW_IOMUXC_GPR1_ADDRS3(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_ADDRS3) | BF_IOMUXC_GPR1_ADDRS3(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field GINT[12] (RW)
 *
 * Global interrupt "0" bit (connected to ARM IRQ#0 and GPC)
 *
 * Values:
 * - 0 - Global interrupt request is not asserted
 * - 1 - Global interrupt request is asserted
 */
//@{
#define BP_IOMUXC_GPR1_GINT      (12)      //!< Bit position for IOMUXC_GPR1_GINT.
#define BM_IOMUXC_GPR1_GINT      (0x00001000)  //!< Bit mask for IOMUXC_GPR1_GINT.

//! @brief Get value of IOMUXC_GPR1_GINT from a register value.
#define BG_IOMUXC_GPR1_GINT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_GINT) >> BP_IOMUXC_GPR1_GINT)

//! @brief Format value for bitfield IOMUXC_GPR1_GINT.
#define BF_IOMUXC_GPR1_GINT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_GINT) & BM_IOMUXC_GPR1_GINT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the GINT field to a new value.
#define BW_IOMUXC_GPR1_GINT(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_GINT) | BF_IOMUXC_GPR1_GINT(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field USB_OTG_ID_SEL[13] (RW)
 *
 * ''usb_otg_id' pin iomux select control. (It functions as the 'daisy chain' mux control)
 *
 * Values:
 * - 0 - selects ENET_RX_ER
 * - 1 - selects GPIO_1.
 */
//@{
#define BP_IOMUXC_GPR1_USB_OTG_ID_SEL      (13)      //!< Bit position for IOMUXC_GPR1_USB_OTG_ID_SEL.
#define BM_IOMUXC_GPR1_USB_OTG_ID_SEL      (0x00002000)  //!< Bit mask for IOMUXC_GPR1_USB_OTG_ID_SEL.

//! @brief Get value of IOMUXC_GPR1_USB_OTG_ID_SEL from a register value.
#define BG_IOMUXC_GPR1_USB_OTG_ID_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_USB_OTG_ID_SEL) >> BP_IOMUXC_GPR1_USB_OTG_ID_SEL)

//! @brief Format value for bitfield IOMUXC_GPR1_USB_OTG_ID_SEL.
#define BF_IOMUXC_GPR1_USB_OTG_ID_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_USB_OTG_ID_SEL) & BM_IOMUXC_GPR1_USB_OTG_ID_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the USB_OTG_ID_SEL field to a new value.
#define BW_IOMUXC_GPR1_USB_OTG_ID_SEL(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_USB_OTG_ID_SEL) | BF_IOMUXC_GPR1_USB_OTG_ID_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field SYS_INT[14] (RW)
 *
 * PCIe_CTL - When SYS_INT goes from low to high, the core generates an Assert_INTx Message. When
 * sys_int goes from high to low, the core generates a Deassert_INTx Message.
 *
 * Values:
 * - 0 - PCIe system interrupt request is not asserted
 * - 1 - PCIe system interrupt request is asserted
 */
//@{
#define BP_IOMUXC_GPR1_SYS_INT      (14)      //!< Bit position for IOMUXC_GPR1_SYS_INT.
#define BM_IOMUXC_GPR1_SYS_INT      (0x00004000)  //!< Bit mask for IOMUXC_GPR1_SYS_INT.

//! @brief Get value of IOMUXC_GPR1_SYS_INT from a register value.
#define BG_IOMUXC_GPR1_SYS_INT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_SYS_INT) >> BP_IOMUXC_GPR1_SYS_INT)

//! @brief Format value for bitfield IOMUXC_GPR1_SYS_INT.
#define BF_IOMUXC_GPR1_SYS_INT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_SYS_INT) & BM_IOMUXC_GPR1_SYS_INT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SYS_INT field to a new value.
#define BW_IOMUXC_GPR1_SYS_INT(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_SYS_INT) | BF_IOMUXC_GPR1_SYS_INT(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field USB_EXP_MODE[15] (RW)
 *
 * USB Exposure mode
 *
 * Values:
 * - 0 - Exposure mode is disabled.
 * - 1 - Exposure mode is enabled.
 */
//@{
#define BP_IOMUXC_GPR1_USB_EXP_MODE      (15)      //!< Bit position for IOMUXC_GPR1_USB_EXP_MODE.
#define BM_IOMUXC_GPR1_USB_EXP_MODE      (0x00008000)  //!< Bit mask for IOMUXC_GPR1_USB_EXP_MODE.

//! @brief Get value of IOMUXC_GPR1_USB_EXP_MODE from a register value.
#define BG_IOMUXC_GPR1_USB_EXP_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_USB_EXP_MODE) >> BP_IOMUXC_GPR1_USB_EXP_MODE)

//! @brief Format value for bitfield IOMUXC_GPR1_USB_EXP_MODE.
#define BF_IOMUXC_GPR1_USB_EXP_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_USB_EXP_MODE) & BM_IOMUXC_GPR1_USB_EXP_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the USB_EXP_MODE field to a new value.
#define BW_IOMUXC_GPR1_USB_EXP_MODE(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_USB_EXP_MODE) | BF_IOMUXC_GPR1_USB_EXP_MODE(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field REF_SSP_EN[16] (RW)
 *
 * PCIe_PHY - Reference Clock Enable for SS function. Function: Enables the reference clock to the
 * prescaler. The phy_ref_ssp_en signal must remain deasserted until the reference clock is running
 * at the appropriate frequency, at which point phy_ref_ssp_en can be asserted. For lower power
 * states, phy_ref_ssp_en can also be deasserted.
 *
 * Values:
 * - 0 - PCIe PHY reference clock is disabled
 * - 1 - PCIe PHY reference clock is enabled
 */
//@{
#define BP_IOMUXC_GPR1_REF_SSP_EN      (16)      //!< Bit position for IOMUXC_GPR1_REF_SSP_EN.
#define BM_IOMUXC_GPR1_REF_SSP_EN      (0x00010000)  //!< Bit mask for IOMUXC_GPR1_REF_SSP_EN.

//! @brief Get value of IOMUXC_GPR1_REF_SSP_EN from a register value.
#define BG_IOMUXC_GPR1_REF_SSP_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_REF_SSP_EN) >> BP_IOMUXC_GPR1_REF_SSP_EN)

//! @brief Format value for bitfield IOMUXC_GPR1_REF_SSP_EN.
#define BF_IOMUXC_GPR1_REF_SSP_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_REF_SSP_EN) & BM_IOMUXC_GPR1_REF_SSP_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the REF_SSP_EN field to a new value.
#define BW_IOMUXC_GPR1_REF_SSP_EN(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_REF_SSP_EN) | BF_IOMUXC_GPR1_REF_SSP_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field IPU_VPU_MUX[17] (RW)
 *
 * IPU-1/IPU-2 to VPU signals control. This control selects between IPU-1 and IPU-2 outputs that are
 * going to the VPU (current buffer, new frame, end of line)
 *
 * Values:
 * - 0 - IPU-1 is selected
 * - 1 - IPU-2 is selected
 */
//@{
#define BP_IOMUXC_GPR1_IPU_VPU_MUX      (17)      //!< Bit position for IOMUXC_GPR1_IPU_VPU_MUX.
#define BM_IOMUXC_GPR1_IPU_VPU_MUX      (0x00020000)  //!< Bit mask for IOMUXC_GPR1_IPU_VPU_MUX.

//! @brief Get value of IOMUXC_GPR1_IPU_VPU_MUX from a register value.
#define BG_IOMUXC_GPR1_IPU_VPU_MUX(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_IPU_VPU_MUX) >> BP_IOMUXC_GPR1_IPU_VPU_MUX)

//! @brief Format value for bitfield IOMUXC_GPR1_IPU_VPU_MUX.
#define BF_IOMUXC_GPR1_IPU_VPU_MUX(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_IPU_VPU_MUX) & BM_IOMUXC_GPR1_IPU_VPU_MUX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU_VPU_MUX field to a new value.
#define BW_IOMUXC_GPR1_IPU_VPU_MUX(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_IPU_VPU_MUX) | BF_IOMUXC_GPR1_IPU_VPU_MUX(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field TEST_POWERDOWN[18] (RW)
 *
 * PCIe_PHY - All Circuits Power-Down Control Function: Powers down all circuitry in the PHY for
 * IDDQ testing.
 *
 * Values:
 * - 0 - Power down is not requested
 * - 1 - Power down is requested
 */
//@{
#define BP_IOMUXC_GPR1_TEST_POWERDOWN      (18)      //!< Bit position for IOMUXC_GPR1_TEST_POWERDOWN.
#define BM_IOMUXC_GPR1_TEST_POWERDOWN      (0x00040000)  //!< Bit mask for IOMUXC_GPR1_TEST_POWERDOWN.

//! @brief Get value of IOMUXC_GPR1_TEST_POWERDOWN from a register value.
#define BG_IOMUXC_GPR1_TEST_POWERDOWN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_TEST_POWERDOWN) >> BP_IOMUXC_GPR1_TEST_POWERDOWN)

//! @brief Format value for bitfield IOMUXC_GPR1_TEST_POWERDOWN.
#define BF_IOMUXC_GPR1_TEST_POWERDOWN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_TEST_POWERDOWN) & BM_IOMUXC_GPR1_TEST_POWERDOWN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TEST_POWERDOWN field to a new value.
#define BW_IOMUXC_GPR1_TEST_POWERDOWN(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_TEST_POWERDOWN) | BF_IOMUXC_GPR1_TEST_POWERDOWN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field MIPI_IPU1_MUX[19] (RW)
 *
 * MIPI sensor to IPU-1 mux control
 *
 * Values:
 * - 0 - Enable mipi to IPU1 CSI0 - virtual channel is fixed to 0.
 * - 1 - Enable parallel interface to IPU1 CSI0.
 */
//@{
#define BP_IOMUXC_GPR1_MIPI_IPU1_MUX      (19)      //!< Bit position for IOMUXC_GPR1_MIPI_IPU1_MUX.
#define BM_IOMUXC_GPR1_MIPI_IPU1_MUX      (0x00080000)  //!< Bit mask for IOMUXC_GPR1_MIPI_IPU1_MUX.

//! @brief Get value of IOMUXC_GPR1_MIPI_IPU1_MUX from a register value.
#define BG_IOMUXC_GPR1_MIPI_IPU1_MUX(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_MIPI_IPU1_MUX) >> BP_IOMUXC_GPR1_MIPI_IPU1_MUX)

//! @brief Format value for bitfield IOMUXC_GPR1_MIPI_IPU1_MUX.
#define BF_IOMUXC_GPR1_MIPI_IPU1_MUX(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_MIPI_IPU1_MUX) & BM_IOMUXC_GPR1_MIPI_IPU1_MUX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MIPI_IPU1_MUX field to a new value.
#define BW_IOMUXC_GPR1_MIPI_IPU1_MUX(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_MIPI_IPU1_MUX) | BF_IOMUXC_GPR1_MIPI_IPU1_MUX(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field MIPI_IPU2_MUX[20] (RW)
 *
 * MIPI sensor to IPU-2 mux control
 *
 * Values:
 * - 0 - Enable mipi to IPU2 CSI1 - virtual channel is fixed to 3.
 * - 1 - Enable parallel interface to IPU2 CSI1.
 */
//@{
#define BP_IOMUXC_GPR1_MIPI_IPU2_MUX      (20)      //!< Bit position for IOMUXC_GPR1_MIPI_IPU2_MUX.
#define BM_IOMUXC_GPR1_MIPI_IPU2_MUX      (0x00100000)  //!< Bit mask for IOMUXC_GPR1_MIPI_IPU2_MUX.

//! @brief Get value of IOMUXC_GPR1_MIPI_IPU2_MUX from a register value.
#define BG_IOMUXC_GPR1_MIPI_IPU2_MUX(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_MIPI_IPU2_MUX) >> BP_IOMUXC_GPR1_MIPI_IPU2_MUX)

//! @brief Format value for bitfield IOMUXC_GPR1_MIPI_IPU2_MUX.
#define BF_IOMUXC_GPR1_MIPI_IPU2_MUX(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_MIPI_IPU2_MUX) & BM_IOMUXC_GPR1_MIPI_IPU2_MUX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MIPI_IPU2_MUX field to a new value.
#define BW_IOMUXC_GPR1_MIPI_IPU2_MUX(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_MIPI_IPU2_MUX) | BF_IOMUXC_GPR1_MIPI_IPU2_MUX(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field ENET_CLK_SEL[21] (RW)
 *
 * ENET TX reference clock
 *
 * Values:
 * - 0 - get enet tx reference clk from pad (external OSC for both external PHY and Internal Controller)
 * - 1 - get enet tx reference clk from internal clock from anatop (loopback through pad), this clock also
 *     sent out to external PHY
 */
//@{
#define BP_IOMUXC_GPR1_ENET_CLK_SEL      (21)      //!< Bit position for IOMUXC_GPR1_ENET_CLK_SEL.
#define BM_IOMUXC_GPR1_ENET_CLK_SEL      (0x00200000)  //!< Bit mask for IOMUXC_GPR1_ENET_CLK_SEL.

//! @brief Get value of IOMUXC_GPR1_ENET_CLK_SEL from a register value.
#define BG_IOMUXC_GPR1_ENET_CLK_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_ENET_CLK_SEL) >> BP_IOMUXC_GPR1_ENET_CLK_SEL)

//! @brief Format value for bitfield IOMUXC_GPR1_ENET_CLK_SEL.
#define BF_IOMUXC_GPR1_ENET_CLK_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_ENET_CLK_SEL) & BM_IOMUXC_GPR1_ENET_CLK_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ENET_CLK_SEL field to a new value.
#define BW_IOMUXC_GPR1_ENET_CLK_SEL(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_ENET_CLK_SEL) | BF_IOMUXC_GPR1_ENET_CLK_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field EXC_MON[22] (RW)
 *
 * Exclusive monitor response select of illegal command (of lal gaskets, except MMDC)
 *
 * Values:
 * - 0 - OKEY response
 * - 1 - SLVError (default)
 */
//@{
#define BP_IOMUXC_GPR1_EXC_MON      (22)      //!< Bit position for IOMUXC_GPR1_EXC_MON.
#define BM_IOMUXC_GPR1_EXC_MON      (0x00400000)  //!< Bit mask for IOMUXC_GPR1_EXC_MON.

//! @brief Get value of IOMUXC_GPR1_EXC_MON from a register value.
#define BG_IOMUXC_GPR1_EXC_MON(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_EXC_MON) >> BP_IOMUXC_GPR1_EXC_MON)

//! @brief Format value for bitfield IOMUXC_GPR1_EXC_MON.
#define BF_IOMUXC_GPR1_EXC_MON(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_EXC_MON) & BM_IOMUXC_GPR1_EXC_MON)

#ifndef __LANGUAGE_ASM__
//! @brief Set the EXC_MON field to a new value.
#define BW_IOMUXC_GPR1_EXC_MON(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_EXC_MON) | BF_IOMUXC_GPR1_EXC_MON(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field MIPI_DPI_OFF[24] (RW)
 *
 * MIPI DPI shutdown request
 *
 * Values:
 * - 0 - MIPI DPI shutdown request is not set
 * - 1 - MIPI DPI shutdown request is set
 */
//@{
#define BP_IOMUXC_GPR1_MIPI_DPI_OFF      (24)      //!< Bit position for IOMUXC_GPR1_MIPI_DPI_OFF.
#define BM_IOMUXC_GPR1_MIPI_DPI_OFF      (0x01000000)  //!< Bit mask for IOMUXC_GPR1_MIPI_DPI_OFF.

//! @brief Get value of IOMUXC_GPR1_MIPI_DPI_OFF from a register value.
#define BG_IOMUXC_GPR1_MIPI_DPI_OFF(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_MIPI_DPI_OFF) >> BP_IOMUXC_GPR1_MIPI_DPI_OFF)

//! @brief Format value for bitfield IOMUXC_GPR1_MIPI_DPI_OFF.
#define BF_IOMUXC_GPR1_MIPI_DPI_OFF(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_MIPI_DPI_OFF) & BM_IOMUXC_GPR1_MIPI_DPI_OFF)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MIPI_DPI_OFF field to a new value.
#define BW_IOMUXC_GPR1_MIPI_DPI_OFF(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_MIPI_DPI_OFF) | BF_IOMUXC_GPR1_MIPI_DPI_OFF(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field MIPI_COLOR_SW[25] (RW)
 *
 * MIPI color switch control
 *
 * Values:
 * - 0 - MIPI color switch request is not set
 * - 1 - MIPI color switch request is set
 */
//@{
#define BP_IOMUXC_GPR1_MIPI_COLOR_SW      (25)      //!< Bit position for IOMUXC_GPR1_MIPI_COLOR_SW.
#define BM_IOMUXC_GPR1_MIPI_COLOR_SW      (0x02000000)  //!< Bit mask for IOMUXC_GPR1_MIPI_COLOR_SW.

//! @brief Get value of IOMUXC_GPR1_MIPI_COLOR_SW from a register value.
#define BG_IOMUXC_GPR1_MIPI_COLOR_SW(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_MIPI_COLOR_SW) >> BP_IOMUXC_GPR1_MIPI_COLOR_SW)

//! @brief Format value for bitfield IOMUXC_GPR1_MIPI_COLOR_SW.
#define BF_IOMUXC_GPR1_MIPI_COLOR_SW(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_MIPI_COLOR_SW) & BM_IOMUXC_GPR1_MIPI_COLOR_SW)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MIPI_COLOR_SW field to a new value.
#define BW_IOMUXC_GPR1_MIPI_COLOR_SW(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_MIPI_COLOR_SW) | BF_IOMUXC_GPR1_MIPI_COLOR_SW(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field APP_REQ_ENTR_L1[26] (RW)
 *
 * PCIe_CTL - Application Request to Enter L1. Request from the application to enter ASPM state L1.
 *
 * Values:
 * - 0 - PCIe application request is not set
 * - 1 - PCIe application request is set
 */
//@{
#define BP_IOMUXC_GPR1_APP_REQ_ENTR_L1      (26)      //!< Bit position for IOMUXC_GPR1_APP_REQ_ENTR_L1.
#define BM_IOMUXC_GPR1_APP_REQ_ENTR_L1      (0x04000000)  //!< Bit mask for IOMUXC_GPR1_APP_REQ_ENTR_L1.

//! @brief Get value of IOMUXC_GPR1_APP_REQ_ENTR_L1 from a register value.
#define BG_IOMUXC_GPR1_APP_REQ_ENTR_L1(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_APP_REQ_ENTR_L1) >> BP_IOMUXC_GPR1_APP_REQ_ENTR_L1)

//! @brief Format value for bitfield IOMUXC_GPR1_APP_REQ_ENTR_L1.
#define BF_IOMUXC_GPR1_APP_REQ_ENTR_L1(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_APP_REQ_ENTR_L1) & BM_IOMUXC_GPR1_APP_REQ_ENTR_L1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the APP_REQ_ENTR_L1 field to a new value.
#define BW_IOMUXC_GPR1_APP_REQ_ENTR_L1(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_APP_REQ_ENTR_L1) | BF_IOMUXC_GPR1_APP_REQ_ENTR_L1(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field APP_READY_ENTR_L23[27] (RW)
 *
 * PCIe_CTL - Application Ready to Enter L23. Indication from the application that it is ready to
 * enter the L23 state.
 *
 * Values:
 * - 0 - PCIe application is not ready to enter L23
 * - 1 - PCIe application is ready to enter L23
 */
//@{
#define BP_IOMUXC_GPR1_APP_READY_ENTR_L23      (27)      //!< Bit position for IOMUXC_GPR1_APP_READY_ENTR_L23.
#define BM_IOMUXC_GPR1_APP_READY_ENTR_L23      (0x08000000)  //!< Bit mask for IOMUXC_GPR1_APP_READY_ENTR_L23.

//! @brief Get value of IOMUXC_GPR1_APP_READY_ENTR_L23 from a register value.
#define BG_IOMUXC_GPR1_APP_READY_ENTR_L23(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_APP_READY_ENTR_L23) >> BP_IOMUXC_GPR1_APP_READY_ENTR_L23)

//! @brief Format value for bitfield IOMUXC_GPR1_APP_READY_ENTR_L23.
#define BF_IOMUXC_GPR1_APP_READY_ENTR_L23(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_APP_READY_ENTR_L23) & BM_IOMUXC_GPR1_APP_READY_ENTR_L23)

#ifndef __LANGUAGE_ASM__
//! @brief Set the APP_READY_ENTR_L23 field to a new value.
#define BW_IOMUXC_GPR1_APP_READY_ENTR_L23(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_APP_READY_ENTR_L23) | BF_IOMUXC_GPR1_APP_READY_ENTR_L23(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field APP_REQ_EXIT_L1[28] (RW)
 *
 * PCIe_CTL - Application Request to Exit L1. Request from the application to exit ASPM state L1.
 *
 * Values:
 * - 0 - PCIe application request is not set
 * - 1 - PCIe application request is set
 */
//@{
#define BP_IOMUXC_GPR1_APP_REQ_EXIT_L1      (28)      //!< Bit position for IOMUXC_GPR1_APP_REQ_EXIT_L1.
#define BM_IOMUXC_GPR1_APP_REQ_EXIT_L1      (0x10000000)  //!< Bit mask for IOMUXC_GPR1_APP_REQ_EXIT_L1.

//! @brief Get value of IOMUXC_GPR1_APP_REQ_EXIT_L1 from a register value.
#define BG_IOMUXC_GPR1_APP_REQ_EXIT_L1(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_APP_REQ_EXIT_L1) >> BP_IOMUXC_GPR1_APP_REQ_EXIT_L1)

//! @brief Format value for bitfield IOMUXC_GPR1_APP_REQ_EXIT_L1.
#define BF_IOMUXC_GPR1_APP_REQ_EXIT_L1(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_APP_REQ_EXIT_L1) & BM_IOMUXC_GPR1_APP_REQ_EXIT_L1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the APP_REQ_EXIT_L1 field to a new value.
#define BW_IOMUXC_GPR1_APP_REQ_EXIT_L1(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_APP_REQ_EXIT_L1) | BF_IOMUXC_GPR1_APP_REQ_EXIT_L1(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field APP_CLK_REQ_N[30] (RW)
 *
 * PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Indicates that application logic is ready to have
 * reference clock removed.
 */
//@{
#define BP_IOMUXC_GPR1_APP_CLK_REQ_N      (30)      //!< Bit position for IOMUXC_GPR1_APP_CLK_REQ_N.
#define BM_IOMUXC_GPR1_APP_CLK_REQ_N      (0x40000000)  //!< Bit mask for IOMUXC_GPR1_APP_CLK_REQ_N.

//! @brief Get value of IOMUXC_GPR1_APP_CLK_REQ_N from a register value.
#define BG_IOMUXC_GPR1_APP_CLK_REQ_N(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_APP_CLK_REQ_N) >> BP_IOMUXC_GPR1_APP_CLK_REQ_N)

//! @brief Format value for bitfield IOMUXC_GPR1_APP_CLK_REQ_N.
#define BF_IOMUXC_GPR1_APP_CLK_REQ_N(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_APP_CLK_REQ_N) & BM_IOMUXC_GPR1_APP_CLK_REQ_N)

#ifndef __LANGUAGE_ASM__
//! @brief Set the APP_CLK_REQ_N field to a new value.
#define BW_IOMUXC_GPR1_APP_CLK_REQ_N(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_APP_CLK_REQ_N) | BF_IOMUXC_GPR1_APP_CLK_REQ_N(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR1, field CFG_L1_CLK_REMOVAL_EN[31] (RW)
 *
 * PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Enable the reference clock removal in L1 state. This is a
 * bit from application register.
 */
//@{
#define BP_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN      (31)      //!< Bit position for IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN.
#define BM_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN      (0x80000000)  //!< Bit mask for IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN.

//! @brief Get value of IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN from a register value.
#define BG_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN) >> BP_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN)

//! @brief Format value for bitfield IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN.
#define BF_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN) & BM_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CFG_L1_CLK_REMOVAL_EN field to a new value.
#define BW_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN(v)   (HW_IOMUXC_GPR1_WR((HW_IOMUXC_GPR1_RD() & ~BM_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN) | BF_IOMUXC_GPR1_CFG_L1_CLK_REMOVAL_EN(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR2 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR2 - GPR (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_gpr2
{
    reg32_t U;
    struct _hw_iomuxc_gpr2_bitfields
    {
        unsigned CH0_MODE : 2; //!< [1:0] LVDS channel 0 operation mode
        unsigned CH1_MODE : 2; //!< [3:2] LVDS channel 1 operation mode
        unsigned SPLIT_MODE_EN : 1; //!< [4] Enable split mode.
        unsigned DATA_WIDTH_CH0 : 1; //!< [5] Data width for LVDS channel 0.
        unsigned BIT_MAPPING_CH0 : 1; //!< [6] Data mapping for LVDS channel 0.
        unsigned DATA_WIDTH_CH1 : 1; //!< [7] Data width for LVDS channel 1.
        unsigned BIT_MAPPING_CH1 : 1; //!< [8] Data mapping for LVDS channel 1.
        unsigned DI0_VS_POLARITY : 1; //!< [9] Vsync polarity for IPU's DI0 interface.
        unsigned DI1_VS_POLARITY : 1; //!< [10] Vsync polarity for IPU's DI1 interface.
        unsigned RESERVED0 : 5; //!< [15:11] Reserved
        unsigned LVDS_CLK_SHIFT : 3; //!< [18:16] Shifts the LVDS output clock in relation to the data.
        unsigned RESERVED1 : 1; //!< [19] Reserved
        unsigned COUNTER_RESET_VAL : 2; //!< [21:20] Reset value for the LDB counter which determines when the shift registers are loaded with data.
        unsigned RESERVED2 : 10; //!< [31:22] Reserved
    } B;
} hw_iomuxc_gpr2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR2 register
 */
//@{
#define HW_IOMUXC_GPR2_ADDR      (REGS_IOMUXC_BASE + 0x8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR2           (*(volatile hw_iomuxc_gpr2_t *) HW_IOMUXC_GPR2_ADDR)
#define HW_IOMUXC_GPR2_RD()      (HW_IOMUXC_GPR2.U)
#define HW_IOMUXC_GPR2_WR(v)     (HW_IOMUXC_GPR2.U = (v))
#define HW_IOMUXC_GPR2_SET(v)    (HW_IOMUXC_GPR2_WR(HW_IOMUXC_GPR2_RD() |  (v)))
#define HW_IOMUXC_GPR2_CLR(v)    (HW_IOMUXC_GPR2_WR(HW_IOMUXC_GPR2_RD() & ~(v)))
#define HW_IOMUXC_GPR2_TOG(v)    (HW_IOMUXC_GPR2_WR(HW_IOMUXC_GPR2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR2 bitfields
 */

/*! @name Register IOMUXC_GPR2, field CH0_MODE[1:0] (RW)
 *
 * LVDS channel 0 operation mode
 *
 * Values:
 * - 00 - Channel disabled.
 * - 01 - Channel enabled, routed to DI0
 * - 10 - Channel disabled.
 * - 11 - Channel enabled, routed to DI1.
 */
//@{
#define BP_IOMUXC_GPR2_CH0_MODE      (0)      //!< Bit position for IOMUXC_GPR2_CH0_MODE.
#define BM_IOMUXC_GPR2_CH0_MODE      (0x00000003)  //!< Bit mask for IOMUXC_GPR2_CH0_MODE.

//! @brief Get value of IOMUXC_GPR2_CH0_MODE from a register value.
#define BG_IOMUXC_GPR2_CH0_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_CH0_MODE) >> BP_IOMUXC_GPR2_CH0_MODE)

//! @brief Format value for bitfield IOMUXC_GPR2_CH0_MODE.
#define BF_IOMUXC_GPR2_CH0_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_CH0_MODE) & BM_IOMUXC_GPR2_CH0_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CH0_MODE field to a new value.
#define BW_IOMUXC_GPR2_CH0_MODE(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_CH0_MODE) | BF_IOMUXC_GPR2_CH0_MODE(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field CH1_MODE[3:2] (RW)
 *
 * LVDS channel 1 operation mode
 *
 * Values:
 * - 00 - Channel disabled.
 * - 01 - Channel enabled, routed to DI0
 * - 10 - Channel disabled.
 * - 11 - Channel enabled, routed to DI1.
 */
//@{
#define BP_IOMUXC_GPR2_CH1_MODE      (2)      //!< Bit position for IOMUXC_GPR2_CH1_MODE.
#define BM_IOMUXC_GPR2_CH1_MODE      (0x0000000c)  //!< Bit mask for IOMUXC_GPR2_CH1_MODE.

//! @brief Get value of IOMUXC_GPR2_CH1_MODE from a register value.
#define BG_IOMUXC_GPR2_CH1_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_CH1_MODE) >> BP_IOMUXC_GPR2_CH1_MODE)

//! @brief Format value for bitfield IOMUXC_GPR2_CH1_MODE.
#define BF_IOMUXC_GPR2_CH1_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_CH1_MODE) & BM_IOMUXC_GPR2_CH1_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CH1_MODE field to a new value.
#define BW_IOMUXC_GPR2_CH1_MODE(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_CH1_MODE) | BF_IOMUXC_GPR2_CH1_MODE(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field SPLIT_MODE_EN[4] (RW)
 *
 * Enable split mode.
 *
 * Values:
 * - 0 - Split mode is disabled.
 * - 1 - Split mode is enabled. In this mode both channels should be enabled and working with the same DI
 *     (ch0_mode and ch1_mode should both be either '01' or '11')
 */
//@{
#define BP_IOMUXC_GPR2_SPLIT_MODE_EN      (4)      //!< Bit position for IOMUXC_GPR2_SPLIT_MODE_EN.
#define BM_IOMUXC_GPR2_SPLIT_MODE_EN      (0x00000010)  //!< Bit mask for IOMUXC_GPR2_SPLIT_MODE_EN.

//! @brief Get value of IOMUXC_GPR2_SPLIT_MODE_EN from a register value.
#define BG_IOMUXC_GPR2_SPLIT_MODE_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_SPLIT_MODE_EN) >> BP_IOMUXC_GPR2_SPLIT_MODE_EN)

//! @brief Format value for bitfield IOMUXC_GPR2_SPLIT_MODE_EN.
#define BF_IOMUXC_GPR2_SPLIT_MODE_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_SPLIT_MODE_EN) & BM_IOMUXC_GPR2_SPLIT_MODE_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPLIT_MODE_EN field to a new value.
#define BW_IOMUXC_GPR2_SPLIT_MODE_EN(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_SPLIT_MODE_EN) | BF_IOMUXC_GPR2_SPLIT_MODE_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field DATA_WIDTH_CH0[5] (RW)
 *
 * Data width for LVDS channel 0. This bit must be set when using JEIDA standard (bit_mapping_ch0 is
 * set)
 *
 * Values:
 * - 0 - Data width is 18 bits wide (lvds0_tx3 is not used)
 * - 1 - Data width is 24 bits wide.
 */
//@{
#define BP_IOMUXC_GPR2_DATA_WIDTH_CH0      (5)      //!< Bit position for IOMUXC_GPR2_DATA_WIDTH_CH0.
#define BM_IOMUXC_GPR2_DATA_WIDTH_CH0      (0x00000020)  //!< Bit mask for IOMUXC_GPR2_DATA_WIDTH_CH0.

//! @brief Get value of IOMUXC_GPR2_DATA_WIDTH_CH0 from a register value.
#define BG_IOMUXC_GPR2_DATA_WIDTH_CH0(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_DATA_WIDTH_CH0) >> BP_IOMUXC_GPR2_DATA_WIDTH_CH0)

//! @brief Format value for bitfield IOMUXC_GPR2_DATA_WIDTH_CH0.
#define BF_IOMUXC_GPR2_DATA_WIDTH_CH0(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_DATA_WIDTH_CH0) & BM_IOMUXC_GPR2_DATA_WIDTH_CH0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DATA_WIDTH_CH0 field to a new value.
#define BW_IOMUXC_GPR2_DATA_WIDTH_CH0(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_DATA_WIDTH_CH0) | BF_IOMUXC_GPR2_DATA_WIDTH_CH0(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field BIT_MAPPING_CH0[6] (RW)
 *
 * Data mapping for LVDS channel 0.
 *
 * Values:
 * - 0 - Use SPWG standard.
 * - 1 - Use JEIDA standard.
 */
//@{
#define BP_IOMUXC_GPR2_BIT_MAPPING_CH0      (6)      //!< Bit position for IOMUXC_GPR2_BIT_MAPPING_CH0.
#define BM_IOMUXC_GPR2_BIT_MAPPING_CH0      (0x00000040)  //!< Bit mask for IOMUXC_GPR2_BIT_MAPPING_CH0.

//! @brief Get value of IOMUXC_GPR2_BIT_MAPPING_CH0 from a register value.
#define BG_IOMUXC_GPR2_BIT_MAPPING_CH0(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_BIT_MAPPING_CH0) >> BP_IOMUXC_GPR2_BIT_MAPPING_CH0)

//! @brief Format value for bitfield IOMUXC_GPR2_BIT_MAPPING_CH0.
#define BF_IOMUXC_GPR2_BIT_MAPPING_CH0(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_BIT_MAPPING_CH0) & BM_IOMUXC_GPR2_BIT_MAPPING_CH0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the BIT_MAPPING_CH0 field to a new value.
#define BW_IOMUXC_GPR2_BIT_MAPPING_CH0(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_BIT_MAPPING_CH0) | BF_IOMUXC_GPR2_BIT_MAPPING_CH0(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field DATA_WIDTH_CH1[7] (RW)
 *
 * Data width for LVDS channel 1. This bit must be set when using JEIDA standard (bit_mapping_ch1 is
 * set)
 *
 * Values:
 * - 0 - Data width is 18 bits wide (lvds1_tx3 is not used)
 * - 1 - Data width is 24 bits wide.
 */
//@{
#define BP_IOMUXC_GPR2_DATA_WIDTH_CH1      (7)      //!< Bit position for IOMUXC_GPR2_DATA_WIDTH_CH1.
#define BM_IOMUXC_GPR2_DATA_WIDTH_CH1      (0x00000080)  //!< Bit mask for IOMUXC_GPR2_DATA_WIDTH_CH1.

//! @brief Get value of IOMUXC_GPR2_DATA_WIDTH_CH1 from a register value.
#define BG_IOMUXC_GPR2_DATA_WIDTH_CH1(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_DATA_WIDTH_CH1) >> BP_IOMUXC_GPR2_DATA_WIDTH_CH1)

//! @brief Format value for bitfield IOMUXC_GPR2_DATA_WIDTH_CH1.
#define BF_IOMUXC_GPR2_DATA_WIDTH_CH1(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_DATA_WIDTH_CH1) & BM_IOMUXC_GPR2_DATA_WIDTH_CH1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DATA_WIDTH_CH1 field to a new value.
#define BW_IOMUXC_GPR2_DATA_WIDTH_CH1(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_DATA_WIDTH_CH1) | BF_IOMUXC_GPR2_DATA_WIDTH_CH1(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field BIT_MAPPING_CH1[8] (RW)
 *
 * Data mapping for LVDS channel 1.
 *
 * Values:
 * - 0 - Use SPWG standard.
 * - 1 - Use JEIDA standard.
 */
//@{
#define BP_IOMUXC_GPR2_BIT_MAPPING_CH1      (8)      //!< Bit position for IOMUXC_GPR2_BIT_MAPPING_CH1.
#define BM_IOMUXC_GPR2_BIT_MAPPING_CH1      (0x00000100)  //!< Bit mask for IOMUXC_GPR2_BIT_MAPPING_CH1.

//! @brief Get value of IOMUXC_GPR2_BIT_MAPPING_CH1 from a register value.
#define BG_IOMUXC_GPR2_BIT_MAPPING_CH1(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_BIT_MAPPING_CH1) >> BP_IOMUXC_GPR2_BIT_MAPPING_CH1)

//! @brief Format value for bitfield IOMUXC_GPR2_BIT_MAPPING_CH1.
#define BF_IOMUXC_GPR2_BIT_MAPPING_CH1(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_BIT_MAPPING_CH1) & BM_IOMUXC_GPR2_BIT_MAPPING_CH1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the BIT_MAPPING_CH1 field to a new value.
#define BW_IOMUXC_GPR2_BIT_MAPPING_CH1(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_BIT_MAPPING_CH1) | BF_IOMUXC_GPR2_BIT_MAPPING_CH1(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field DI0_VS_POLARITY[9] (RW)
 *
 * Vsync polarity for IPU's DI0 interface.
 *
 * Values:
 * - 0 - ipu_di0_vsync is active high.
 * - 1 - ipu_di0_vsync is active low.
 */
//@{
#define BP_IOMUXC_GPR2_DI0_VS_POLARITY      (9)      //!< Bit position for IOMUXC_GPR2_DI0_VS_POLARITY.
#define BM_IOMUXC_GPR2_DI0_VS_POLARITY      (0x00000200)  //!< Bit mask for IOMUXC_GPR2_DI0_VS_POLARITY.

//! @brief Get value of IOMUXC_GPR2_DI0_VS_POLARITY from a register value.
#define BG_IOMUXC_GPR2_DI0_VS_POLARITY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_DI0_VS_POLARITY) >> BP_IOMUXC_GPR2_DI0_VS_POLARITY)

//! @brief Format value for bitfield IOMUXC_GPR2_DI0_VS_POLARITY.
#define BF_IOMUXC_GPR2_DI0_VS_POLARITY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_DI0_VS_POLARITY) & BM_IOMUXC_GPR2_DI0_VS_POLARITY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DI0_VS_POLARITY field to a new value.
#define BW_IOMUXC_GPR2_DI0_VS_POLARITY(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_DI0_VS_POLARITY) | BF_IOMUXC_GPR2_DI0_VS_POLARITY(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field DI1_VS_POLARITY[10] (RW)
 *
 * Vsync polarity for IPU's DI1 interface.
 *
 * Values:
 * - 0 - ipu_di1_vsync is active high.
 * - 1 - ipu_di1_vsync is active low.
 */
//@{
#define BP_IOMUXC_GPR2_DI1_VS_POLARITY      (10)      //!< Bit position for IOMUXC_GPR2_DI1_VS_POLARITY.
#define BM_IOMUXC_GPR2_DI1_VS_POLARITY      (0x00000400)  //!< Bit mask for IOMUXC_GPR2_DI1_VS_POLARITY.

//! @brief Get value of IOMUXC_GPR2_DI1_VS_POLARITY from a register value.
#define BG_IOMUXC_GPR2_DI1_VS_POLARITY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_DI1_VS_POLARITY) >> BP_IOMUXC_GPR2_DI1_VS_POLARITY)

//! @brief Format value for bitfield IOMUXC_GPR2_DI1_VS_POLARITY.
#define BF_IOMUXC_GPR2_DI1_VS_POLARITY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_DI1_VS_POLARITY) & BM_IOMUXC_GPR2_DI1_VS_POLARITY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DI1_VS_POLARITY field to a new value.
#define BW_IOMUXC_GPR2_DI1_VS_POLARITY(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_DI1_VS_POLARITY) | BF_IOMUXC_GPR2_DI1_VS_POLARITY(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field LVDS_CLK_SHIFT[18:16] (RW)
 *
 * Shifts the LVDS output clock in relation to the data. Used for debug purposes only. In normal
 * functional operation must be '000'
 *
 * Values:
 * - 000 - Output clock is '1100011' (normal operation)
 * - 001 - Output clock is '1110001'
 * - 010 - Output clock is '1111000'
 * - 011 - Output clock is '1000111'
 * - 100 - Output clock is '0001111'
 * - 101 - Output clock is '0011111'
 * - 110 - Output clock is '0111100'
 * - 111 - Output clock is '1100011'
 */
//@{
#define BP_IOMUXC_GPR2_LVDS_CLK_SHIFT      (16)      //!< Bit position for IOMUXC_GPR2_LVDS_CLK_SHIFT.
#define BM_IOMUXC_GPR2_LVDS_CLK_SHIFT      (0x00070000)  //!< Bit mask for IOMUXC_GPR2_LVDS_CLK_SHIFT.

//! @brief Get value of IOMUXC_GPR2_LVDS_CLK_SHIFT from a register value.
#define BG_IOMUXC_GPR2_LVDS_CLK_SHIFT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_LVDS_CLK_SHIFT) >> BP_IOMUXC_GPR2_LVDS_CLK_SHIFT)

//! @brief Format value for bitfield IOMUXC_GPR2_LVDS_CLK_SHIFT.
#define BF_IOMUXC_GPR2_LVDS_CLK_SHIFT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_LVDS_CLK_SHIFT) & BM_IOMUXC_GPR2_LVDS_CLK_SHIFT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LVDS_CLK_SHIFT field to a new value.
#define BW_IOMUXC_GPR2_LVDS_CLK_SHIFT(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_LVDS_CLK_SHIFT) | BF_IOMUXC_GPR2_LVDS_CLK_SHIFT(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR2, field COUNTER_RESET_VAL[21:20] (RW)
 *
 * Reset value for the LDB counter which determines when the shift registers are loaded with data.
 * Used for debug purposes only. In normal functional operation must be '00'
 *
 * Values:
 * - 00 - Reset value is 5
 * - 01 - Reset value is 3
 * - 10 - Reset value is 4
 * - 11 - Reset value is 6
 */
//@{
#define BP_IOMUXC_GPR2_COUNTER_RESET_VAL      (20)      //!< Bit position for IOMUXC_GPR2_COUNTER_RESET_VAL.
#define BM_IOMUXC_GPR2_COUNTER_RESET_VAL      (0x00300000)  //!< Bit mask for IOMUXC_GPR2_COUNTER_RESET_VAL.

//! @brief Get value of IOMUXC_GPR2_COUNTER_RESET_VAL from a register value.
#define BG_IOMUXC_GPR2_COUNTER_RESET_VAL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR2_COUNTER_RESET_VAL) >> BP_IOMUXC_GPR2_COUNTER_RESET_VAL)

//! @brief Format value for bitfield IOMUXC_GPR2_COUNTER_RESET_VAL.
#define BF_IOMUXC_GPR2_COUNTER_RESET_VAL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR2_COUNTER_RESET_VAL) & BM_IOMUXC_GPR2_COUNTER_RESET_VAL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the COUNTER_RESET_VAL field to a new value.
#define BW_IOMUXC_GPR2_COUNTER_RESET_VAL(v)   (HW_IOMUXC_GPR2_WR((HW_IOMUXC_GPR2_RD() & ~BM_IOMUXC_GPR2_COUNTER_RESET_VAL) | BF_IOMUXC_GPR2_COUNTER_RESET_VAL(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR3 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR3 - GPR (RW)
 *
 * Reset value: 0x01e00000
 */
typedef union _hw_iomuxc_gpr3
{
    reg32_t U;
    struct _hw_iomuxc_gpr3_bitfields
    {
        unsigned RESERVED0 : 2; //!< [1:0] Reserved
        unsigned HDMI_MUX_CTL : 2; //!< [3:2] HDMI MUX control
        unsigned MIPI_MUX_CTL : 2; //!< [5:4] MIPI MUX control
        unsigned LVDS0_MUX_CTL : 2; //!< [7:6] LVDS0 MUX control
        unsigned LVDS1_MUX_CTL : 2; //!< [9:8] LVDS1 MUX control
        unsigned IPU_DIAG : 1; //!< [10] IPU diagnostic debug bus mux
        unsigned TZASC1_BOOT_LOCK : 1; //!< [11] TZASC-1 secure boot lock
        unsigned TZASC2_BOOT_LOCK : 1; //!< [12] TZASC-2 secure boot lock
        unsigned CORE0_DBG_ACK_EN : 1; //!< [13] Mask control of Core 1 debug acknowledge to global debug acknowledge
        unsigned CORE1_DBG_ACK_EN : 1; //!< [14] Mask control of Core 1 debug acknowledge to global debug acknowledge.
        unsigned CORE2_DBG_ACK_EN : 1; //!< [15] Mask control of Core 2 debug acknowledge to global debug acknowledge
        unsigned CORE3_DBG_ACK_EN : 1; //!< [16] Mask control of Core 3 debug acknowledge to global debug acknowledge
        unsigned OCRAM_STATUS : 4; //!< [20:17] This field shows the OCRAM pipeline settings status, controlled by OCRAM_CTL[24:21] bits respectively.
        unsigned OCRAM_CTL : 4; //!< [24:21] OCRAM_CTL[24] write address pipeline control bit.
        unsigned USDHCX_RD_CACHE_CTL : 1; //!< [25] Control uSDHCx [1-4] blocks cacheable attribute of AXI read transactions
        unsigned USDHCX_WR_CACHE_CTL : 1; //!< [26] Control uSDHCx [1-4] blocks cacheable attribute of AXI write transactions
        unsigned BCH_RD_CACHE_CTL : 1; //!< [27] Control BCH block cacheable attribute of AXI read transactions Set of the cache bits, enable packet optimization through the bus system to DDR controller.
        unsigned BCH_WR_CACHE_CTL : 1; //!< [28] Control BCH block cacheable attribute of AXI write transactions
        unsigned GPU_DBG : 2; //!< [30:29] GPU debug busses to IOMUX
        unsigned RESERVED1 : 1; //!< [31] Reserved
    } B;
} hw_iomuxc_gpr3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR3 register
 */
//@{
#define HW_IOMUXC_GPR3_ADDR      (REGS_IOMUXC_BASE + 0xc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR3           (*(volatile hw_iomuxc_gpr3_t *) HW_IOMUXC_GPR3_ADDR)
#define HW_IOMUXC_GPR3_RD()      (HW_IOMUXC_GPR3.U)
#define HW_IOMUXC_GPR3_WR(v)     (HW_IOMUXC_GPR3.U = (v))
#define HW_IOMUXC_GPR3_SET(v)    (HW_IOMUXC_GPR3_WR(HW_IOMUXC_GPR3_RD() |  (v)))
#define HW_IOMUXC_GPR3_CLR(v)    (HW_IOMUXC_GPR3_WR(HW_IOMUXC_GPR3_RD() & ~(v)))
#define HW_IOMUXC_GPR3_TOG(v)    (HW_IOMUXC_GPR3_WR(HW_IOMUXC_GPR3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR3 bitfields
 */

/*! @name Register IOMUXC_GPR3, field HDMI_MUX_CTL[3:2] (RW)
 *
 * HDMI MUX control
 *
 * Values:
 * - 00 - HDMI source is IPU1 DI0 port
 * - 01 - HDMI source is IPU1 DI1 port
 * - 10 - HDMI source is IPU2 DI0 port
 * - 11 - HDMI source is IPU2 DI1 port
 */
//@{
#define BP_IOMUXC_GPR3_HDMI_MUX_CTL      (2)      //!< Bit position for IOMUXC_GPR3_HDMI_MUX_CTL.
#define BM_IOMUXC_GPR3_HDMI_MUX_CTL      (0x0000000c)  //!< Bit mask for IOMUXC_GPR3_HDMI_MUX_CTL.

//! @brief Get value of IOMUXC_GPR3_HDMI_MUX_CTL from a register value.
#define BG_IOMUXC_GPR3_HDMI_MUX_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_HDMI_MUX_CTL) >> BP_IOMUXC_GPR3_HDMI_MUX_CTL)

//! @brief Format value for bitfield IOMUXC_GPR3_HDMI_MUX_CTL.
#define BF_IOMUXC_GPR3_HDMI_MUX_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_HDMI_MUX_CTL) & BM_IOMUXC_GPR3_HDMI_MUX_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HDMI_MUX_CTL field to a new value.
#define BW_IOMUXC_GPR3_HDMI_MUX_CTL(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_HDMI_MUX_CTL) | BF_IOMUXC_GPR3_HDMI_MUX_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field MIPI_MUX_CTL[5:4] (RW)
 *
 * MIPI MUX control
 *
 * Values:
 * - 00 - MIPI source is IPU1 DI0 port
 * - 01 - MIPI source is IPU1 DI1 port
 * - 10 - MIPI source is IPU2 DI0 port
 * - 11 - MIPI source is IPU2 DI1 port
 */
//@{
#define BP_IOMUXC_GPR3_MIPI_MUX_CTL      (4)      //!< Bit position for IOMUXC_GPR3_MIPI_MUX_CTL.
#define BM_IOMUXC_GPR3_MIPI_MUX_CTL      (0x00000030)  //!< Bit mask for IOMUXC_GPR3_MIPI_MUX_CTL.

//! @brief Get value of IOMUXC_GPR3_MIPI_MUX_CTL from a register value.
#define BG_IOMUXC_GPR3_MIPI_MUX_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_MIPI_MUX_CTL) >> BP_IOMUXC_GPR3_MIPI_MUX_CTL)

//! @brief Format value for bitfield IOMUXC_GPR3_MIPI_MUX_CTL.
#define BF_IOMUXC_GPR3_MIPI_MUX_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_MIPI_MUX_CTL) & BM_IOMUXC_GPR3_MIPI_MUX_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MIPI_MUX_CTL field to a new value.
#define BW_IOMUXC_GPR3_MIPI_MUX_CTL(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_MIPI_MUX_CTL) | BF_IOMUXC_GPR3_MIPI_MUX_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field LVDS0_MUX_CTL[7:6] (RW)
 *
 * LVDS0 MUX control
 *
 * Values:
 * - 00 - LVDS0 source is IPU1 DI0 port
 * - 01 - LVDS0 source is IPU1 DI1 port
 * - 10 - LVDS0 source is IPU2 DI0 port
 * - 11 - LVDS0 source is IPU2 DI1 port
 */
//@{
#define BP_IOMUXC_GPR3_LVDS0_MUX_CTL      (6)      //!< Bit position for IOMUXC_GPR3_LVDS0_MUX_CTL.
#define BM_IOMUXC_GPR3_LVDS0_MUX_CTL      (0x000000c0)  //!< Bit mask for IOMUXC_GPR3_LVDS0_MUX_CTL.

//! @brief Get value of IOMUXC_GPR3_LVDS0_MUX_CTL from a register value.
#define BG_IOMUXC_GPR3_LVDS0_MUX_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_LVDS0_MUX_CTL) >> BP_IOMUXC_GPR3_LVDS0_MUX_CTL)

//! @brief Format value for bitfield IOMUXC_GPR3_LVDS0_MUX_CTL.
#define BF_IOMUXC_GPR3_LVDS0_MUX_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_LVDS0_MUX_CTL) & BM_IOMUXC_GPR3_LVDS0_MUX_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LVDS0_MUX_CTL field to a new value.
#define BW_IOMUXC_GPR3_LVDS0_MUX_CTL(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_LVDS0_MUX_CTL) | BF_IOMUXC_GPR3_LVDS0_MUX_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field LVDS1_MUX_CTL[9:8] (RW)
 *
 * LVDS1 MUX control
 *
 * Values:
 * - 00 - LVDS1 source is IPU1 DI0 port
 * - 01 - LVDS1 source is IPU1 DI1 port
 * - 10 - LVDS1 source is IPU2 DI0 port
 * - 11 - LVDS1 source is IPU2 DI1 port
 */
//@{
#define BP_IOMUXC_GPR3_LVDS1_MUX_CTL      (8)      //!< Bit position for IOMUXC_GPR3_LVDS1_MUX_CTL.
#define BM_IOMUXC_GPR3_LVDS1_MUX_CTL      (0x00000300)  //!< Bit mask for IOMUXC_GPR3_LVDS1_MUX_CTL.

//! @brief Get value of IOMUXC_GPR3_LVDS1_MUX_CTL from a register value.
#define BG_IOMUXC_GPR3_LVDS1_MUX_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_LVDS1_MUX_CTL) >> BP_IOMUXC_GPR3_LVDS1_MUX_CTL)

//! @brief Format value for bitfield IOMUXC_GPR3_LVDS1_MUX_CTL.
#define BF_IOMUXC_GPR3_LVDS1_MUX_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_LVDS1_MUX_CTL) & BM_IOMUXC_GPR3_LVDS1_MUX_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LVDS1_MUX_CTL field to a new value.
#define BW_IOMUXC_GPR3_LVDS1_MUX_CTL(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_LVDS1_MUX_CTL) | BF_IOMUXC_GPR3_LVDS1_MUX_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field IPU_DIAG[10] (RW)
 *
 * IPU diagnostic debug bus mux
 *
 * Values:
 * - 0 - IPU1 diagnostic bus is selected
 * - 1 - IPU2 diagnostic bus is selected
 */
//@{
#define BP_IOMUXC_GPR3_IPU_DIAG      (10)      //!< Bit position for IOMUXC_GPR3_IPU_DIAG.
#define BM_IOMUXC_GPR3_IPU_DIAG      (0x00000400)  //!< Bit mask for IOMUXC_GPR3_IPU_DIAG.

//! @brief Get value of IOMUXC_GPR3_IPU_DIAG from a register value.
#define BG_IOMUXC_GPR3_IPU_DIAG(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_IPU_DIAG) >> BP_IOMUXC_GPR3_IPU_DIAG)

//! @brief Format value for bitfield IOMUXC_GPR3_IPU_DIAG.
#define BF_IOMUXC_GPR3_IPU_DIAG(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_IPU_DIAG) & BM_IOMUXC_GPR3_IPU_DIAG)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU_DIAG field to a new value.
#define BW_IOMUXC_GPR3_IPU_DIAG(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_IPU_DIAG) | BF_IOMUXC_GPR3_IPU_DIAG(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field TZASC1_BOOT_LOCK[11] (RW)
 *
 * TZASC-1 secure boot lock
 *
 * Values:
 * - 0 - secure boot lock is disabled.
 * - 1 - secure boot lock is enabled
 */
//@{
#define BP_IOMUXC_GPR3_TZASC1_BOOT_LOCK      (11)      //!< Bit position for IOMUXC_GPR3_TZASC1_BOOT_LOCK.
#define BM_IOMUXC_GPR3_TZASC1_BOOT_LOCK      (0x00000800)  //!< Bit mask for IOMUXC_GPR3_TZASC1_BOOT_LOCK.

//! @brief Get value of IOMUXC_GPR3_TZASC1_BOOT_LOCK from a register value.
#define BG_IOMUXC_GPR3_TZASC1_BOOT_LOCK(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_TZASC1_BOOT_LOCK) >> BP_IOMUXC_GPR3_TZASC1_BOOT_LOCK)

//! @brief Format value for bitfield IOMUXC_GPR3_TZASC1_BOOT_LOCK.
#define BF_IOMUXC_GPR3_TZASC1_BOOT_LOCK(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_TZASC1_BOOT_LOCK) & BM_IOMUXC_GPR3_TZASC1_BOOT_LOCK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TZASC1_BOOT_LOCK field to a new value.
#define BW_IOMUXC_GPR3_TZASC1_BOOT_LOCK(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_TZASC1_BOOT_LOCK) | BF_IOMUXC_GPR3_TZASC1_BOOT_LOCK(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field TZASC2_BOOT_LOCK[12] (RW)
 *
 * TZASC-2 secure boot lock
 *
 * Values:
 * - 0 - secure boot lock is disabled.
 * - 1 - secure boot lock is enabled
 */
//@{
#define BP_IOMUXC_GPR3_TZASC2_BOOT_LOCK      (12)      //!< Bit position for IOMUXC_GPR3_TZASC2_BOOT_LOCK.
#define BM_IOMUXC_GPR3_TZASC2_BOOT_LOCK      (0x00001000)  //!< Bit mask for IOMUXC_GPR3_TZASC2_BOOT_LOCK.

//! @brief Get value of IOMUXC_GPR3_TZASC2_BOOT_LOCK from a register value.
#define BG_IOMUXC_GPR3_TZASC2_BOOT_LOCK(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_TZASC2_BOOT_LOCK) >> BP_IOMUXC_GPR3_TZASC2_BOOT_LOCK)

//! @brief Format value for bitfield IOMUXC_GPR3_TZASC2_BOOT_LOCK.
#define BF_IOMUXC_GPR3_TZASC2_BOOT_LOCK(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_TZASC2_BOOT_LOCK) & BM_IOMUXC_GPR3_TZASC2_BOOT_LOCK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TZASC2_BOOT_LOCK field to a new value.
#define BW_IOMUXC_GPR3_TZASC2_BOOT_LOCK(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_TZASC2_BOOT_LOCK) | BF_IOMUXC_GPR3_TZASC2_BOOT_LOCK(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field CORE0_DBG_ACK_EN[13] (RW)
 *
 * Mask control of Core 1 debug acknowledge to global debug acknowledge
 *
 * Values:
 * - 0 - Core 0 debug acknowledge is part of global acknowledge.
 * - 1 - Core 0 debug acknowledge is masked by this bit, and it is not part of global acknowledge.
 */
//@{
#define BP_IOMUXC_GPR3_CORE0_DBG_ACK_EN      (13)      //!< Bit position for IOMUXC_GPR3_CORE0_DBG_ACK_EN.
#define BM_IOMUXC_GPR3_CORE0_DBG_ACK_EN      (0x00002000)  //!< Bit mask for IOMUXC_GPR3_CORE0_DBG_ACK_EN.

//! @brief Get value of IOMUXC_GPR3_CORE0_DBG_ACK_EN from a register value.
#define BG_IOMUXC_GPR3_CORE0_DBG_ACK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_CORE0_DBG_ACK_EN) >> BP_IOMUXC_GPR3_CORE0_DBG_ACK_EN)

//! @brief Format value for bitfield IOMUXC_GPR3_CORE0_DBG_ACK_EN.
#define BF_IOMUXC_GPR3_CORE0_DBG_ACK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_CORE0_DBG_ACK_EN) & BM_IOMUXC_GPR3_CORE0_DBG_ACK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CORE0_DBG_ACK_EN field to a new value.
#define BW_IOMUXC_GPR3_CORE0_DBG_ACK_EN(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_CORE0_DBG_ACK_EN) | BF_IOMUXC_GPR3_CORE0_DBG_ACK_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field CORE1_DBG_ACK_EN[14] (RW)
 *
 * Mask control of Core 1 debug acknowledge to global debug acknowledge.
 *
 * Values:
 * - 0 - Core 1 debug acknowledge is part of global acknowledge.
 * - 1 - Core 1 debug acknowledge is masked by this bit, and it is not part of global acknowledge.
 */
//@{
#define BP_IOMUXC_GPR3_CORE1_DBG_ACK_EN      (14)      //!< Bit position for IOMUXC_GPR3_CORE1_DBG_ACK_EN.
#define BM_IOMUXC_GPR3_CORE1_DBG_ACK_EN      (0x00004000)  //!< Bit mask for IOMUXC_GPR3_CORE1_DBG_ACK_EN.

//! @brief Get value of IOMUXC_GPR3_CORE1_DBG_ACK_EN from a register value.
#define BG_IOMUXC_GPR3_CORE1_DBG_ACK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_CORE1_DBG_ACK_EN) >> BP_IOMUXC_GPR3_CORE1_DBG_ACK_EN)

//! @brief Format value for bitfield IOMUXC_GPR3_CORE1_DBG_ACK_EN.
#define BF_IOMUXC_GPR3_CORE1_DBG_ACK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_CORE1_DBG_ACK_EN) & BM_IOMUXC_GPR3_CORE1_DBG_ACK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CORE1_DBG_ACK_EN field to a new value.
#define BW_IOMUXC_GPR3_CORE1_DBG_ACK_EN(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_CORE1_DBG_ACK_EN) | BF_IOMUXC_GPR3_CORE1_DBG_ACK_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field CORE2_DBG_ACK_EN[15] (RW)
 *
 * Mask control of Core 2 debug acknowledge to global debug acknowledge
 *
 * Values:
 * - 0 - Core 2 debug acknowledge is part of global acknowledge.
 * - 1 - Core 2 debug acknowledge is masked by this bit, and it is not part of global acknowledge.
 */
//@{
#define BP_IOMUXC_GPR3_CORE2_DBG_ACK_EN      (15)      //!< Bit position for IOMUXC_GPR3_CORE2_DBG_ACK_EN.
#define BM_IOMUXC_GPR3_CORE2_DBG_ACK_EN      (0x00008000)  //!< Bit mask for IOMUXC_GPR3_CORE2_DBG_ACK_EN.

//! @brief Get value of IOMUXC_GPR3_CORE2_DBG_ACK_EN from a register value.
#define BG_IOMUXC_GPR3_CORE2_DBG_ACK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_CORE2_DBG_ACK_EN) >> BP_IOMUXC_GPR3_CORE2_DBG_ACK_EN)

//! @brief Format value for bitfield IOMUXC_GPR3_CORE2_DBG_ACK_EN.
#define BF_IOMUXC_GPR3_CORE2_DBG_ACK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_CORE2_DBG_ACK_EN) & BM_IOMUXC_GPR3_CORE2_DBG_ACK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CORE2_DBG_ACK_EN field to a new value.
#define BW_IOMUXC_GPR3_CORE2_DBG_ACK_EN(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_CORE2_DBG_ACK_EN) | BF_IOMUXC_GPR3_CORE2_DBG_ACK_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field CORE3_DBG_ACK_EN[16] (RW)
 *
 * Mask control of Core 3 debug acknowledge to global debug acknowledge
 *
 * Values:
 * - 0 - Core 3 debug acknowledge is part of global acknowledge.
 * - 1 - Core 3 debug acknowledge is masked by this bit, and it is not part of global acknowledge.
 */
//@{
#define BP_IOMUXC_GPR3_CORE3_DBG_ACK_EN      (16)      //!< Bit position for IOMUXC_GPR3_CORE3_DBG_ACK_EN.
#define BM_IOMUXC_GPR3_CORE3_DBG_ACK_EN      (0x00010000)  //!< Bit mask for IOMUXC_GPR3_CORE3_DBG_ACK_EN.

//! @brief Get value of IOMUXC_GPR3_CORE3_DBG_ACK_EN from a register value.
#define BG_IOMUXC_GPR3_CORE3_DBG_ACK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_CORE3_DBG_ACK_EN) >> BP_IOMUXC_GPR3_CORE3_DBG_ACK_EN)

//! @brief Format value for bitfield IOMUXC_GPR3_CORE3_DBG_ACK_EN.
#define BF_IOMUXC_GPR3_CORE3_DBG_ACK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_CORE3_DBG_ACK_EN) & BM_IOMUXC_GPR3_CORE3_DBG_ACK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CORE3_DBG_ACK_EN field to a new value.
#define BW_IOMUXC_GPR3_CORE3_DBG_ACK_EN(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_CORE3_DBG_ACK_EN) | BF_IOMUXC_GPR3_CORE3_DBG_ACK_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field OCRAM_STATUS[20:17] (RO)
 *
 * This field shows the OCRAM pipeline settings status, controlled by OCRAM_CTL[24:21] bits
 * respectively. When the control bit is changed, the corresponding status bit goes high and keeps
 * high until this new configuration is applied the internal logic. This provides a way for software
 * to detect that the configuration has become valid. The suggested flow for changing the
 * configuration in software is: set/clear the control bit poll the status bit until it goes to 0
 * OCRAM_STATUS[17] shows the write address pipeline status. This bit value reflects the propagation
 * of the respective control bit to OCRAM memory. OCRAM_STATUS[18] shows the write data pipeline
 * status. This bit value reflects the propagation of the respective control bit to OCRAM memory.
 * OCRAM_STATUS[19] shows the read address pipeline status. This bit value reflects the propagation
 * of the respective control bit to OCRAM memory. OCRAM_STATUS[20] shows the read data pipeline
 * status. This bit value reflects the propagation of the respective control bit to OCRAM memory.
 *
 * Values:
 * - 0 - read data pipeline configuration valid
 * - 1 - read data pipeline control bit changed
 */
//@{
#define BP_IOMUXC_GPR3_OCRAM_STATUS      (17)      //!< Bit position for IOMUXC_GPR3_OCRAM_STATUS.
#define BM_IOMUXC_GPR3_OCRAM_STATUS      (0x001e0000)  //!< Bit mask for IOMUXC_GPR3_OCRAM_STATUS.

//! @brief Get value of IOMUXC_GPR3_OCRAM_STATUS from a register value.
#define BG_IOMUXC_GPR3_OCRAM_STATUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_OCRAM_STATUS) >> BP_IOMUXC_GPR3_OCRAM_STATUS)
//@}

/*! @name Register IOMUXC_GPR3, field OCRAM_CTL[24:21] (RW)
 *
 * OCRAM_CTL[24] write address pipeline control bit. When this feature is enabled, the write address
 * from the AXI master would be delayed 1 cycle before it can be accepted by the on-chip RAM. This
 * can avoid any setup time issue for the write access on the memory cell at high frequency.
 * Enabling this feature would cost at most 1 more clock cycle for each AXI write transaction, i.e.,
 * at most 1 more clock cycle for each write burst with multiple beats of data. When this feature is
 * disabled, the write address from the AXI master can be accepted by the on-chip RAM without delay,
 * and data can be written to memory at this cycle (if no other access and write data is also ready
 * at this cycle). 0 write address pipeline is disabled 1 write address pipeline is enabled
 * OCRAM_CTL[23] - write data pipeline control bit When this feature is enabled, the write data from
 * the AXI master would be delayed 1 cycle before it can be accepted by the on-chip RAM. This can
 * avoid any setup time issue for the write access on the memory cell at high frequency. Enabling
 * this feature would cost at most 1 more clock cycle for each AXI write transaction, i.e., at most
 * 1 more clock cycle for each write burst with multiple beats of data. When this feature is
 * disabled, the write data from the AXI master can be accepted by the on-chip RAM without delay,
 * and data can be written to memory at this cycle (if no other access and write address is also
 * ready at this cycle). 0 write data pipeline is disabled 1 write data pipeline is enabled
 * OCRAM_CTL[22] read address pipeline control bit. When this feature is enabled, the read address
 * from the AXI master would be delayed 1 cycle before it can be accepted by the on-chip RAM. This
 * can avoid any setup time issue for the read access on the memory cell at high frequency. Enabling
 * this feature would cost at most 1 more clock cycle for each AXI read transaction, i.e., at most 1
 * more clock cycle for each read burst with multiple beats of data. When this feature is disabled,
 * the read address from the AXI master can be accepted by the on-chip RAM without delay, and data
 * can become ready for master at next clock cycle (if no other access and no read data wait). 0
 * read address pipeline is disabled 1 read address pipeline is enabled OCRAM_CTL[21] - read data
 * wait state control bit When the read data wait state is enabled, it will cost 2 cycles for each
 * read access, (each beat of a read burst). This can avoid the potential timing problem caused by
 * the relatively longer memory access time at higher frequency. When this feature is disabled, it
 * only costs 1 clock cycle to finish a read transaction, i.e., get read data back in the next cycle
 * of read request becomes valid on the bus.
 *
 * Values:
 * - 0 - read data pipeline is disabled
 * - 1 - read data pipeline is enabled
 */
//@{
#define BP_IOMUXC_GPR3_OCRAM_CTL      (21)      //!< Bit position for IOMUXC_GPR3_OCRAM_CTL.
#define BM_IOMUXC_GPR3_OCRAM_CTL      (0x01e00000)  //!< Bit mask for IOMUXC_GPR3_OCRAM_CTL.

//! @brief Get value of IOMUXC_GPR3_OCRAM_CTL from a register value.
#define BG_IOMUXC_GPR3_OCRAM_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_OCRAM_CTL) >> BP_IOMUXC_GPR3_OCRAM_CTL)

//! @brief Format value for bitfield IOMUXC_GPR3_OCRAM_CTL.
#define BF_IOMUXC_GPR3_OCRAM_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_OCRAM_CTL) & BM_IOMUXC_GPR3_OCRAM_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the OCRAM_CTL field to a new value.
#define BW_IOMUXC_GPR3_OCRAM_CTL(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_OCRAM_CTL) | BF_IOMUXC_GPR3_OCRAM_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field USDHCX_RD_CACHE_CTL[25] (RW)
 *
 * Control uSDHCx [1-4] blocks cacheable attribute of AXI read transactions
 *
 * Values:
 * - 0 - Cacheable attribute is off for read transactions.
 * - 1 - Cacheable attribute is on for read transactions.
 */
//@{
#define BP_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL      (25)      //!< Bit position for IOMUXC_GPR3_USDHCX_RD_CACHE_CTL.
#define BM_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL      (0x02000000)  //!< Bit mask for IOMUXC_GPR3_USDHCX_RD_CACHE_CTL.

//! @brief Get value of IOMUXC_GPR3_USDHCX_RD_CACHE_CTL from a register value.
#define BG_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL) >> BP_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL)

//! @brief Format value for bitfield IOMUXC_GPR3_USDHCX_RD_CACHE_CTL.
#define BF_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL) & BM_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the USDHCX_RD_CACHE_CTL field to a new value.
#define BW_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL) | BF_IOMUXC_GPR3_USDHCX_RD_CACHE_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field USDHCX_WR_CACHE_CTL[26] (RW)
 *
 * Control uSDHCx [1-4] blocks cacheable attribute of AXI write transactions
 *
 * Values:
 * - 0 - Cacheable attribute is off for write transactions.
 * - 1 - Cacheable attribute is on for write transactions.
 */
//@{
#define BP_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL      (26)      //!< Bit position for IOMUXC_GPR3_USDHCX_WR_CACHE_CTL.
#define BM_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL      (0x04000000)  //!< Bit mask for IOMUXC_GPR3_USDHCX_WR_CACHE_CTL.

//! @brief Get value of IOMUXC_GPR3_USDHCX_WR_CACHE_CTL from a register value.
#define BG_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL) >> BP_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL)

//! @brief Format value for bitfield IOMUXC_GPR3_USDHCX_WR_CACHE_CTL.
#define BF_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL) & BM_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the USDHCX_WR_CACHE_CTL field to a new value.
#define BW_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL) | BF_IOMUXC_GPR3_USDHCX_WR_CACHE_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field BCH_RD_CACHE_CTL[27] (RW)
 *
 * Control BCH block cacheable attribute of AXI read transactions Set of the cache bits, enable
 * packet optimization through the bus system to DDR controller. The only side effect is that bus
 * may change the nature of the accesses, which may lead to problems when accessing FIFO type
 * address. In most typical cases, these bits should be set. For the GPU3D, GPU2D and OpenVG, such
 * settings are possible through the IP programming model. For few peripherals, for these bits to
 * take effect, it is required to also select set '1' to 'cache-mux' control bit.
 *
 * Values:
 * - 0 - Cacheable attribute is off for read transactions.
 * - 1 - Cacheable attribute is on for read transactions.
 */
//@{
#define BP_IOMUXC_GPR3_BCH_RD_CACHE_CTL      (27)      //!< Bit position for IOMUXC_GPR3_BCH_RD_CACHE_CTL.
#define BM_IOMUXC_GPR3_BCH_RD_CACHE_CTL      (0x08000000)  //!< Bit mask for IOMUXC_GPR3_BCH_RD_CACHE_CTL.

//! @brief Get value of IOMUXC_GPR3_BCH_RD_CACHE_CTL from a register value.
#define BG_IOMUXC_GPR3_BCH_RD_CACHE_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_BCH_RD_CACHE_CTL) >> BP_IOMUXC_GPR3_BCH_RD_CACHE_CTL)

//! @brief Format value for bitfield IOMUXC_GPR3_BCH_RD_CACHE_CTL.
#define BF_IOMUXC_GPR3_BCH_RD_CACHE_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_BCH_RD_CACHE_CTL) & BM_IOMUXC_GPR3_BCH_RD_CACHE_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the BCH_RD_CACHE_CTL field to a new value.
#define BW_IOMUXC_GPR3_BCH_RD_CACHE_CTL(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_BCH_RD_CACHE_CTL) | BF_IOMUXC_GPR3_BCH_RD_CACHE_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field BCH_WR_CACHE_CTL[28] (RW)
 *
 * Control BCH block cacheable attribute of AXI write transactions
 *
 * Values:
 * - 0 - Cacheable attribute is off for write transactions.
 * - 1 - Cacheable attribute is on for write transactions.
 */
//@{
#define BP_IOMUXC_GPR3_BCH_WR_CACHE_CTL      (28)      //!< Bit position for IOMUXC_GPR3_BCH_WR_CACHE_CTL.
#define BM_IOMUXC_GPR3_BCH_WR_CACHE_CTL      (0x10000000)  //!< Bit mask for IOMUXC_GPR3_BCH_WR_CACHE_CTL.

//! @brief Get value of IOMUXC_GPR3_BCH_WR_CACHE_CTL from a register value.
#define BG_IOMUXC_GPR3_BCH_WR_CACHE_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_BCH_WR_CACHE_CTL) >> BP_IOMUXC_GPR3_BCH_WR_CACHE_CTL)

//! @brief Format value for bitfield IOMUXC_GPR3_BCH_WR_CACHE_CTL.
#define BF_IOMUXC_GPR3_BCH_WR_CACHE_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_BCH_WR_CACHE_CTL) & BM_IOMUXC_GPR3_BCH_WR_CACHE_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the BCH_WR_CACHE_CTL field to a new value.
#define BW_IOMUXC_GPR3_BCH_WR_CACHE_CTL(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_BCH_WR_CACHE_CTL) | BF_IOMUXC_GPR3_BCH_WR_CACHE_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR3, field GPU_DBG[30:29] (RW)
 *
 * GPU debug busses to IOMUX
 *
 * Values:
 * - 00 - GPU3D
 * - 01 - GPU2D
 * - 10 - OpenVG
 * - 11 - Reserved
 */
//@{
#define BP_IOMUXC_GPR3_GPU_DBG      (29)      //!< Bit position for IOMUXC_GPR3_GPU_DBG.
#define BM_IOMUXC_GPR3_GPU_DBG      (0x60000000)  //!< Bit mask for IOMUXC_GPR3_GPU_DBG.

//! @brief Get value of IOMUXC_GPR3_GPU_DBG from a register value.
#define BG_IOMUXC_GPR3_GPU_DBG(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR3_GPU_DBG) >> BP_IOMUXC_GPR3_GPU_DBG)

//! @brief Format value for bitfield IOMUXC_GPR3_GPU_DBG.
#define BF_IOMUXC_GPR3_GPU_DBG(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR3_GPU_DBG) & BM_IOMUXC_GPR3_GPU_DBG)

#ifndef __LANGUAGE_ASM__
//! @brief Set the GPU_DBG field to a new value.
#define BW_IOMUXC_GPR3_GPU_DBG(v)   (HW_IOMUXC_GPR3_WR((HW_IOMUXC_GPR3_RD() & ~BM_IOMUXC_GPR3_GPU_DBG) | BF_IOMUXC_GPR3_GPU_DBG(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR4 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR4 - GPR (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_gpr4
{
    reg32_t U;
    struct _hw_iomuxc_gpr4_bitfields
    {
        unsigned IPU_RD_CACHE_CTL : 1; //!< [0] Control IPU-1 and IPU-2 block cacheable attribute of AXI read transactions Set of the cache bits, enable packet optimization through the bus system to DDR controller.
        unsigned IPU_WR_CACHE_CTL : 1; //!< [1] Control IPU-1 and IPU-2 block cacheable attribute of AXI write transactions
        unsigned VPU_P_RD_CACHE_VAL : 1; //!< [2] VPU (primary bus) block cacheable attribute value of AXI read transactions
        unsigned VPU_P_WR_CACHE_VAL : 1; //!< [3] VPU (primary bus) block cacheable attribute value of AXI write transactions
        unsigned RESERVED0 : 2; //!< [5:4] Reserved.
        unsigned VPU_RD_CACHE_SEL : 1; //!< [6] This bit selects the cacheable attribute of VPU AXI read transcations (both primary and secondary AXI buses)
        unsigned VPU_WR_CACHE_SEL : 1; //!< [7] This bit selects the cacheable attribute of VPU AXI write transcations (both primary and secondary AXI buses)
        unsigned SOC_VERSION : 8; //!< [15:8] This is status (read only) field.
        unsigned ENET_STOP_ACK : 1; //!< [16] ENET stop acknowledge.
        unsigned CAN1_STOP_ACK : 1; //!< [17] CAN-1 stop acknowledge.
        unsigned CAN2_STOP_ACK : 1; //!< [18] CAN-2 stop acknowledge.
        unsigned SDMA_STOP_ACK : 1; //!< [19] SDMA stop acknowledge.
        unsigned RESERVED1 : 4; //!< [23:20] Reserved
        unsigned PCIE_RD_CACHE_VAL : 1; //!< [24] PCIe block cacheable attribute value of AXI read transactions
        unsigned PCIE_WR_CACHE_VAL : 1; //!< [25] PCIe block cacheable attribute value of AXI write transactions
        unsigned PCIE_RD_CACHE_SEL : 1; //!< [26] This bit selects the cacheable attribute of PCIe AXI read transcations)
        unsigned PCIE_WR_CACHE_SEL : 1; //!< [27] This bit selects the cacheable attribute of PCIe AXI write transcations
        unsigned VDOA_RD_CACHE_VAL : 1; //!< [28] VDOA block cacheable attribute value of AXI read transactions
        unsigned VDOA_WR_CACHE_VAL : 1; //!< [29] VDOA block cacheable attribute value of AXI write transactions
        unsigned VDOA_RD_CACHE_SEL : 1; //!< [30] This bit selects the cacheable attribute of VDOA AXI read transcations)
        unsigned VDOA_WR_CACHE_SEL : 1; //!< [31] This bit selects the cacheable attribute of VDOA AXI write transcations
    } B;
} hw_iomuxc_gpr4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR4 register
 */
//@{
#define HW_IOMUXC_GPR4_ADDR      (REGS_IOMUXC_BASE + 0x10)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR4           (*(volatile hw_iomuxc_gpr4_t *) HW_IOMUXC_GPR4_ADDR)
#define HW_IOMUXC_GPR4_RD()      (HW_IOMUXC_GPR4.U)
#define HW_IOMUXC_GPR4_WR(v)     (HW_IOMUXC_GPR4.U = (v))
#define HW_IOMUXC_GPR4_SET(v)    (HW_IOMUXC_GPR4_WR(HW_IOMUXC_GPR4_RD() |  (v)))
#define HW_IOMUXC_GPR4_CLR(v)    (HW_IOMUXC_GPR4_WR(HW_IOMUXC_GPR4_RD() & ~(v)))
#define HW_IOMUXC_GPR4_TOG(v)    (HW_IOMUXC_GPR4_WR(HW_IOMUXC_GPR4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR4 bitfields
 */

/*! @name Register IOMUXC_GPR4, field IPU_RD_CACHE_CTL[0] (RW)
 *
 * Control IPU-1 and IPU-2 block cacheable attribute of AXI read transactions Set of the cache bits,
 * enable packet optimization through the bus system to DDR controller. The only side effect is that
 * bus may change the nature of the accesses, which may lead to problems when accessing FIFO type
 * address. In most typical cases, these bits should be set. For the GPU3D, GPU2D and OpenVG, such
 * settings are possible through the IP programming model. For few peripherals, for these bits to
 * take effect, it is required to also select set '1' to 'cache-mux' control bit.
 *
 * Values:
 * - 0 - Cacheable attribute is off for read transactions.
 * - 1 - Cacheable attribute is on for read transactions.
 */
//@{
#define BP_IOMUXC_GPR4_IPU_RD_CACHE_CTL      (0)      //!< Bit position for IOMUXC_GPR4_IPU_RD_CACHE_CTL.
#define BM_IOMUXC_GPR4_IPU_RD_CACHE_CTL      (0x00000001)  //!< Bit mask for IOMUXC_GPR4_IPU_RD_CACHE_CTL.

//! @brief Get value of IOMUXC_GPR4_IPU_RD_CACHE_CTL from a register value.
#define BG_IOMUXC_GPR4_IPU_RD_CACHE_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_IPU_RD_CACHE_CTL) >> BP_IOMUXC_GPR4_IPU_RD_CACHE_CTL)

//! @brief Format value for bitfield IOMUXC_GPR4_IPU_RD_CACHE_CTL.
#define BF_IOMUXC_GPR4_IPU_RD_CACHE_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_IPU_RD_CACHE_CTL) & BM_IOMUXC_GPR4_IPU_RD_CACHE_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU_RD_CACHE_CTL field to a new value.
#define BW_IOMUXC_GPR4_IPU_RD_CACHE_CTL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_IPU_RD_CACHE_CTL) | BF_IOMUXC_GPR4_IPU_RD_CACHE_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field IPU_WR_CACHE_CTL[1] (RW)
 *
 * Control IPU-1 and IPU-2 block cacheable attribute of AXI write transactions
 *
 * Values:
 * - 0 - Cacheable attribute is off for write transactions.
 * - 1 - Cacheable attribute is on for write transactions.
 */
//@{
#define BP_IOMUXC_GPR4_IPU_WR_CACHE_CTL      (1)      //!< Bit position for IOMUXC_GPR4_IPU_WR_CACHE_CTL.
#define BM_IOMUXC_GPR4_IPU_WR_CACHE_CTL      (0x00000002)  //!< Bit mask for IOMUXC_GPR4_IPU_WR_CACHE_CTL.

//! @brief Get value of IOMUXC_GPR4_IPU_WR_CACHE_CTL from a register value.
#define BG_IOMUXC_GPR4_IPU_WR_CACHE_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_IPU_WR_CACHE_CTL) >> BP_IOMUXC_GPR4_IPU_WR_CACHE_CTL)

//! @brief Format value for bitfield IOMUXC_GPR4_IPU_WR_CACHE_CTL.
#define BF_IOMUXC_GPR4_IPU_WR_CACHE_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_IPU_WR_CACHE_CTL) & BM_IOMUXC_GPR4_IPU_WR_CACHE_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU_WR_CACHE_CTL field to a new value.
#define BW_IOMUXC_GPR4_IPU_WR_CACHE_CTL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_IPU_WR_CACHE_CTL) | BF_IOMUXC_GPR4_IPU_WR_CACHE_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field VPU_P_RD_CACHE_VAL[2] (RW)
 *
 * VPU (primary bus) block cacheable attribute value of AXI read transactions The value of
 * VPU_P_RD_CACHE_VAL is affecting the transactions only if VPU_RD_CACHE_SEL is set.
 *
 * Values:
 * - 0 - Cacheable attribute is off for read transactions.
 * - 1 - Cacheable attribute is on for read transactions.
 */
//@{
#define BP_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL      (2)      //!< Bit position for IOMUXC_GPR4_VPU_P_RD_CACHE_VAL.
#define BM_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL      (0x00000004)  //!< Bit mask for IOMUXC_GPR4_VPU_P_RD_CACHE_VAL.

//! @brief Get value of IOMUXC_GPR4_VPU_P_RD_CACHE_VAL from a register value.
#define BG_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL) >> BP_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL)

//! @brief Format value for bitfield IOMUXC_GPR4_VPU_P_RD_CACHE_VAL.
#define BF_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL) & BM_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the VPU_P_RD_CACHE_VAL field to a new value.
#define BW_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL) | BF_IOMUXC_GPR4_VPU_P_RD_CACHE_VAL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field VPU_P_WR_CACHE_VAL[3] (RW)
 *
 * VPU (primary bus) block cacheable attribute value of AXI write transactions The value of
 * VPU_P_WR_CACHE_VAL is affecting the transactions only if VPU_WR_CACHE_SEL is set.
 *
 * Values:
 * - 0 - Cacheable attribute is off for write transactions.
 * - 1 - Cacheable attribute is on for write transactions.
 */
//@{
#define BP_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL      (3)      //!< Bit position for IOMUXC_GPR4_VPU_P_WR_CACHE_VAL.
#define BM_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL      (0x00000008)  //!< Bit mask for IOMUXC_GPR4_VPU_P_WR_CACHE_VAL.

//! @brief Get value of IOMUXC_GPR4_VPU_P_WR_CACHE_VAL from a register value.
#define BG_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL) >> BP_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL)

//! @brief Format value for bitfield IOMUXC_GPR4_VPU_P_WR_CACHE_VAL.
#define BF_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL) & BM_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the VPU_P_WR_CACHE_VAL field to a new value.
#define BW_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL) | BF_IOMUXC_GPR4_VPU_P_WR_CACHE_VAL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field VPU_RD_CACHE_SEL[6] (RW)
 *
 * This bit selects the cacheable attribute of VPU AXI read transcations (both primary and secondary
 * AXI buses)
 *
 * Values:
 * - 0 - The read transaction cacheable attribute is driven by the VPU core
 * - 1 - The read transaction cacheable attribute is driven by VPU_SEC_RD_CACHE_VAL for secondary bus and
 *     VPU_P_RD_CACHE_VAL for primary bus.
 */
//@{
#define BP_IOMUXC_GPR4_VPU_RD_CACHE_SEL      (6)      //!< Bit position for IOMUXC_GPR4_VPU_RD_CACHE_SEL.
#define BM_IOMUXC_GPR4_VPU_RD_CACHE_SEL      (0x00000040)  //!< Bit mask for IOMUXC_GPR4_VPU_RD_CACHE_SEL.

//! @brief Get value of IOMUXC_GPR4_VPU_RD_CACHE_SEL from a register value.
#define BG_IOMUXC_GPR4_VPU_RD_CACHE_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_VPU_RD_CACHE_SEL) >> BP_IOMUXC_GPR4_VPU_RD_CACHE_SEL)

//! @brief Format value for bitfield IOMUXC_GPR4_VPU_RD_CACHE_SEL.
#define BF_IOMUXC_GPR4_VPU_RD_CACHE_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_VPU_RD_CACHE_SEL) & BM_IOMUXC_GPR4_VPU_RD_CACHE_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the VPU_RD_CACHE_SEL field to a new value.
#define BW_IOMUXC_GPR4_VPU_RD_CACHE_SEL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_VPU_RD_CACHE_SEL) | BF_IOMUXC_GPR4_VPU_RD_CACHE_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field VPU_WR_CACHE_SEL[7] (RW)
 *
 * This bit selects the cacheable attribute of VPU AXI write transcations (both primary and
 * secondary AXI buses)
 *
 * Values:
 * - 0 - The write transactions cacheable attribute is driven by the VPU core
 * - 1 - The write transactions cacheable attribute is driven by VPU_SEC_WR_CACHE_VAL for secondary bus and
 *     VPU_P_WR_CACHE_VAL for primary bus.
 */
//@{
#define BP_IOMUXC_GPR4_VPU_WR_CACHE_SEL      (7)      //!< Bit position for IOMUXC_GPR4_VPU_WR_CACHE_SEL.
#define BM_IOMUXC_GPR4_VPU_WR_CACHE_SEL      (0x00000080)  //!< Bit mask for IOMUXC_GPR4_VPU_WR_CACHE_SEL.

//! @brief Get value of IOMUXC_GPR4_VPU_WR_CACHE_SEL from a register value.
#define BG_IOMUXC_GPR4_VPU_WR_CACHE_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_VPU_WR_CACHE_SEL) >> BP_IOMUXC_GPR4_VPU_WR_CACHE_SEL)

//! @brief Format value for bitfield IOMUXC_GPR4_VPU_WR_CACHE_SEL.
#define BF_IOMUXC_GPR4_VPU_WR_CACHE_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_VPU_WR_CACHE_SEL) & BM_IOMUXC_GPR4_VPU_WR_CACHE_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the VPU_WR_CACHE_SEL field to a new value.
#define BW_IOMUXC_GPR4_VPU_WR_CACHE_SEL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_VPU_WR_CACHE_SEL) | BF_IOMUXC_GPR4_VPU_WR_CACHE_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field SOC_VERSION[15:8] (RW)
 *
 * This is status (read only) field.
 */
//@{
#define BP_IOMUXC_GPR4_SOC_VERSION      (8)      //!< Bit position for IOMUXC_GPR4_SOC_VERSION.
#define BM_IOMUXC_GPR4_SOC_VERSION      (0x0000ff00)  //!< Bit mask for IOMUXC_GPR4_SOC_VERSION.

//! @brief Get value of IOMUXC_GPR4_SOC_VERSION from a register value.
#define BG_IOMUXC_GPR4_SOC_VERSION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_SOC_VERSION) >> BP_IOMUXC_GPR4_SOC_VERSION)

//! @brief Format value for bitfield IOMUXC_GPR4_SOC_VERSION.
#define BF_IOMUXC_GPR4_SOC_VERSION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_SOC_VERSION) & BM_IOMUXC_GPR4_SOC_VERSION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SOC_VERSION field to a new value.
#define BW_IOMUXC_GPR4_SOC_VERSION(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_SOC_VERSION) | BF_IOMUXC_GPR4_SOC_VERSION(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field ENET_STOP_ACK[16] (RW)
 *
 * ENET stop acknowledge. This is status (read only) bit.
 *
 * Values:
 * - 0 - ENET stop acknowledge is not asserted.
 * - 1 - ENET stop acknowledge is asserted, ENET is in STOP mode.
 */
//@{
#define BP_IOMUXC_GPR4_ENET_STOP_ACK      (16)      //!< Bit position for IOMUXC_GPR4_ENET_STOP_ACK.
#define BM_IOMUXC_GPR4_ENET_STOP_ACK      (0x00010000)  //!< Bit mask for IOMUXC_GPR4_ENET_STOP_ACK.

//! @brief Get value of IOMUXC_GPR4_ENET_STOP_ACK from a register value.
#define BG_IOMUXC_GPR4_ENET_STOP_ACK(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_ENET_STOP_ACK) >> BP_IOMUXC_GPR4_ENET_STOP_ACK)

//! @brief Format value for bitfield IOMUXC_GPR4_ENET_STOP_ACK.
#define BF_IOMUXC_GPR4_ENET_STOP_ACK(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_ENET_STOP_ACK) & BM_IOMUXC_GPR4_ENET_STOP_ACK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ENET_STOP_ACK field to a new value.
#define BW_IOMUXC_GPR4_ENET_STOP_ACK(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_ENET_STOP_ACK) | BF_IOMUXC_GPR4_ENET_STOP_ACK(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field CAN1_STOP_ACK[17] (RW)
 *
 * CAN-1 stop acknowledge. This is status (read only) bit.
 *
 * Values:
 * - 0 - CAN-1 stop acknowledge is not asserted.
 * - 1 - CAN-1 stop acknowledge is asserted, CAN-1 is in STOP mode.
 */
//@{
#define BP_IOMUXC_GPR4_CAN1_STOP_ACK      (17)      //!< Bit position for IOMUXC_GPR4_CAN1_STOP_ACK.
#define BM_IOMUXC_GPR4_CAN1_STOP_ACK      (0x00020000)  //!< Bit mask for IOMUXC_GPR4_CAN1_STOP_ACK.

//! @brief Get value of IOMUXC_GPR4_CAN1_STOP_ACK from a register value.
#define BG_IOMUXC_GPR4_CAN1_STOP_ACK(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_CAN1_STOP_ACK) >> BP_IOMUXC_GPR4_CAN1_STOP_ACK)

//! @brief Format value for bitfield IOMUXC_GPR4_CAN1_STOP_ACK.
#define BF_IOMUXC_GPR4_CAN1_STOP_ACK(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_CAN1_STOP_ACK) & BM_IOMUXC_GPR4_CAN1_STOP_ACK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CAN1_STOP_ACK field to a new value.
#define BW_IOMUXC_GPR4_CAN1_STOP_ACK(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_CAN1_STOP_ACK) | BF_IOMUXC_GPR4_CAN1_STOP_ACK(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field CAN2_STOP_ACK[18] (RW)
 *
 * CAN-2 stop acknowledge. This is status (read only) bit.
 *
 * Values:
 * - 0 - CAN-2 stop acknowledge is not asserted.
 * - 1 - CAN-2 stop acknowledge is asserted, CAN-2 is in STOP mode.
 */
//@{
#define BP_IOMUXC_GPR4_CAN2_STOP_ACK      (18)      //!< Bit position for IOMUXC_GPR4_CAN2_STOP_ACK.
#define BM_IOMUXC_GPR4_CAN2_STOP_ACK      (0x00040000)  //!< Bit mask for IOMUXC_GPR4_CAN2_STOP_ACK.

//! @brief Get value of IOMUXC_GPR4_CAN2_STOP_ACK from a register value.
#define BG_IOMUXC_GPR4_CAN2_STOP_ACK(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_CAN2_STOP_ACK) >> BP_IOMUXC_GPR4_CAN2_STOP_ACK)

//! @brief Format value for bitfield IOMUXC_GPR4_CAN2_STOP_ACK.
#define BF_IOMUXC_GPR4_CAN2_STOP_ACK(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_CAN2_STOP_ACK) & BM_IOMUXC_GPR4_CAN2_STOP_ACK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CAN2_STOP_ACK field to a new value.
#define BW_IOMUXC_GPR4_CAN2_STOP_ACK(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_CAN2_STOP_ACK) | BF_IOMUXC_GPR4_CAN2_STOP_ACK(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field SDMA_STOP_ACK[19] (RW)
 *
 * SDMA stop acknowledge. This is status (read only) bit.
 *
 * Values:
 * - 0 - SDMA stop acknowledge is not asserted.
 * - 1 - SDMA stop acknowledge is asserted, SDMA is in STOP mode.
 */
//@{
#define BP_IOMUXC_GPR4_SDMA_STOP_ACK      (19)      //!< Bit position for IOMUXC_GPR4_SDMA_STOP_ACK.
#define BM_IOMUXC_GPR4_SDMA_STOP_ACK      (0x00080000)  //!< Bit mask for IOMUXC_GPR4_SDMA_STOP_ACK.

//! @brief Get value of IOMUXC_GPR4_SDMA_STOP_ACK from a register value.
#define BG_IOMUXC_GPR4_SDMA_STOP_ACK(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_SDMA_STOP_ACK) >> BP_IOMUXC_GPR4_SDMA_STOP_ACK)

//! @brief Format value for bitfield IOMUXC_GPR4_SDMA_STOP_ACK.
#define BF_IOMUXC_GPR4_SDMA_STOP_ACK(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_SDMA_STOP_ACK) & BM_IOMUXC_GPR4_SDMA_STOP_ACK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SDMA_STOP_ACK field to a new value.
#define BW_IOMUXC_GPR4_SDMA_STOP_ACK(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_SDMA_STOP_ACK) | BF_IOMUXC_GPR4_SDMA_STOP_ACK(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field PCIE_RD_CACHE_VAL[24] (RW)
 *
 * PCIe block cacheable attribute value of AXI read transactions The value of PCIe_RD_CACHE_VAL is
 * affecting the transactions only if PCIe_RD_CACHE_SEL is set.
 *
 * Values:
 * - 0 - Cacheable attribute is off for read transactions.
 * - 1 - Cacheable attribute is on for read transactions.
 */
//@{
#define BP_IOMUXC_GPR4_PCIE_RD_CACHE_VAL      (24)      //!< Bit position for IOMUXC_GPR4_PCIE_RD_CACHE_VAL.
#define BM_IOMUXC_GPR4_PCIE_RD_CACHE_VAL      (0x01000000)  //!< Bit mask for IOMUXC_GPR4_PCIE_RD_CACHE_VAL.

//! @brief Get value of IOMUXC_GPR4_PCIE_RD_CACHE_VAL from a register value.
#define BG_IOMUXC_GPR4_PCIE_RD_CACHE_VAL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_PCIE_RD_CACHE_VAL) >> BP_IOMUXC_GPR4_PCIE_RD_CACHE_VAL)

//! @brief Format value for bitfield IOMUXC_GPR4_PCIE_RD_CACHE_VAL.
#define BF_IOMUXC_GPR4_PCIE_RD_CACHE_VAL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_PCIE_RD_CACHE_VAL) & BM_IOMUXC_GPR4_PCIE_RD_CACHE_VAL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCIE_RD_CACHE_VAL field to a new value.
#define BW_IOMUXC_GPR4_PCIE_RD_CACHE_VAL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_PCIE_RD_CACHE_VAL) | BF_IOMUXC_GPR4_PCIE_RD_CACHE_VAL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field PCIE_WR_CACHE_VAL[25] (RW)
 *
 * PCIe block cacheable attribute value of AXI write transactions The value of PCIe_WR_CACHE_VAL is
 * affecting the transactions only if PCIe_WR_CACHE_SEL is set.
 *
 * Values:
 * - 0 - Cacheable attribute is off for write transactions.
 * - 1 - Cacheable attribute is on for write transactions.
 */
//@{
#define BP_IOMUXC_GPR4_PCIE_WR_CACHE_VAL      (25)      //!< Bit position for IOMUXC_GPR4_PCIE_WR_CACHE_VAL.
#define BM_IOMUXC_GPR4_PCIE_WR_CACHE_VAL      (0x02000000)  //!< Bit mask for IOMUXC_GPR4_PCIE_WR_CACHE_VAL.

//! @brief Get value of IOMUXC_GPR4_PCIE_WR_CACHE_VAL from a register value.
#define BG_IOMUXC_GPR4_PCIE_WR_CACHE_VAL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_PCIE_WR_CACHE_VAL) >> BP_IOMUXC_GPR4_PCIE_WR_CACHE_VAL)

//! @brief Format value for bitfield IOMUXC_GPR4_PCIE_WR_CACHE_VAL.
#define BF_IOMUXC_GPR4_PCIE_WR_CACHE_VAL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_PCIE_WR_CACHE_VAL) & BM_IOMUXC_GPR4_PCIE_WR_CACHE_VAL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCIE_WR_CACHE_VAL field to a new value.
#define BW_IOMUXC_GPR4_PCIE_WR_CACHE_VAL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_PCIE_WR_CACHE_VAL) | BF_IOMUXC_GPR4_PCIE_WR_CACHE_VAL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field PCIE_RD_CACHE_SEL[26] (RW)
 *
 * This bit selects the cacheable attribute of PCIe AXI read transcations)
 *
 * Values:
 * - 0 - The read transaction cacheable attribute is driven by the PCIe core
 * - 1 - The read transaction cacheable attribute is driven by PCIe_RD_CACHE_VAL.
 */
//@{
#define BP_IOMUXC_GPR4_PCIE_RD_CACHE_SEL      (26)      //!< Bit position for IOMUXC_GPR4_PCIE_RD_CACHE_SEL.
#define BM_IOMUXC_GPR4_PCIE_RD_CACHE_SEL      (0x04000000)  //!< Bit mask for IOMUXC_GPR4_PCIE_RD_CACHE_SEL.

//! @brief Get value of IOMUXC_GPR4_PCIE_RD_CACHE_SEL from a register value.
#define BG_IOMUXC_GPR4_PCIE_RD_CACHE_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_PCIE_RD_CACHE_SEL) >> BP_IOMUXC_GPR4_PCIE_RD_CACHE_SEL)

//! @brief Format value for bitfield IOMUXC_GPR4_PCIE_RD_CACHE_SEL.
#define BF_IOMUXC_GPR4_PCIE_RD_CACHE_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_PCIE_RD_CACHE_SEL) & BM_IOMUXC_GPR4_PCIE_RD_CACHE_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCIE_RD_CACHE_SEL field to a new value.
#define BW_IOMUXC_GPR4_PCIE_RD_CACHE_SEL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_PCIE_RD_CACHE_SEL) | BF_IOMUXC_GPR4_PCIE_RD_CACHE_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field PCIE_WR_CACHE_SEL[27] (RW)
 *
 * This bit selects the cacheable attribute of PCIe AXI write transcations
 *
 * Values:
 * - 0 - The write transactions cacheable attribute is driven by the PCIe core
 * - 1 - The write transactions cacheable attribute is driven by PCIe_WR_CACHE_VAL.
 */
//@{
#define BP_IOMUXC_GPR4_PCIE_WR_CACHE_SEL      (27)      //!< Bit position for IOMUXC_GPR4_PCIE_WR_CACHE_SEL.
#define BM_IOMUXC_GPR4_PCIE_WR_CACHE_SEL      (0x08000000)  //!< Bit mask for IOMUXC_GPR4_PCIE_WR_CACHE_SEL.

//! @brief Get value of IOMUXC_GPR4_PCIE_WR_CACHE_SEL from a register value.
#define BG_IOMUXC_GPR4_PCIE_WR_CACHE_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_PCIE_WR_CACHE_SEL) >> BP_IOMUXC_GPR4_PCIE_WR_CACHE_SEL)

//! @brief Format value for bitfield IOMUXC_GPR4_PCIE_WR_CACHE_SEL.
#define BF_IOMUXC_GPR4_PCIE_WR_CACHE_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_PCIE_WR_CACHE_SEL) & BM_IOMUXC_GPR4_PCIE_WR_CACHE_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCIE_WR_CACHE_SEL field to a new value.
#define BW_IOMUXC_GPR4_PCIE_WR_CACHE_SEL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_PCIE_WR_CACHE_SEL) | BF_IOMUXC_GPR4_PCIE_WR_CACHE_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field VDOA_RD_CACHE_VAL[28] (RW)
 *
 * VDOA block cacheable attribute value of AXI read transactions The value of VDOA_RD_CACHE_VAL is
 * affecting the transactions only if VDOA_RD_CACHE_SEL is set.
 *
 * Values:
 * - 0 - Cacheable attribute is off for read transactions.
 * - 1 - Cacheable attribute is on for read transactions.
 */
//@{
#define BP_IOMUXC_GPR4_VDOA_RD_CACHE_VAL      (28)      //!< Bit position for IOMUXC_GPR4_VDOA_RD_CACHE_VAL.
#define BM_IOMUXC_GPR4_VDOA_RD_CACHE_VAL      (0x10000000)  //!< Bit mask for IOMUXC_GPR4_VDOA_RD_CACHE_VAL.

//! @brief Get value of IOMUXC_GPR4_VDOA_RD_CACHE_VAL from a register value.
#define BG_IOMUXC_GPR4_VDOA_RD_CACHE_VAL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_VDOA_RD_CACHE_VAL) >> BP_IOMUXC_GPR4_VDOA_RD_CACHE_VAL)

//! @brief Format value for bitfield IOMUXC_GPR4_VDOA_RD_CACHE_VAL.
#define BF_IOMUXC_GPR4_VDOA_RD_CACHE_VAL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_VDOA_RD_CACHE_VAL) & BM_IOMUXC_GPR4_VDOA_RD_CACHE_VAL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the VDOA_RD_CACHE_VAL field to a new value.
#define BW_IOMUXC_GPR4_VDOA_RD_CACHE_VAL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_VDOA_RD_CACHE_VAL) | BF_IOMUXC_GPR4_VDOA_RD_CACHE_VAL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field VDOA_WR_CACHE_VAL[29] (RW)
 *
 * VDOA block cacheable attribute value of AXI write transactions The value of VDOA_WR_CACHE_VAL is
 * affecting the transactions only if VDOA_WR_CACHE_SEL is set.
 *
 * Values:
 * - 0 - Cacheable attribute is off for write transactions.
 * - 1 - Cacheable attribute is on for write transactions.
 */
//@{
#define BP_IOMUXC_GPR4_VDOA_WR_CACHE_VAL      (29)      //!< Bit position for IOMUXC_GPR4_VDOA_WR_CACHE_VAL.
#define BM_IOMUXC_GPR4_VDOA_WR_CACHE_VAL      (0x20000000)  //!< Bit mask for IOMUXC_GPR4_VDOA_WR_CACHE_VAL.

//! @brief Get value of IOMUXC_GPR4_VDOA_WR_CACHE_VAL from a register value.
#define BG_IOMUXC_GPR4_VDOA_WR_CACHE_VAL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_VDOA_WR_CACHE_VAL) >> BP_IOMUXC_GPR4_VDOA_WR_CACHE_VAL)

//! @brief Format value for bitfield IOMUXC_GPR4_VDOA_WR_CACHE_VAL.
#define BF_IOMUXC_GPR4_VDOA_WR_CACHE_VAL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_VDOA_WR_CACHE_VAL) & BM_IOMUXC_GPR4_VDOA_WR_CACHE_VAL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the VDOA_WR_CACHE_VAL field to a new value.
#define BW_IOMUXC_GPR4_VDOA_WR_CACHE_VAL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_VDOA_WR_CACHE_VAL) | BF_IOMUXC_GPR4_VDOA_WR_CACHE_VAL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field VDOA_RD_CACHE_SEL[30] (RW)
 *
 * This bit selects the cacheable attribute of VDOA AXI read transcations)
 *
 * Values:
 * - 0 - The read transaction cacheable attribute is driven by the VDOA core
 * - 1 - The read transaction cacheable attribute is driven by VDOA_RD_CACHE_VAL.
 */
//@{
#define BP_IOMUXC_GPR4_VDOA_RD_CACHE_SEL      (30)      //!< Bit position for IOMUXC_GPR4_VDOA_RD_CACHE_SEL.
#define BM_IOMUXC_GPR4_VDOA_RD_CACHE_SEL      (0x40000000)  //!< Bit mask for IOMUXC_GPR4_VDOA_RD_CACHE_SEL.

//! @brief Get value of IOMUXC_GPR4_VDOA_RD_CACHE_SEL from a register value.
#define BG_IOMUXC_GPR4_VDOA_RD_CACHE_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_VDOA_RD_CACHE_SEL) >> BP_IOMUXC_GPR4_VDOA_RD_CACHE_SEL)

//! @brief Format value for bitfield IOMUXC_GPR4_VDOA_RD_CACHE_SEL.
#define BF_IOMUXC_GPR4_VDOA_RD_CACHE_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_VDOA_RD_CACHE_SEL) & BM_IOMUXC_GPR4_VDOA_RD_CACHE_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the VDOA_RD_CACHE_SEL field to a new value.
#define BW_IOMUXC_GPR4_VDOA_RD_CACHE_SEL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_VDOA_RD_CACHE_SEL) | BF_IOMUXC_GPR4_VDOA_RD_CACHE_SEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR4, field VDOA_WR_CACHE_SEL[31] (RW)
 *
 * This bit selects the cacheable attribute of VDOA AXI write transcations
 *
 * Values:
 * - 0 - The write transactions cacheable attribute is driven by the VDOA core
 * - 1 - The write transactions cacheable attribute is driven by VDOA_WR_CACHE_VAL.
 */
//@{
#define BP_IOMUXC_GPR4_VDOA_WR_CACHE_SEL      (31)      //!< Bit position for IOMUXC_GPR4_VDOA_WR_CACHE_SEL.
#define BM_IOMUXC_GPR4_VDOA_WR_CACHE_SEL      (0x80000000)  //!< Bit mask for IOMUXC_GPR4_VDOA_WR_CACHE_SEL.

//! @brief Get value of IOMUXC_GPR4_VDOA_WR_CACHE_SEL from a register value.
#define BG_IOMUXC_GPR4_VDOA_WR_CACHE_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR4_VDOA_WR_CACHE_SEL) >> BP_IOMUXC_GPR4_VDOA_WR_CACHE_SEL)

//! @brief Format value for bitfield IOMUXC_GPR4_VDOA_WR_CACHE_SEL.
#define BF_IOMUXC_GPR4_VDOA_WR_CACHE_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR4_VDOA_WR_CACHE_SEL) & BM_IOMUXC_GPR4_VDOA_WR_CACHE_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the VDOA_WR_CACHE_SEL field to a new value.
#define BW_IOMUXC_GPR4_VDOA_WR_CACHE_SEL(v)   (HW_IOMUXC_GPR4_WR((HW_IOMUXC_GPR4_RD() & ~BM_IOMUXC_GPR4_VDOA_WR_CACHE_SEL) | BF_IOMUXC_GPR4_VDOA_WR_CACHE_SEL(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR5 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR5 - GPR (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_gpr5
{
    reg32_t U;
    struct _hw_iomuxc_gpr5_bitfields
    {
        unsigned ARM_WFI : 4; //!< [3:0] ARM WFI event out indicating on WFI state of the cores (these are status, read only bits)
        unsigned ARM_WFE : 4; //!< [7:4] ARM WFE event out indication on WFE state of the cores (these are status, read only bits)
        unsigned L2_CLK_STOP : 1; //!< [8] L2 cache clock stop indication (this is a status, read only bit)
        unsigned RESERVED0 : 23; //!< [31:9] Reserved
    } B;
} hw_iomuxc_gpr5_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR5 register
 */
//@{
#define HW_IOMUXC_GPR5_ADDR      (REGS_IOMUXC_BASE + 0x14)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR5           (*(volatile hw_iomuxc_gpr5_t *) HW_IOMUXC_GPR5_ADDR)
#define HW_IOMUXC_GPR5_RD()      (HW_IOMUXC_GPR5.U)
#define HW_IOMUXC_GPR5_WR(v)     (HW_IOMUXC_GPR5.U = (v))
#define HW_IOMUXC_GPR5_SET(v)    (HW_IOMUXC_GPR5_WR(HW_IOMUXC_GPR5_RD() |  (v)))
#define HW_IOMUXC_GPR5_CLR(v)    (HW_IOMUXC_GPR5_WR(HW_IOMUXC_GPR5_RD() & ~(v)))
#define HW_IOMUXC_GPR5_TOG(v)    (HW_IOMUXC_GPR5_WR(HW_IOMUXC_GPR5_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR5 bitfields
 */

/*! @name Register IOMUXC_GPR5, field ARM_WFI[3:0] (RO)
 *
 * ARM WFI event out indicating on WFI state of the cores (these are status, read only bits)
 *
 * Values:
 * - 0 - ARM Core[GPR5-index] is not in “Wait for Interrupt” mode
 * - 1 - ARM Core[GPR5-index] is in “Wait for Interrupt” mode
 */
//@{
#define BP_IOMUXC_GPR5_ARM_WFI      (0)      //!< Bit position for IOMUXC_GPR5_ARM_WFI.
#define BM_IOMUXC_GPR5_ARM_WFI      (0x0000000f)  //!< Bit mask for IOMUXC_GPR5_ARM_WFI.

//! @brief Get value of IOMUXC_GPR5_ARM_WFI from a register value.
#define BG_IOMUXC_GPR5_ARM_WFI(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR5_ARM_WFI) >> BP_IOMUXC_GPR5_ARM_WFI)
//@}

/*! @name Register IOMUXC_GPR5, field ARM_WFE[7:4] (RO)
 *
 * ARM WFE event out indication on WFE state of the cores (these are status, read only bits)
 *
 * Values:
 * - 0 - ARM Core[GPR5-index - 4] is not in “Wait for Event” mode
 * - 1 - ARM Core[GPR5-index - 4] is in “Wait for Event” mode
 */
//@{
#define BP_IOMUXC_GPR5_ARM_WFE      (4)      //!< Bit position for IOMUXC_GPR5_ARM_WFE.
#define BM_IOMUXC_GPR5_ARM_WFE      (0x000000f0)  //!< Bit mask for IOMUXC_GPR5_ARM_WFE.

//! @brief Get value of IOMUXC_GPR5_ARM_WFE from a register value.
#define BG_IOMUXC_GPR5_ARM_WFE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR5_ARM_WFE) >> BP_IOMUXC_GPR5_ARM_WFE)
//@}

/*! @name Register IOMUXC_GPR5, field L2_CLK_STOP[8] (RO)
 *
 * L2 cache clock stop indication (this is a status, read only bit)
 *
 * Values:
 * - 0 - L2 cache clock is running
 * - 1 - L2 cache clock stopped
 */
//@{
#define BP_IOMUXC_GPR5_L2_CLK_STOP      (8)      //!< Bit position for IOMUXC_GPR5_L2_CLK_STOP.
#define BM_IOMUXC_GPR5_L2_CLK_STOP      (0x00000100)  //!< Bit mask for IOMUXC_GPR5_L2_CLK_STOP.

//! @brief Get value of IOMUXC_GPR5_L2_CLK_STOP from a register value.
#define BG_IOMUXC_GPR5_L2_CLK_STOP(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR5_L2_CLK_STOP) >> BP_IOMUXC_GPR5_L2_CLK_STOP)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR6 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR6 - GPR (RW)
 *
 * Reset value: 0x22222222
 */
typedef union _hw_iomuxc_gpr6
{
    reg32_t U;
    struct _hw_iomuxc_gpr6_bitfields
    {
        unsigned IPU1_ID00_WR_QOS : 4; //!< [3:0] IPU1 Write AXI ID=00 Quality of Service (QoS) priority
        unsigned IPU1_ID01_WR_QOS : 4; //!< [7:4] IPU1 Write AXI ID=01 Quality of Service (QoS) priority
        unsigned IPU1_ID10_WR_QOS : 4; //!< [11:8] IPU1 Write AXI ID=10 Quality of Service (QoS) priority
        unsigned IPU1_ID11_WR_QOS : 4; //!< [15:12] IPU1 Write AXI ID=11 Quality of Service (QoS) priority
        unsigned IPU1_ID00_RD_QOS : 4; //!< [19:16] IPU1 Read AXI ID=00 Quality of Service (QoS) priority
        unsigned IPU1_ID01_RD_QOS : 4; //!< [23:20] IPU1 Read AXI ID=01 Quality of Service (QoS) priority
        unsigned IPU1_ID10_RD_QOS : 4; //!< [27:24] IPU1 Read AXI ID=10 Quality of Service (QoS) priority
        unsigned IPU1_ID11_RD_QOS : 4; //!< [31:28] IPU1 Read AXI ID=11 Quality of Service (QoS) priority
    } B;
} hw_iomuxc_gpr6_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR6 register
 */
//@{
#define HW_IOMUXC_GPR6_ADDR      (REGS_IOMUXC_BASE + 0x18)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR6           (*(volatile hw_iomuxc_gpr6_t *) HW_IOMUXC_GPR6_ADDR)
#define HW_IOMUXC_GPR6_RD()      (HW_IOMUXC_GPR6.U)
#define HW_IOMUXC_GPR6_WR(v)     (HW_IOMUXC_GPR6.U = (v))
#define HW_IOMUXC_GPR6_SET(v)    (HW_IOMUXC_GPR6_WR(HW_IOMUXC_GPR6_RD() |  (v)))
#define HW_IOMUXC_GPR6_CLR(v)    (HW_IOMUXC_GPR6_WR(HW_IOMUXC_GPR6_RD() & ~(v)))
#define HW_IOMUXC_GPR6_TOG(v)    (HW_IOMUXC_GPR6_WR(HW_IOMUXC_GPR6_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR6 bitfields
 */

/*! @name Register IOMUXC_GPR6, field IPU1_ID00_WR_QOS[3:0] (RW)
 *
 * IPU1 Write AXI ID=00 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as
 * configured 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR6_IPU1_ID00_WR_QOS      (0)      //!< Bit position for IOMUXC_GPR6_IPU1_ID00_WR_QOS.
#define BM_IOMUXC_GPR6_IPU1_ID00_WR_QOS      (0x0000000f)  //!< Bit mask for IOMUXC_GPR6_IPU1_ID00_WR_QOS.

//! @brief Get value of IOMUXC_GPR6_IPU1_ID00_WR_QOS from a register value.
#define BG_IOMUXC_GPR6_IPU1_ID00_WR_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR6_IPU1_ID00_WR_QOS) >> BP_IOMUXC_GPR6_IPU1_ID00_WR_QOS)

//! @brief Format value for bitfield IOMUXC_GPR6_IPU1_ID00_WR_QOS.
#define BF_IOMUXC_GPR6_IPU1_ID00_WR_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR6_IPU1_ID00_WR_QOS) & BM_IOMUXC_GPR6_IPU1_ID00_WR_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU1_ID00_WR_QOS field to a new value.
#define BW_IOMUXC_GPR6_IPU1_ID00_WR_QOS(v)   (HW_IOMUXC_GPR6_WR((HW_IOMUXC_GPR6_RD() & ~BM_IOMUXC_GPR6_IPU1_ID00_WR_QOS) | BF_IOMUXC_GPR6_IPU1_ID00_WR_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR6, field IPU1_ID01_WR_QOS[7:4] (RW)
 *
 * IPU1 Write AXI ID=01 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as
 * configured 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR6_IPU1_ID01_WR_QOS      (4)      //!< Bit position for IOMUXC_GPR6_IPU1_ID01_WR_QOS.
#define BM_IOMUXC_GPR6_IPU1_ID01_WR_QOS      (0x000000f0)  //!< Bit mask for IOMUXC_GPR6_IPU1_ID01_WR_QOS.

//! @brief Get value of IOMUXC_GPR6_IPU1_ID01_WR_QOS from a register value.
#define BG_IOMUXC_GPR6_IPU1_ID01_WR_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR6_IPU1_ID01_WR_QOS) >> BP_IOMUXC_GPR6_IPU1_ID01_WR_QOS)

//! @brief Format value for bitfield IOMUXC_GPR6_IPU1_ID01_WR_QOS.
#define BF_IOMUXC_GPR6_IPU1_ID01_WR_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR6_IPU1_ID01_WR_QOS) & BM_IOMUXC_GPR6_IPU1_ID01_WR_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU1_ID01_WR_QOS field to a new value.
#define BW_IOMUXC_GPR6_IPU1_ID01_WR_QOS(v)   (HW_IOMUXC_GPR6_WR((HW_IOMUXC_GPR6_RD() & ~BM_IOMUXC_GPR6_IPU1_ID01_WR_QOS) | BF_IOMUXC_GPR6_IPU1_ID01_WR_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR6, field IPU1_ID10_WR_QOS[11:8] (RW)
 *
 * IPU1 Write AXI ID=10 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as
 * configured 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR6_IPU1_ID10_WR_QOS      (8)      //!< Bit position for IOMUXC_GPR6_IPU1_ID10_WR_QOS.
#define BM_IOMUXC_GPR6_IPU1_ID10_WR_QOS      (0x00000f00)  //!< Bit mask for IOMUXC_GPR6_IPU1_ID10_WR_QOS.

//! @brief Get value of IOMUXC_GPR6_IPU1_ID10_WR_QOS from a register value.
#define BG_IOMUXC_GPR6_IPU1_ID10_WR_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR6_IPU1_ID10_WR_QOS) >> BP_IOMUXC_GPR6_IPU1_ID10_WR_QOS)

//! @brief Format value for bitfield IOMUXC_GPR6_IPU1_ID10_WR_QOS.
#define BF_IOMUXC_GPR6_IPU1_ID10_WR_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR6_IPU1_ID10_WR_QOS) & BM_IOMUXC_GPR6_IPU1_ID10_WR_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU1_ID10_WR_QOS field to a new value.
#define BW_IOMUXC_GPR6_IPU1_ID10_WR_QOS(v)   (HW_IOMUXC_GPR6_WR((HW_IOMUXC_GPR6_RD() & ~BM_IOMUXC_GPR6_IPU1_ID10_WR_QOS) | BF_IOMUXC_GPR6_IPU1_ID10_WR_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR6, field IPU1_ID11_WR_QOS[15:12] (RW)
 *
 * IPU1 Write AXI ID=11 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as
 * configured 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR6_IPU1_ID11_WR_QOS      (12)      //!< Bit position for IOMUXC_GPR6_IPU1_ID11_WR_QOS.
#define BM_IOMUXC_GPR6_IPU1_ID11_WR_QOS      (0x0000f000)  //!< Bit mask for IOMUXC_GPR6_IPU1_ID11_WR_QOS.

//! @brief Get value of IOMUXC_GPR6_IPU1_ID11_WR_QOS from a register value.
#define BG_IOMUXC_GPR6_IPU1_ID11_WR_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR6_IPU1_ID11_WR_QOS) >> BP_IOMUXC_GPR6_IPU1_ID11_WR_QOS)

//! @brief Format value for bitfield IOMUXC_GPR6_IPU1_ID11_WR_QOS.
#define BF_IOMUXC_GPR6_IPU1_ID11_WR_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR6_IPU1_ID11_WR_QOS) & BM_IOMUXC_GPR6_IPU1_ID11_WR_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU1_ID11_WR_QOS field to a new value.
#define BW_IOMUXC_GPR6_IPU1_ID11_WR_QOS(v)   (HW_IOMUXC_GPR6_WR((HW_IOMUXC_GPR6_RD() & ~BM_IOMUXC_GPR6_IPU1_ID11_WR_QOS) | BF_IOMUXC_GPR6_IPU1_ID11_WR_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR6, field IPU1_ID00_RD_QOS[19:16] (RW)
 *
 * IPU1 Read AXI ID=00 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as configured
 * 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR6_IPU1_ID00_RD_QOS      (16)      //!< Bit position for IOMUXC_GPR6_IPU1_ID00_RD_QOS.
#define BM_IOMUXC_GPR6_IPU1_ID00_RD_QOS      (0x000f0000)  //!< Bit mask for IOMUXC_GPR6_IPU1_ID00_RD_QOS.

//! @brief Get value of IOMUXC_GPR6_IPU1_ID00_RD_QOS from a register value.
#define BG_IOMUXC_GPR6_IPU1_ID00_RD_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR6_IPU1_ID00_RD_QOS) >> BP_IOMUXC_GPR6_IPU1_ID00_RD_QOS)

//! @brief Format value for bitfield IOMUXC_GPR6_IPU1_ID00_RD_QOS.
#define BF_IOMUXC_GPR6_IPU1_ID00_RD_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR6_IPU1_ID00_RD_QOS) & BM_IOMUXC_GPR6_IPU1_ID00_RD_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU1_ID00_RD_QOS field to a new value.
#define BW_IOMUXC_GPR6_IPU1_ID00_RD_QOS(v)   (HW_IOMUXC_GPR6_WR((HW_IOMUXC_GPR6_RD() & ~BM_IOMUXC_GPR6_IPU1_ID00_RD_QOS) | BF_IOMUXC_GPR6_IPU1_ID00_RD_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR6, field IPU1_ID01_RD_QOS[23:20] (RW)
 *
 * IPU1 Read AXI ID=01 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as configured
 * 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR6_IPU1_ID01_RD_QOS      (20)      //!< Bit position for IOMUXC_GPR6_IPU1_ID01_RD_QOS.
#define BM_IOMUXC_GPR6_IPU1_ID01_RD_QOS      (0x00f00000)  //!< Bit mask for IOMUXC_GPR6_IPU1_ID01_RD_QOS.

//! @brief Get value of IOMUXC_GPR6_IPU1_ID01_RD_QOS from a register value.
#define BG_IOMUXC_GPR6_IPU1_ID01_RD_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR6_IPU1_ID01_RD_QOS) >> BP_IOMUXC_GPR6_IPU1_ID01_RD_QOS)

//! @brief Format value for bitfield IOMUXC_GPR6_IPU1_ID01_RD_QOS.
#define BF_IOMUXC_GPR6_IPU1_ID01_RD_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR6_IPU1_ID01_RD_QOS) & BM_IOMUXC_GPR6_IPU1_ID01_RD_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU1_ID01_RD_QOS field to a new value.
#define BW_IOMUXC_GPR6_IPU1_ID01_RD_QOS(v)   (HW_IOMUXC_GPR6_WR((HW_IOMUXC_GPR6_RD() & ~BM_IOMUXC_GPR6_IPU1_ID01_RD_QOS) | BF_IOMUXC_GPR6_IPU1_ID01_RD_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR6, field IPU1_ID10_RD_QOS[27:24] (RW)
 *
 * IPU1 Read AXI ID=10 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as configured
 * 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR6_IPU1_ID10_RD_QOS      (24)      //!< Bit position for IOMUXC_GPR6_IPU1_ID10_RD_QOS.
#define BM_IOMUXC_GPR6_IPU1_ID10_RD_QOS      (0x0f000000)  //!< Bit mask for IOMUXC_GPR6_IPU1_ID10_RD_QOS.

//! @brief Get value of IOMUXC_GPR6_IPU1_ID10_RD_QOS from a register value.
#define BG_IOMUXC_GPR6_IPU1_ID10_RD_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR6_IPU1_ID10_RD_QOS) >> BP_IOMUXC_GPR6_IPU1_ID10_RD_QOS)

//! @brief Format value for bitfield IOMUXC_GPR6_IPU1_ID10_RD_QOS.
#define BF_IOMUXC_GPR6_IPU1_ID10_RD_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR6_IPU1_ID10_RD_QOS) & BM_IOMUXC_GPR6_IPU1_ID10_RD_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU1_ID10_RD_QOS field to a new value.
#define BW_IOMUXC_GPR6_IPU1_ID10_RD_QOS(v)   (HW_IOMUXC_GPR6_WR((HW_IOMUXC_GPR6_RD() & ~BM_IOMUXC_GPR6_IPU1_ID10_RD_QOS) | BF_IOMUXC_GPR6_IPU1_ID10_RD_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR6, field IPU1_ID11_RD_QOS[31:28] (RW)
 *
 * IPU1 Read AXI ID=11 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as configured
 * 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR6_IPU1_ID11_RD_QOS      (28)      //!< Bit position for IOMUXC_GPR6_IPU1_ID11_RD_QOS.
#define BM_IOMUXC_GPR6_IPU1_ID11_RD_QOS      (0xf0000000)  //!< Bit mask for IOMUXC_GPR6_IPU1_ID11_RD_QOS.

//! @brief Get value of IOMUXC_GPR6_IPU1_ID11_RD_QOS from a register value.
#define BG_IOMUXC_GPR6_IPU1_ID11_RD_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR6_IPU1_ID11_RD_QOS) >> BP_IOMUXC_GPR6_IPU1_ID11_RD_QOS)

//! @brief Format value for bitfield IOMUXC_GPR6_IPU1_ID11_RD_QOS.
#define BF_IOMUXC_GPR6_IPU1_ID11_RD_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR6_IPU1_ID11_RD_QOS) & BM_IOMUXC_GPR6_IPU1_ID11_RD_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU1_ID11_RD_QOS field to a new value.
#define BW_IOMUXC_GPR6_IPU1_ID11_RD_QOS(v)   (HW_IOMUXC_GPR6_WR((HW_IOMUXC_GPR6_RD() & ~BM_IOMUXC_GPR6_IPU1_ID11_RD_QOS) | BF_IOMUXC_GPR6_IPU1_ID11_RD_QOS(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR7 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR7 - GPR (RW)
 *
 * Reset value: 0x22222222
 */
typedef union _hw_iomuxc_gpr7
{
    reg32_t U;
    struct _hw_iomuxc_gpr7_bitfields
    {
        unsigned IPU2_ID00_WR_QOS : 4; //!< [3:0] IPU2 Write AXI ID=00 Quality of Service (QoS) priority
        unsigned IPU2_ID01_WR_QOS : 4; //!< [7:4] IPU2 Write AXI ID=01 Quality of Service (QoS) priority
        unsigned IPU2_ID10_WR_QOS : 4; //!< [11:8] IPU2 Write AXI ID=10 Quality of Service (QoS) priority
        unsigned IPU2_ID11_WR_QOS : 4; //!< [15:12] IPU2 Write AXI ID=11 Quality of Service (QoS) priority
        unsigned IPU2_ID00_RD_QOS : 4; //!< [19:16] IPU2 Read AXI ID=00 Quality of Service (QoS) priority
        unsigned IPU2_ID01_RD_QOS : 4; //!< [23:20] IPU2 Read AXI ID=01 Quality of Service (QoS) priority
        unsigned IPU2_ID10_RD_QOS : 4; //!< [27:24] IPU2 Read AXI ID=10 Quality of Service (QoS) priority
        unsigned IPU2_ID11_RD_QOS : 4; //!< [31:28] IPU2 Read AXI ID=11 Quality of Service (QoS) priority
    } B;
} hw_iomuxc_gpr7_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR7 register
 */
//@{
#define HW_IOMUXC_GPR7_ADDR      (REGS_IOMUXC_BASE + 0x1c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR7           (*(volatile hw_iomuxc_gpr7_t *) HW_IOMUXC_GPR7_ADDR)
#define HW_IOMUXC_GPR7_RD()      (HW_IOMUXC_GPR7.U)
#define HW_IOMUXC_GPR7_WR(v)     (HW_IOMUXC_GPR7.U = (v))
#define HW_IOMUXC_GPR7_SET(v)    (HW_IOMUXC_GPR7_WR(HW_IOMUXC_GPR7_RD() |  (v)))
#define HW_IOMUXC_GPR7_CLR(v)    (HW_IOMUXC_GPR7_WR(HW_IOMUXC_GPR7_RD() & ~(v)))
#define HW_IOMUXC_GPR7_TOG(v)    (HW_IOMUXC_GPR7_WR(HW_IOMUXC_GPR7_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR7 bitfields
 */

/*! @name Register IOMUXC_GPR7, field IPU2_ID00_WR_QOS[3:0] (RW)
 *
 * IPU2 Write AXI ID=00 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as
 * configured 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR7_IPU2_ID00_WR_QOS      (0)      //!< Bit position for IOMUXC_GPR7_IPU2_ID00_WR_QOS.
#define BM_IOMUXC_GPR7_IPU2_ID00_WR_QOS      (0x0000000f)  //!< Bit mask for IOMUXC_GPR7_IPU2_ID00_WR_QOS.

//! @brief Get value of IOMUXC_GPR7_IPU2_ID00_WR_QOS from a register value.
#define BG_IOMUXC_GPR7_IPU2_ID00_WR_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR7_IPU2_ID00_WR_QOS) >> BP_IOMUXC_GPR7_IPU2_ID00_WR_QOS)

//! @brief Format value for bitfield IOMUXC_GPR7_IPU2_ID00_WR_QOS.
#define BF_IOMUXC_GPR7_IPU2_ID00_WR_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR7_IPU2_ID00_WR_QOS) & BM_IOMUXC_GPR7_IPU2_ID00_WR_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU2_ID00_WR_QOS field to a new value.
#define BW_IOMUXC_GPR7_IPU2_ID00_WR_QOS(v)   (HW_IOMUXC_GPR7_WR((HW_IOMUXC_GPR7_RD() & ~BM_IOMUXC_GPR7_IPU2_ID00_WR_QOS) | BF_IOMUXC_GPR7_IPU2_ID00_WR_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR7, field IPU2_ID01_WR_QOS[7:4] (RW)
 *
 * IPU2 Write AXI ID=01 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as
 * configured 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR7_IPU2_ID01_WR_QOS      (4)      //!< Bit position for IOMUXC_GPR7_IPU2_ID01_WR_QOS.
#define BM_IOMUXC_GPR7_IPU2_ID01_WR_QOS      (0x000000f0)  //!< Bit mask for IOMUXC_GPR7_IPU2_ID01_WR_QOS.

//! @brief Get value of IOMUXC_GPR7_IPU2_ID01_WR_QOS from a register value.
#define BG_IOMUXC_GPR7_IPU2_ID01_WR_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR7_IPU2_ID01_WR_QOS) >> BP_IOMUXC_GPR7_IPU2_ID01_WR_QOS)

//! @brief Format value for bitfield IOMUXC_GPR7_IPU2_ID01_WR_QOS.
#define BF_IOMUXC_GPR7_IPU2_ID01_WR_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR7_IPU2_ID01_WR_QOS) & BM_IOMUXC_GPR7_IPU2_ID01_WR_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU2_ID01_WR_QOS field to a new value.
#define BW_IOMUXC_GPR7_IPU2_ID01_WR_QOS(v)   (HW_IOMUXC_GPR7_WR((HW_IOMUXC_GPR7_RD() & ~BM_IOMUXC_GPR7_IPU2_ID01_WR_QOS) | BF_IOMUXC_GPR7_IPU2_ID01_WR_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR7, field IPU2_ID10_WR_QOS[11:8] (RW)
 *
 * IPU2 Write AXI ID=10 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as
 * configured 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR7_IPU2_ID10_WR_QOS      (8)      //!< Bit position for IOMUXC_GPR7_IPU2_ID10_WR_QOS.
#define BM_IOMUXC_GPR7_IPU2_ID10_WR_QOS      (0x00000f00)  //!< Bit mask for IOMUXC_GPR7_IPU2_ID10_WR_QOS.

//! @brief Get value of IOMUXC_GPR7_IPU2_ID10_WR_QOS from a register value.
#define BG_IOMUXC_GPR7_IPU2_ID10_WR_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR7_IPU2_ID10_WR_QOS) >> BP_IOMUXC_GPR7_IPU2_ID10_WR_QOS)

//! @brief Format value for bitfield IOMUXC_GPR7_IPU2_ID10_WR_QOS.
#define BF_IOMUXC_GPR7_IPU2_ID10_WR_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR7_IPU2_ID10_WR_QOS) & BM_IOMUXC_GPR7_IPU2_ID10_WR_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU2_ID10_WR_QOS field to a new value.
#define BW_IOMUXC_GPR7_IPU2_ID10_WR_QOS(v)   (HW_IOMUXC_GPR7_WR((HW_IOMUXC_GPR7_RD() & ~BM_IOMUXC_GPR7_IPU2_ID10_WR_QOS) | BF_IOMUXC_GPR7_IPU2_ID10_WR_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR7, field IPU2_ID11_WR_QOS[15:12] (RW)
 *
 * IPU2 Write AXI ID=11 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as
 * configured 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR7_IPU2_ID11_WR_QOS      (12)      //!< Bit position for IOMUXC_GPR7_IPU2_ID11_WR_QOS.
#define BM_IOMUXC_GPR7_IPU2_ID11_WR_QOS      (0x0000f000)  //!< Bit mask for IOMUXC_GPR7_IPU2_ID11_WR_QOS.

//! @brief Get value of IOMUXC_GPR7_IPU2_ID11_WR_QOS from a register value.
#define BG_IOMUXC_GPR7_IPU2_ID11_WR_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR7_IPU2_ID11_WR_QOS) >> BP_IOMUXC_GPR7_IPU2_ID11_WR_QOS)

//! @brief Format value for bitfield IOMUXC_GPR7_IPU2_ID11_WR_QOS.
#define BF_IOMUXC_GPR7_IPU2_ID11_WR_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR7_IPU2_ID11_WR_QOS) & BM_IOMUXC_GPR7_IPU2_ID11_WR_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU2_ID11_WR_QOS field to a new value.
#define BW_IOMUXC_GPR7_IPU2_ID11_WR_QOS(v)   (HW_IOMUXC_GPR7_WR((HW_IOMUXC_GPR7_RD() & ~BM_IOMUXC_GPR7_IPU2_ID11_WR_QOS) | BF_IOMUXC_GPR7_IPU2_ID11_WR_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR7, field IPU2_ID00_RD_QOS[19:16] (RW)
 *
 * IPU2 Read AXI ID=00 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as configured
 * 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR7_IPU2_ID00_RD_QOS      (16)      //!< Bit position for IOMUXC_GPR7_IPU2_ID00_RD_QOS.
#define BM_IOMUXC_GPR7_IPU2_ID00_RD_QOS      (0x000f0000)  //!< Bit mask for IOMUXC_GPR7_IPU2_ID00_RD_QOS.

//! @brief Get value of IOMUXC_GPR7_IPU2_ID00_RD_QOS from a register value.
#define BG_IOMUXC_GPR7_IPU2_ID00_RD_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR7_IPU2_ID00_RD_QOS) >> BP_IOMUXC_GPR7_IPU2_ID00_RD_QOS)

//! @brief Format value for bitfield IOMUXC_GPR7_IPU2_ID00_RD_QOS.
#define BF_IOMUXC_GPR7_IPU2_ID00_RD_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR7_IPU2_ID00_RD_QOS) & BM_IOMUXC_GPR7_IPU2_ID00_RD_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU2_ID00_RD_QOS field to a new value.
#define BW_IOMUXC_GPR7_IPU2_ID00_RD_QOS(v)   (HW_IOMUXC_GPR7_WR((HW_IOMUXC_GPR7_RD() & ~BM_IOMUXC_GPR7_IPU2_ID00_RD_QOS) | BF_IOMUXC_GPR7_IPU2_ID00_RD_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR7, field IPU2_ID01_RD_QOS[23:20] (RW)
 *
 * IPU2 Read AXI ID=01 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as configured
 * 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR7_IPU2_ID01_RD_QOS      (20)      //!< Bit position for IOMUXC_GPR7_IPU2_ID01_RD_QOS.
#define BM_IOMUXC_GPR7_IPU2_ID01_RD_QOS      (0x00f00000)  //!< Bit mask for IOMUXC_GPR7_IPU2_ID01_RD_QOS.

//! @brief Get value of IOMUXC_GPR7_IPU2_ID01_RD_QOS from a register value.
#define BG_IOMUXC_GPR7_IPU2_ID01_RD_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR7_IPU2_ID01_RD_QOS) >> BP_IOMUXC_GPR7_IPU2_ID01_RD_QOS)

//! @brief Format value for bitfield IOMUXC_GPR7_IPU2_ID01_RD_QOS.
#define BF_IOMUXC_GPR7_IPU2_ID01_RD_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR7_IPU2_ID01_RD_QOS) & BM_IOMUXC_GPR7_IPU2_ID01_RD_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU2_ID01_RD_QOS field to a new value.
#define BW_IOMUXC_GPR7_IPU2_ID01_RD_QOS(v)   (HW_IOMUXC_GPR7_WR((HW_IOMUXC_GPR7_RD() & ~BM_IOMUXC_GPR7_IPU2_ID01_RD_QOS) | BF_IOMUXC_GPR7_IPU2_ID01_RD_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR7, field IPU2_ID10_RD_QOS[27:24] (RW)
 *
 * IPU2 Read AXI ID=10 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as configured
 * 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR7_IPU2_ID10_RD_QOS      (24)      //!< Bit position for IOMUXC_GPR7_IPU2_ID10_RD_QOS.
#define BM_IOMUXC_GPR7_IPU2_ID10_RD_QOS      (0x0f000000)  //!< Bit mask for IOMUXC_GPR7_IPU2_ID10_RD_QOS.

//! @brief Get value of IOMUXC_GPR7_IPU2_ID10_RD_QOS from a register value.
#define BG_IOMUXC_GPR7_IPU2_ID10_RD_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR7_IPU2_ID10_RD_QOS) >> BP_IOMUXC_GPR7_IPU2_ID10_RD_QOS)

//! @brief Format value for bitfield IOMUXC_GPR7_IPU2_ID10_RD_QOS.
#define BF_IOMUXC_GPR7_IPU2_ID10_RD_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR7_IPU2_ID10_RD_QOS) & BM_IOMUXC_GPR7_IPU2_ID10_RD_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU2_ID10_RD_QOS field to a new value.
#define BW_IOMUXC_GPR7_IPU2_ID10_RD_QOS(v)   (HW_IOMUXC_GPR7_WR((HW_IOMUXC_GPR7_RD() & ~BM_IOMUXC_GPR7_IPU2_ID10_RD_QOS) | BF_IOMUXC_GPR7_IPU2_ID10_RD_QOS(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR7, field IPU2_ID11_RD_QOS[31:28] (RW)
 *
 * IPU2 Read AXI ID=11 Quality of Service (QoS) priority 0xxx - 3 lsb’s will be passed as configured
 * 1xxx - 1111
 */
//@{
#define BP_IOMUXC_GPR7_IPU2_ID11_RD_QOS      (28)      //!< Bit position for IOMUXC_GPR7_IPU2_ID11_RD_QOS.
#define BM_IOMUXC_GPR7_IPU2_ID11_RD_QOS      (0xf0000000)  //!< Bit mask for IOMUXC_GPR7_IPU2_ID11_RD_QOS.

//! @brief Get value of IOMUXC_GPR7_IPU2_ID11_RD_QOS from a register value.
#define BG_IOMUXC_GPR7_IPU2_ID11_RD_QOS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR7_IPU2_ID11_RD_QOS) >> BP_IOMUXC_GPR7_IPU2_ID11_RD_QOS)

//! @brief Format value for bitfield IOMUXC_GPR7_IPU2_ID11_RD_QOS.
#define BF_IOMUXC_GPR7_IPU2_ID11_RD_QOS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR7_IPU2_ID11_RD_QOS) & BM_IOMUXC_GPR7_IPU2_ID11_RD_QOS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the IPU2_ID11_RD_QOS field to a new value.
#define BW_IOMUXC_GPR7_IPU2_ID11_RD_QOS(v)   (HW_IOMUXC_GPR7_WR((HW_IOMUXC_GPR7_RD() & ~BM_IOMUXC_GPR7_IPU2_ID11_RD_QOS) | BF_IOMUXC_GPR7_IPU2_ID11_RD_QOS(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR8 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR8 - GPR (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_gpr8
{
    reg32_t U;
    struct _hw_iomuxc_gpr8_bitfields
    {
        unsigned PCS_TX_DEEMPH_GEN1 : 6; //!< [5:0] PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen1 rate.
        unsigned PCS_TX_DEEMPH_GEN2_3P5DB : 6; //!< [11:6] PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen2 (3p5db) rate.
        unsigned PCS_TX_DEEMPH_GEN2_6DB : 6; //!< [17:12] PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b0 and the PHY is running at the Gen2 (6db) rate.
        unsigned PCS_TX_SWING_FULL : 7; //!< [24:18] PCIe_PHY - This static value sets the Tx driver SWING_FULL value.
        unsigned PCS_TX_SWING_LOW : 7; //!< [31:25] PCIe_PHY - This static value sets the launch amplitude of the transmitter when pipe0_tx_swing is set to 1'b0 (default state).
    } B;
} hw_iomuxc_gpr8_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR8 register
 */
//@{
#define HW_IOMUXC_GPR8_ADDR      (REGS_IOMUXC_BASE + 0x20)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR8           (*(volatile hw_iomuxc_gpr8_t *) HW_IOMUXC_GPR8_ADDR)
#define HW_IOMUXC_GPR8_RD()      (HW_IOMUXC_GPR8.U)
#define HW_IOMUXC_GPR8_WR(v)     (HW_IOMUXC_GPR8.U = (v))
#define HW_IOMUXC_GPR8_SET(v)    (HW_IOMUXC_GPR8_WR(HW_IOMUXC_GPR8_RD() |  (v)))
#define HW_IOMUXC_GPR8_CLR(v)    (HW_IOMUXC_GPR8_WR(HW_IOMUXC_GPR8_RD() & ~(v)))
#define HW_IOMUXC_GPR8_TOG(v)    (HW_IOMUXC_GPR8_WR(HW_IOMUXC_GPR8_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR8 bitfields
 */

/*! @name Register IOMUXC_GPR8, field PCS_TX_DEEMPH_GEN1[5:0] (RW)
 *
 * PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where
 * pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen1 rate.
 * 6'hxx - Gen1 De-emphasis value.
 */
//@{
#define BP_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1      (0)      //!< Bit position for IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1.
#define BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1      (0x0000003f)  //!< Bit mask for IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1.

//! @brief Get value of IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1 from a register value.
#define BG_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1) >> BP_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1)

//! @brief Format value for bitfield IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1.
#define BF_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1) & BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCS_TX_DEEMPH_GEN1 field to a new value.
#define BW_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1(v)   (HW_IOMUXC_GPR8_WR((HW_IOMUXC_GPR8_RD() & ~BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1) | BF_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR8, field PCS_TX_DEEMPH_GEN2_3P5DB[11:6] (RW)
 *
 * PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where
 * pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen2 (3p5db)
 * rate. 6'hxx - Gen2 De-emphasis value.
 */
//@{
#define BP_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB      (6)      //!< Bit position for IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB.
#define BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB      (0x00000fc0)  //!< Bit mask for IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB.

//! @brief Get value of IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB from a register value.
#define BG_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB) >> BP_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB)

//! @brief Format value for bitfield IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB.
#define BF_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB) & BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCS_TX_DEEMPH_GEN2_3P5DB field to a new value.
#define BW_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB(v)   (HW_IOMUXC_GPR8_WR((HW_IOMUXC_GPR8_RD() & ~BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB) | BF_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR8, field PCS_TX_DEEMPH_GEN2_6DB[17:12] (RW)
 *
 * PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where
 * pipe0_tx_deemph is set to 1'b0 and the PHY is running at the Gen2 (6db) rate. 6'hxx - Gen2 (6db)
 * De-emphasis value.
 */
//@{
#define BP_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB      (12)      //!< Bit position for IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB.
#define BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB      (0x0003f000)  //!< Bit mask for IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB.

//! @brief Get value of IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB from a register value.
#define BG_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB) >> BP_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB)

//! @brief Format value for bitfield IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB.
#define BF_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB) & BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCS_TX_DEEMPH_GEN2_6DB field to a new value.
#define BW_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB(v)   (HW_IOMUXC_GPR8_WR((HW_IOMUXC_GPR8_RD() & ~BM_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB) | BF_IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR8, field PCS_TX_SWING_FULL[24:18] (RW)
 *
 * PCIe_PHY - This static value sets the Tx driver SWING_FULL value. 7'hxx - Gen2 TX SWING FULL
 * value.
 */
//@{
#define BP_IOMUXC_GPR8_PCS_TX_SWING_FULL      (18)      //!< Bit position for IOMUXC_GPR8_PCS_TX_SWING_FULL.
#define BM_IOMUXC_GPR8_PCS_TX_SWING_FULL      (0x01fc0000)  //!< Bit mask for IOMUXC_GPR8_PCS_TX_SWING_FULL.

//! @brief Get value of IOMUXC_GPR8_PCS_TX_SWING_FULL from a register value.
#define BG_IOMUXC_GPR8_PCS_TX_SWING_FULL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR8_PCS_TX_SWING_FULL) >> BP_IOMUXC_GPR8_PCS_TX_SWING_FULL)

//! @brief Format value for bitfield IOMUXC_GPR8_PCS_TX_SWING_FULL.
#define BF_IOMUXC_GPR8_PCS_TX_SWING_FULL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR8_PCS_TX_SWING_FULL) & BM_IOMUXC_GPR8_PCS_TX_SWING_FULL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCS_TX_SWING_FULL field to a new value.
#define BW_IOMUXC_GPR8_PCS_TX_SWING_FULL(v)   (HW_IOMUXC_GPR8_WR((HW_IOMUXC_GPR8_RD() & ~BM_IOMUXC_GPR8_PCS_TX_SWING_FULL) | BF_IOMUXC_GPR8_PCS_TX_SWING_FULL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR8, field PCS_TX_SWING_LOW[31:25] (RW)
 *
 * PCIe_PHY - This static value sets the launch amplitude of the transmitter when pipe0_tx_swing is
 * set to 1'b0 (default state). 7'hxx - TX launch amplitude swing_low value.
 */
//@{
#define BP_IOMUXC_GPR8_PCS_TX_SWING_LOW      (25)      //!< Bit position for IOMUXC_GPR8_PCS_TX_SWING_LOW.
#define BM_IOMUXC_GPR8_PCS_TX_SWING_LOW      (0xfe000000)  //!< Bit mask for IOMUXC_GPR8_PCS_TX_SWING_LOW.

//! @brief Get value of IOMUXC_GPR8_PCS_TX_SWING_LOW from a register value.
#define BG_IOMUXC_GPR8_PCS_TX_SWING_LOW(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR8_PCS_TX_SWING_LOW) >> BP_IOMUXC_GPR8_PCS_TX_SWING_LOW)

//! @brief Format value for bitfield IOMUXC_GPR8_PCS_TX_SWING_LOW.
#define BF_IOMUXC_GPR8_PCS_TX_SWING_LOW(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR8_PCS_TX_SWING_LOW) & BM_IOMUXC_GPR8_PCS_TX_SWING_LOW)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCS_TX_SWING_LOW field to a new value.
#define BW_IOMUXC_GPR8_PCS_TX_SWING_LOW(v)   (HW_IOMUXC_GPR8_WR((HW_IOMUXC_GPR8_RD() & ~BM_IOMUXC_GPR8_PCS_TX_SWING_LOW) | BF_IOMUXC_GPR8_PCS_TX_SWING_LOW(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR9 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR9 - GPR (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_gpr9
{
    reg32_t U;
    struct _hw_iomuxc_gpr9_bitfields
    {
        unsigned TZASC1_BYP : 1; //!< [0] TZASC-1 BYPASS MUX control
        unsigned TZASC2_BYP : 1; //!< [1] TZASC-2 BYPASS MUX control
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_gpr9_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR9 register
 */
//@{
#define HW_IOMUXC_GPR9_ADDR      (REGS_IOMUXC_BASE + 0x24)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR9           (*(volatile hw_iomuxc_gpr9_t *) HW_IOMUXC_GPR9_ADDR)
#define HW_IOMUXC_GPR9_RD()      (HW_IOMUXC_GPR9.U)
#define HW_IOMUXC_GPR9_WR(v)     (HW_IOMUXC_GPR9.U = (v))
#define HW_IOMUXC_GPR9_SET(v)    (HW_IOMUXC_GPR9_WR(HW_IOMUXC_GPR9_RD() |  (v)))
#define HW_IOMUXC_GPR9_CLR(v)    (HW_IOMUXC_GPR9_WR(HW_IOMUXC_GPR9_RD() & ~(v)))
#define HW_IOMUXC_GPR9_TOG(v)    (HW_IOMUXC_GPR9_WR(HW_IOMUXC_GPR9_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR9 bitfields
 */

/*! @name Register IOMUXC_GPR9, field TZASC1_BYP[0] (RO)
 *
 * TZASC-1 BYPASS MUX control
 *
 * Values:
 * - 0 - The TZASC-1 is bypassed and the transactions to DDR are not being checked.
 * - 1 - The TZASC-1 is not bypassed and the transactions to DDR are being monitored / checked.
 */
//@{
#define BP_IOMUXC_GPR9_TZASC1_BYP      (0)      //!< Bit position for IOMUXC_GPR9_TZASC1_BYP.
#define BM_IOMUXC_GPR9_TZASC1_BYP      (0x00000001)  //!< Bit mask for IOMUXC_GPR9_TZASC1_BYP.

//! @brief Get value of IOMUXC_GPR9_TZASC1_BYP from a register value.
#define BG_IOMUXC_GPR9_TZASC1_BYP(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR9_TZASC1_BYP) >> BP_IOMUXC_GPR9_TZASC1_BYP)
//@}

/*! @name Register IOMUXC_GPR9, field TZASC2_BYP[1] (RO)
 *
 * TZASC-2 BYPASS MUX control
 *
 * Values:
 * - 0 - The TZASC-2 is bypassed and the transactions to DDR are not being checked.
 * - 1 - The TZASC-2 is not bypassed and the transactions to DDR are being monitored / checked.
 */
//@{
#define BP_IOMUXC_GPR9_TZASC2_BYP      (1)      //!< Bit position for IOMUXC_GPR9_TZASC2_BYP.
#define BM_IOMUXC_GPR9_TZASC2_BYP      (0x00000002)  //!< Bit mask for IOMUXC_GPR9_TZASC2_BYP.

//! @brief Get value of IOMUXC_GPR9_TZASC2_BYP from a register value.
#define BG_IOMUXC_GPR9_TZASC2_BYP(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR9_TZASC2_BYP) >> BP_IOMUXC_GPR9_TZASC2_BYP)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR10 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR10 - GPR (RW)
 *
 * Reset value: 0x00003800
 */
typedef union _hw_iomuxc_gpr10
{
    reg32_t U;
    struct _hw_iomuxc_gpr10_bitfields
    {
        unsigned DCIC1_MUX_CTL : 2; //!< [1:0] DCIC-1 MUX control
        unsigned DCIC2_MUX_CTL : 2; //!< [3:2] DCIC-2 MUX control
        unsigned OCRAM_TZ_EN : 1; //!< [4] OCRAM TrustZone (TZ) enable.
        unsigned OCRAM_TZ_ADDR : 6; //!< [10:5] OCRAM TrustZone (TZ) start address.
        unsigned SEC_ERR_RESP : 1; //!< [11] Security error response enable for all security gaskets (on both AHB and AXI busses)
        unsigned DBG_CLK_EN : 1; //!< [12] ARM Debug clock enable
        unsigned DBG_EN : 1; //!< [13] ARM non secure (non-invasive) debug enable
        unsigned RESERVED0 : 2; //!< [15:14] Reserved
        unsigned LOCK_DCIC1_MUX_CTL : 2; //!< [17:16] Lock DCIC1_MUX_CTL field for changes.
        unsigned LOCK_DCIC2_MUX_CTL : 2; //!< [19:18] Lock DCIC2_MUX_CTL field for changes.
        unsigned LOCK_OCRAM_TZ_EN : 1; //!< [20] Lock OCRAM_TZ_EN field for changes.
        unsigned LOCK_OCRAM_TZ_ADDR : 6; //!< [26:21] Lock OCRAM_TZ_ADDR field for changes.
        unsigned LOCK_SEC_ERR_RESP : 1; //!< [27] Lock SEC_ERR_RESP field for changes.
        unsigned LOCK_DBG_CLK_EN : 1; //!< [28] Lock DBG_CLK_EN field for changes.
        unsigned LOCK_DBG_EN : 1; //!< [29] Lock DBG_EN field for changes.
        unsigned RESERVED1 : 2; //!< [31:30] Reserved
    } B;
} hw_iomuxc_gpr10_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR10 register
 */
//@{
#define HW_IOMUXC_GPR10_ADDR      (REGS_IOMUXC_BASE + 0x28)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR10           (*(volatile hw_iomuxc_gpr10_t *) HW_IOMUXC_GPR10_ADDR)
#define HW_IOMUXC_GPR10_RD()      (HW_IOMUXC_GPR10.U)
#define HW_IOMUXC_GPR10_WR(v)     (HW_IOMUXC_GPR10.U = (v))
#define HW_IOMUXC_GPR10_SET(v)    (HW_IOMUXC_GPR10_WR(HW_IOMUXC_GPR10_RD() |  (v)))
#define HW_IOMUXC_GPR10_CLR(v)    (HW_IOMUXC_GPR10_WR(HW_IOMUXC_GPR10_RD() & ~(v)))
#define HW_IOMUXC_GPR10_TOG(v)    (HW_IOMUXC_GPR10_WR(HW_IOMUXC_GPR10_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR10 bitfields
 */

/*! @name Register IOMUXC_GPR10, field DCIC1_MUX_CTL[1:0] (RW)
 *
 * DCIC-1 MUX control
 *
 * Values:
 * - 00 - DCIC-1 source is IPU0 or IPU1 DI0 port
 * - 01 - DCIC-1 source is LVDS0
 * - 10 - DCIC-1 source is LVDS1
 * - 11 - DCIC-1 source is HDMI
 */
//@{
#define BP_IOMUXC_GPR10_DCIC1_MUX_CTL      (0)      //!< Bit position for IOMUXC_GPR10_DCIC1_MUX_CTL.
#define BM_IOMUXC_GPR10_DCIC1_MUX_CTL      (0x00000003)  //!< Bit mask for IOMUXC_GPR10_DCIC1_MUX_CTL.

//! @brief Get value of IOMUXC_GPR10_DCIC1_MUX_CTL from a register value.
#define BG_IOMUXC_GPR10_DCIC1_MUX_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_DCIC1_MUX_CTL) >> BP_IOMUXC_GPR10_DCIC1_MUX_CTL)

//! @brief Format value for bitfield IOMUXC_GPR10_DCIC1_MUX_CTL.
#define BF_IOMUXC_GPR10_DCIC1_MUX_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_DCIC1_MUX_CTL) & BM_IOMUXC_GPR10_DCIC1_MUX_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DCIC1_MUX_CTL field to a new value.
#define BW_IOMUXC_GPR10_DCIC1_MUX_CTL(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_DCIC1_MUX_CTL) | BF_IOMUXC_GPR10_DCIC1_MUX_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field DCIC2_MUX_CTL[3:2] (RW)
 *
 * DCIC-2 MUX control
 *
 * Values:
 * - 00 - DCIC-2 source is IPU0 DI1 port
 * - 01 - DCIC-2 source is LVDS0
 * - 10 - DCIC-2 source is LVDS1
 * - 11 - DCIC-2 source is MIPI DPI
 */
//@{
#define BP_IOMUXC_GPR10_DCIC2_MUX_CTL      (2)      //!< Bit position for IOMUXC_GPR10_DCIC2_MUX_CTL.
#define BM_IOMUXC_GPR10_DCIC2_MUX_CTL      (0x0000000c)  //!< Bit mask for IOMUXC_GPR10_DCIC2_MUX_CTL.

//! @brief Get value of IOMUXC_GPR10_DCIC2_MUX_CTL from a register value.
#define BG_IOMUXC_GPR10_DCIC2_MUX_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_DCIC2_MUX_CTL) >> BP_IOMUXC_GPR10_DCIC2_MUX_CTL)

//! @brief Format value for bitfield IOMUXC_GPR10_DCIC2_MUX_CTL.
#define BF_IOMUXC_GPR10_DCIC2_MUX_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_DCIC2_MUX_CTL) & BM_IOMUXC_GPR10_DCIC2_MUX_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DCIC2_MUX_CTL field to a new value.
#define BW_IOMUXC_GPR10_DCIC2_MUX_CTL(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_DCIC2_MUX_CTL) | BF_IOMUXC_GPR10_DCIC2_MUX_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field OCRAM_TZ_EN[4] (RW)
 *
 * OCRAM TrustZone (TZ) enable.
 *
 * Values:
 * - 0 - The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-
 *     secure/user/supervisor).
 * - 1 - The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR]
 *     follows the execution mode access policy described in CSU chapter.
 */
//@{
#define BP_IOMUXC_GPR10_OCRAM_TZ_EN      (4)      //!< Bit position for IOMUXC_GPR10_OCRAM_TZ_EN.
#define BM_IOMUXC_GPR10_OCRAM_TZ_EN      (0x00000010)  //!< Bit mask for IOMUXC_GPR10_OCRAM_TZ_EN.

//! @brief Get value of IOMUXC_GPR10_OCRAM_TZ_EN from a register value.
#define BG_IOMUXC_GPR10_OCRAM_TZ_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_OCRAM_TZ_EN) >> BP_IOMUXC_GPR10_OCRAM_TZ_EN)

//! @brief Format value for bitfield IOMUXC_GPR10_OCRAM_TZ_EN.
#define BF_IOMUXC_GPR10_OCRAM_TZ_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_OCRAM_TZ_EN) & BM_IOMUXC_GPR10_OCRAM_TZ_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the OCRAM_TZ_EN field to a new value.
#define BW_IOMUXC_GPR10_OCRAM_TZ_EN(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_OCRAM_TZ_EN) | BF_IOMUXC_GPR10_OCRAM_TZ_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field OCRAM_TZ_ADDR[10:5] (RW)
 *
 * OCRAM TrustZone (TZ) start address. This is the start address of the secure memory region within
 * the OCRAM memory space is 4KB granularity. The start address affects the OCRAM transactions only
 * if OCRAM_TZ_EN bit is set. The OCRAM TZ ENDADDR is not configurable and is set to the end of
 * OCRAM memory space.
 */
//@{
#define BP_IOMUXC_GPR10_OCRAM_TZ_ADDR      (5)      //!< Bit position for IOMUXC_GPR10_OCRAM_TZ_ADDR.
#define BM_IOMUXC_GPR10_OCRAM_TZ_ADDR      (0x000007e0)  //!< Bit mask for IOMUXC_GPR10_OCRAM_TZ_ADDR.

//! @brief Get value of IOMUXC_GPR10_OCRAM_TZ_ADDR from a register value.
#define BG_IOMUXC_GPR10_OCRAM_TZ_ADDR(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_OCRAM_TZ_ADDR) >> BP_IOMUXC_GPR10_OCRAM_TZ_ADDR)

//! @brief Format value for bitfield IOMUXC_GPR10_OCRAM_TZ_ADDR.
#define BF_IOMUXC_GPR10_OCRAM_TZ_ADDR(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_OCRAM_TZ_ADDR) & BM_IOMUXC_GPR10_OCRAM_TZ_ADDR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the OCRAM_TZ_ADDR field to a new value.
#define BW_IOMUXC_GPR10_OCRAM_TZ_ADDR(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_OCRAM_TZ_ADDR) | BF_IOMUXC_GPR10_OCRAM_TZ_ADDR(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field SEC_ERR_RESP[11] (RW)
 *
 * Security error response enable for all security gaskets (on both AHB and AXI busses)
 *
 * Values:
 * - 0 - OKEY response
 * - 1 - SLVError (default)
 */
//@{
#define BP_IOMUXC_GPR10_SEC_ERR_RESP      (11)      //!< Bit position for IOMUXC_GPR10_SEC_ERR_RESP.
#define BM_IOMUXC_GPR10_SEC_ERR_RESP      (0x00000800)  //!< Bit mask for IOMUXC_GPR10_SEC_ERR_RESP.

//! @brief Get value of IOMUXC_GPR10_SEC_ERR_RESP from a register value.
#define BG_IOMUXC_GPR10_SEC_ERR_RESP(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_SEC_ERR_RESP) >> BP_IOMUXC_GPR10_SEC_ERR_RESP)

//! @brief Format value for bitfield IOMUXC_GPR10_SEC_ERR_RESP.
#define BF_IOMUXC_GPR10_SEC_ERR_RESP(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_SEC_ERR_RESP) & BM_IOMUXC_GPR10_SEC_ERR_RESP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SEC_ERR_RESP field to a new value.
#define BW_IOMUXC_GPR10_SEC_ERR_RESP(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_SEC_ERR_RESP) | BF_IOMUXC_GPR10_SEC_ERR_RESP(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field DBG_CLK_EN[12] (RW)
 *
 * ARM Debug clock enable
 *
 * Values:
 * - 0 - Debug turned off.
 * - 1 - Debug enabled (default).
 */
//@{
#define BP_IOMUXC_GPR10_DBG_CLK_EN      (12)      //!< Bit position for IOMUXC_GPR10_DBG_CLK_EN.
#define BM_IOMUXC_GPR10_DBG_CLK_EN      (0x00001000)  //!< Bit mask for IOMUXC_GPR10_DBG_CLK_EN.

//! @brief Get value of IOMUXC_GPR10_DBG_CLK_EN from a register value.
#define BG_IOMUXC_GPR10_DBG_CLK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_DBG_CLK_EN) >> BP_IOMUXC_GPR10_DBG_CLK_EN)

//! @brief Format value for bitfield IOMUXC_GPR10_DBG_CLK_EN.
#define BF_IOMUXC_GPR10_DBG_CLK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_DBG_CLK_EN) & BM_IOMUXC_GPR10_DBG_CLK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DBG_CLK_EN field to a new value.
#define BW_IOMUXC_GPR10_DBG_CLK_EN(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_DBG_CLK_EN) | BF_IOMUXC_GPR10_DBG_CLK_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field DBG_EN[13] (RW)
 *
 * ARM non secure (non-invasive) debug enable
 *
 * Values:
 * - 0 - Debug turned off.
 * - 1 - Debug enabled (default).
 */
//@{
#define BP_IOMUXC_GPR10_DBG_EN      (13)      //!< Bit position for IOMUXC_GPR10_DBG_EN.
#define BM_IOMUXC_GPR10_DBG_EN      (0x00002000)  //!< Bit mask for IOMUXC_GPR10_DBG_EN.

//! @brief Get value of IOMUXC_GPR10_DBG_EN from a register value.
#define BG_IOMUXC_GPR10_DBG_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_DBG_EN) >> BP_IOMUXC_GPR10_DBG_EN)

//! @brief Format value for bitfield IOMUXC_GPR10_DBG_EN.
#define BF_IOMUXC_GPR10_DBG_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_DBG_EN) & BM_IOMUXC_GPR10_DBG_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DBG_EN field to a new value.
#define BW_IOMUXC_GPR10_DBG_EN(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_DBG_EN) | BF_IOMUXC_GPR10_DBG_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field LOCK_DCIC1_MUX_CTL[17:16] (RW)
 *
 * Lock DCIC1_MUX_CTL field for changes. This is a sticky field, once set it can't be cleared (only
 * by reset).
 *
 * Values:
 * - 0 - Field is not locked
 * - 1 - Field is locked (read access only)
 */
//@{
#define BP_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL      (16)      //!< Bit position for IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL.
#define BM_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL      (0x00030000)  //!< Bit mask for IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL.

//! @brief Get value of IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL from a register value.
#define BG_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL) >> BP_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL)

//! @brief Format value for bitfield IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL.
#define BF_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL) & BM_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LOCK_DCIC1_MUX_CTL field to a new value.
#define BW_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL) | BF_IOMUXC_GPR10_LOCK_DCIC1_MUX_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field LOCK_DCIC2_MUX_CTL[19:18] (RW)
 *
 * Lock DCIC2_MUX_CTL field for changes. This is a sticky field, once set it can't be cleared (only
 * by reset).
 *
 * Values:
 * - 0 - Field is not locked
 * - 1 - Field is locked (read access only)
 */
//@{
#define BP_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL      (18)      //!< Bit position for IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL.
#define BM_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL      (0x000c0000)  //!< Bit mask for IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL.

//! @brief Get value of IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL from a register value.
#define BG_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL) >> BP_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL)

//! @brief Format value for bitfield IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL.
#define BF_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL) & BM_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LOCK_DCIC2_MUX_CTL field to a new value.
#define BW_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL) | BF_IOMUXC_GPR10_LOCK_DCIC2_MUX_CTL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field LOCK_OCRAM_TZ_EN[20] (RW)
 *
 * Lock OCRAM_TZ_EN field for changes. This is a sticky field, once set it can't be cleared (only by
 * reset).
 *
 * Values:
 * - 0 - Field is not locked
 * - 1 - Field is locked (read access only)
 */
//@{
#define BP_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN      (20)      //!< Bit position for IOMUXC_GPR10_LOCK_OCRAM_TZ_EN.
#define BM_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN      (0x00100000)  //!< Bit mask for IOMUXC_GPR10_LOCK_OCRAM_TZ_EN.

//! @brief Get value of IOMUXC_GPR10_LOCK_OCRAM_TZ_EN from a register value.
#define BG_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN) >> BP_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN)

//! @brief Format value for bitfield IOMUXC_GPR10_LOCK_OCRAM_TZ_EN.
#define BF_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN) & BM_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LOCK_OCRAM_TZ_EN field to a new value.
#define BW_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN) | BF_IOMUXC_GPR10_LOCK_OCRAM_TZ_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field LOCK_OCRAM_TZ_ADDR[26:21] (RW)
 *
 * Lock OCRAM_TZ_ADDR field for changes. This is a sticky field, once set it can't be cleared (only
 * by reset).
 *
 * Values:
 * - 0 - Field is not locked
 * - 1 - Field is locked (read access only)
 */
//@{
#define BP_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR      (21)      //!< Bit position for IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR.
#define BM_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR      (0x07e00000)  //!< Bit mask for IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR.

//! @brief Get value of IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR from a register value.
#define BG_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR) >> BP_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR)

//! @brief Format value for bitfield IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR.
#define BF_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR) & BM_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LOCK_OCRAM_TZ_ADDR field to a new value.
#define BW_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR) | BF_IOMUXC_GPR10_LOCK_OCRAM_TZ_ADDR(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field LOCK_SEC_ERR_RESP[27] (RW)
 *
 * Lock SEC_ERR_RESP field for changes. This is a sticky field, once set it can't be cleared (only
 * by reset).
 *
 * Values:
 * - 0 - Field is not locked
 * - 1 - Field is locked (read access only)
 */
//@{
#define BP_IOMUXC_GPR10_LOCK_SEC_ERR_RESP      (27)      //!< Bit position for IOMUXC_GPR10_LOCK_SEC_ERR_RESP.
#define BM_IOMUXC_GPR10_LOCK_SEC_ERR_RESP      (0x08000000)  //!< Bit mask for IOMUXC_GPR10_LOCK_SEC_ERR_RESP.

//! @brief Get value of IOMUXC_GPR10_LOCK_SEC_ERR_RESP from a register value.
#define BG_IOMUXC_GPR10_LOCK_SEC_ERR_RESP(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_LOCK_SEC_ERR_RESP) >> BP_IOMUXC_GPR10_LOCK_SEC_ERR_RESP)

//! @brief Format value for bitfield IOMUXC_GPR10_LOCK_SEC_ERR_RESP.
#define BF_IOMUXC_GPR10_LOCK_SEC_ERR_RESP(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_LOCK_SEC_ERR_RESP) & BM_IOMUXC_GPR10_LOCK_SEC_ERR_RESP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LOCK_SEC_ERR_RESP field to a new value.
#define BW_IOMUXC_GPR10_LOCK_SEC_ERR_RESP(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_LOCK_SEC_ERR_RESP) | BF_IOMUXC_GPR10_LOCK_SEC_ERR_RESP(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field LOCK_DBG_CLK_EN[28] (RW)
 *
 * Lock DBG_CLK_EN field for changes. This is a sticky field, once set it can't be cleared (only by
 * reset).
 *
 * Values:
 * - 0 - Field is not locked
 * - 1 - Field is locked (read access only)
 */
//@{
#define BP_IOMUXC_GPR10_LOCK_DBG_CLK_EN      (28)      //!< Bit position for IOMUXC_GPR10_LOCK_DBG_CLK_EN.
#define BM_IOMUXC_GPR10_LOCK_DBG_CLK_EN      (0x10000000)  //!< Bit mask for IOMUXC_GPR10_LOCK_DBG_CLK_EN.

//! @brief Get value of IOMUXC_GPR10_LOCK_DBG_CLK_EN from a register value.
#define BG_IOMUXC_GPR10_LOCK_DBG_CLK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_LOCK_DBG_CLK_EN) >> BP_IOMUXC_GPR10_LOCK_DBG_CLK_EN)

//! @brief Format value for bitfield IOMUXC_GPR10_LOCK_DBG_CLK_EN.
#define BF_IOMUXC_GPR10_LOCK_DBG_CLK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_LOCK_DBG_CLK_EN) & BM_IOMUXC_GPR10_LOCK_DBG_CLK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LOCK_DBG_CLK_EN field to a new value.
#define BW_IOMUXC_GPR10_LOCK_DBG_CLK_EN(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_LOCK_DBG_CLK_EN) | BF_IOMUXC_GPR10_LOCK_DBG_CLK_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR10, field LOCK_DBG_EN[29] (RW)
 *
 * Lock DBG_EN field for changes. This is a sticky field, once set it can't be cleared (only by
 * reset).
 *
 * Values:
 * - 0 - Field is not locked
 * - 1 - Field is locked (read access only)
 */
//@{
#define BP_IOMUXC_GPR10_LOCK_DBG_EN      (29)      //!< Bit position for IOMUXC_GPR10_LOCK_DBG_EN.
#define BM_IOMUXC_GPR10_LOCK_DBG_EN      (0x20000000)  //!< Bit mask for IOMUXC_GPR10_LOCK_DBG_EN.

//! @brief Get value of IOMUXC_GPR10_LOCK_DBG_EN from a register value.
#define BG_IOMUXC_GPR10_LOCK_DBG_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR10_LOCK_DBG_EN) >> BP_IOMUXC_GPR10_LOCK_DBG_EN)

//! @brief Format value for bitfield IOMUXC_GPR10_LOCK_DBG_EN.
#define BF_IOMUXC_GPR10_LOCK_DBG_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR10_LOCK_DBG_EN) & BM_IOMUXC_GPR10_LOCK_DBG_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LOCK_DBG_EN field to a new value.
#define BW_IOMUXC_GPR10_LOCK_DBG_EN(v)   (HW_IOMUXC_GPR10_WR((HW_IOMUXC_GPR10_RD() & ~BM_IOMUXC_GPR10_LOCK_DBG_EN) | BF_IOMUXC_GPR10_LOCK_DBG_EN(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR11 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR11 - GPR (RW)
 *
 * Reset value: 0x00003800
 */
typedef union _hw_iomuxc_gpr11
{
    reg32_t U;
    struct _hw_iomuxc_gpr11_bitfields
    {
        unsigned RESERVED2 : 32; //!< [31:0] Reserved.
    } B;
} hw_iomuxc_gpr11_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR11 register
 */
//@{
#define HW_IOMUXC_GPR11_ADDR      (REGS_IOMUXC_BASE + 0x2c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR11           (*(volatile hw_iomuxc_gpr11_t *) HW_IOMUXC_GPR11_ADDR)
#define HW_IOMUXC_GPR11_RD()      (HW_IOMUXC_GPR11.U)
#define HW_IOMUXC_GPR11_WR(v)     (HW_IOMUXC_GPR11.U = (v))
#define HW_IOMUXC_GPR11_SET(v)    (HW_IOMUXC_GPR11_WR(HW_IOMUXC_GPR11_RD() |  (v)))
#define HW_IOMUXC_GPR11_CLR(v)    (HW_IOMUXC_GPR11_WR(HW_IOMUXC_GPR11_RD() & ~(v)))
#define HW_IOMUXC_GPR11_TOG(v)    (HW_IOMUXC_GPR11_WR(HW_IOMUXC_GPR11_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR11 bitfields
 */

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR12 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR12 - GPR (RW)
 *
 * Reset value: 0x0f000000
 */
typedef union _hw_iomuxc_gpr12
{
    reg32_t U;
    struct _hw_iomuxc_gpr12_bitfields
    {
        unsigned RESERVED0 : 2; //!< [1:0] Reserved
        unsigned USDHC_DBG_MUX : 2; //!< [3:2] uSDHC debug bus IO mux control
        unsigned LOS_LEVEL : 5; //!< [8:4] PCIe_PHY - Loss-of-Signal Detector Sensitivity Level Control Function: Sets the sensitivity level for the Loss-of-Signal detector.
        unsigned APPS_PM_XMT_PME : 1; //!< [9] PCIe_CTL - Wake Up.
        unsigned APP_LTSSM_ENABLE : 1; //!< [10] PCIe_CTL - Driven low by the application after reset to hold the LTSSM in the Detect state until the application is ready.
        unsigned APP_INIT_RST : 1; //!< [11] PCIe_CTL - Request from the application to send a Hot Reset to the downstream device.
        unsigned DEVICE_TYPE : 4; //!< [15:12] PCIe_CTL - Device/Port Type.
        unsigned APPS_PM_XMT_TURNOFF : 1; //!< [16] PCIe_CTL - Request from the application to generate a PM_Turn_Off Message.
        unsigned DIA_STATUS_BUS_SELECT : 4; //!< [20:17] PCIe_CTL - used for debug to select what part of diag_status_bus will be reflected on the 32 bits of the iomux
        unsigned PCIE_CTL_7 : 3; //!< [23:21] PCIe control of diagnostic bus select
        unsigned ARMP_APB_CLK_EN : 1; //!< [24] ARM platform APB clock enable
        unsigned ARMP_ATB_CLK_EN : 1; //!< [25] ARM platform ATB clock enable
        unsigned ARMP_AHB_CLK_EN : 1; //!< [26] ARM platform AHB clock enable
        unsigned ARMP_IPG_CLK_EN : 1; //!< [27] ARM platform IPG clock enable
        unsigned RESERVED1 : 4; //!< [31:28] Reserved
    } B;
} hw_iomuxc_gpr12_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR12 register
 */
//@{
#define HW_IOMUXC_GPR12_ADDR      (REGS_IOMUXC_BASE + 0x30)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR12           (*(volatile hw_iomuxc_gpr12_t *) HW_IOMUXC_GPR12_ADDR)
#define HW_IOMUXC_GPR12_RD()      (HW_IOMUXC_GPR12.U)
#define HW_IOMUXC_GPR12_WR(v)     (HW_IOMUXC_GPR12.U = (v))
#define HW_IOMUXC_GPR12_SET(v)    (HW_IOMUXC_GPR12_WR(HW_IOMUXC_GPR12_RD() |  (v)))
#define HW_IOMUXC_GPR12_CLR(v)    (HW_IOMUXC_GPR12_WR(HW_IOMUXC_GPR12_RD() & ~(v)))
#define HW_IOMUXC_GPR12_TOG(v)    (HW_IOMUXC_GPR12_WR(HW_IOMUXC_GPR12_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR12 bitfields
 */

/*! @name Register IOMUXC_GPR12, field USDHC_DBG_MUX[3:2] (RW)
 *
 * uSDHC debug bus IO mux control '00' - uSDHC1 debug '01' - uSDHC2 debug '10' - uSDHC3 debug '11' -
 * uSDHC4 debug
 */
//@{
#define BP_IOMUXC_GPR12_USDHC_DBG_MUX      (2)      //!< Bit position for IOMUXC_GPR12_USDHC_DBG_MUX.
#define BM_IOMUXC_GPR12_USDHC_DBG_MUX      (0x0000000c)  //!< Bit mask for IOMUXC_GPR12_USDHC_DBG_MUX.

//! @brief Get value of IOMUXC_GPR12_USDHC_DBG_MUX from a register value.
#define BG_IOMUXC_GPR12_USDHC_DBG_MUX(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_USDHC_DBG_MUX) >> BP_IOMUXC_GPR12_USDHC_DBG_MUX)

//! @brief Format value for bitfield IOMUXC_GPR12_USDHC_DBG_MUX.
#define BF_IOMUXC_GPR12_USDHC_DBG_MUX(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_USDHC_DBG_MUX) & BM_IOMUXC_GPR12_USDHC_DBG_MUX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the USDHC_DBG_MUX field to a new value.
#define BW_IOMUXC_GPR12_USDHC_DBG_MUX(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_USDHC_DBG_MUX) | BF_IOMUXC_GPR12_USDHC_DBG_MUX(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field LOS_LEVEL[8:4] (RW)
 *
 * PCIe_PHY - Loss-of-Signal Detector Sensitivity Level Control Function: Sets the sensitivity level
 * for the Loss-of-Signal detector. This signal must be set to 0x9
 */
//@{
#define BP_IOMUXC_GPR12_LOS_LEVEL      (4)      //!< Bit position for IOMUXC_GPR12_LOS_LEVEL.
#define BM_IOMUXC_GPR12_LOS_LEVEL      (0x000001f0)  //!< Bit mask for IOMUXC_GPR12_LOS_LEVEL.

//! @brief Get value of IOMUXC_GPR12_LOS_LEVEL from a register value.
#define BG_IOMUXC_GPR12_LOS_LEVEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_LOS_LEVEL) >> BP_IOMUXC_GPR12_LOS_LEVEL)

//! @brief Format value for bitfield IOMUXC_GPR12_LOS_LEVEL.
#define BF_IOMUXC_GPR12_LOS_LEVEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_LOS_LEVEL) & BM_IOMUXC_GPR12_LOS_LEVEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LOS_LEVEL field to a new value.
#define BW_IOMUXC_GPR12_LOS_LEVEL(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_LOS_LEVEL) | BF_IOMUXC_GPR12_LOS_LEVEL(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field APPS_PM_XMT_PME[9] (RW)
 *
 * PCIe_CTL - Wake Up. Used by application logic to wake up the PMC state machine from a D1, D2 or
 * D3 power state. Upon wake-up, the core sends a PM_PME Message
 */
//@{
#define BP_IOMUXC_GPR12_APPS_PM_XMT_PME      (9)      //!< Bit position for IOMUXC_GPR12_APPS_PM_XMT_PME.
#define BM_IOMUXC_GPR12_APPS_PM_XMT_PME      (0x00000200)  //!< Bit mask for IOMUXC_GPR12_APPS_PM_XMT_PME.

//! @brief Get value of IOMUXC_GPR12_APPS_PM_XMT_PME from a register value.
#define BG_IOMUXC_GPR12_APPS_PM_XMT_PME(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_APPS_PM_XMT_PME) >> BP_IOMUXC_GPR12_APPS_PM_XMT_PME)

//! @brief Format value for bitfield IOMUXC_GPR12_APPS_PM_XMT_PME.
#define BF_IOMUXC_GPR12_APPS_PM_XMT_PME(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_APPS_PM_XMT_PME) & BM_IOMUXC_GPR12_APPS_PM_XMT_PME)

#ifndef __LANGUAGE_ASM__
//! @brief Set the APPS_PM_XMT_PME field to a new value.
#define BW_IOMUXC_GPR12_APPS_PM_XMT_PME(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_APPS_PM_XMT_PME) | BF_IOMUXC_GPR12_APPS_PM_XMT_PME(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field APP_LTSSM_ENABLE[10] (RW)
 *
 * PCIe_CTL - Driven low by the application after reset to hold the LTSSM in the Detect state until
 * the application is ready. When the application has finished initializing the core configuration
 * registers, it asserts app_ltssm_enable to allow the LTSSM to continue Link establishment.
 *
 * Values:
 * - 0 - Application is not ready.
 * - 1 - Application is ready.
 */
//@{
#define BP_IOMUXC_GPR12_APP_LTSSM_ENABLE      (10)      //!< Bit position for IOMUXC_GPR12_APP_LTSSM_ENABLE.
#define BM_IOMUXC_GPR12_APP_LTSSM_ENABLE      (0x00000400)  //!< Bit mask for IOMUXC_GPR12_APP_LTSSM_ENABLE.

//! @brief Get value of IOMUXC_GPR12_APP_LTSSM_ENABLE from a register value.
#define BG_IOMUXC_GPR12_APP_LTSSM_ENABLE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_APP_LTSSM_ENABLE) >> BP_IOMUXC_GPR12_APP_LTSSM_ENABLE)

//! @brief Format value for bitfield IOMUXC_GPR12_APP_LTSSM_ENABLE.
#define BF_IOMUXC_GPR12_APP_LTSSM_ENABLE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_APP_LTSSM_ENABLE) & BM_IOMUXC_GPR12_APP_LTSSM_ENABLE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the APP_LTSSM_ENABLE field to a new value.
#define BW_IOMUXC_GPR12_APP_LTSSM_ENABLE(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_APP_LTSSM_ENABLE) | BF_IOMUXC_GPR12_APP_LTSSM_ENABLE(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field APP_INIT_RST[11] (RW)
 *
 * PCIe_CTL - Request from the application to send a Hot Reset to the downstream device.
 */
//@{
#define BP_IOMUXC_GPR12_APP_INIT_RST      (11)      //!< Bit position for IOMUXC_GPR12_APP_INIT_RST.
#define BM_IOMUXC_GPR12_APP_INIT_RST      (0x00000800)  //!< Bit mask for IOMUXC_GPR12_APP_INIT_RST.

//! @brief Get value of IOMUXC_GPR12_APP_INIT_RST from a register value.
#define BG_IOMUXC_GPR12_APP_INIT_RST(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_APP_INIT_RST) >> BP_IOMUXC_GPR12_APP_INIT_RST)

//! @brief Format value for bitfield IOMUXC_GPR12_APP_INIT_RST.
#define BF_IOMUXC_GPR12_APP_INIT_RST(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_APP_INIT_RST) & BM_IOMUXC_GPR12_APP_INIT_RST)

#ifndef __LANGUAGE_ASM__
//! @brief Set the APP_INIT_RST field to a new value.
#define BW_IOMUXC_GPR12_APP_INIT_RST(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_APP_INIT_RST) | BF_IOMUXC_GPR12_APP_INIT_RST(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field DEVICE_TYPE[15:12] (RW)
 *
 * PCIe_CTL - Device/Port Type. Indicates the specific type of this PCI Express Function (EP or RC)
 * DEVICE_TYPE field values 0011-1111 are reserved.
 *
 * Values:
 * - PCIE_EP = 0000 - EP Mode
 * - PCIE_RC = 0010 - RC Mode
 */
//@{
#define BP_IOMUXC_GPR12_DEVICE_TYPE      (12)      //!< Bit position for IOMUXC_GPR12_DEVICE_TYPE.
#define BM_IOMUXC_GPR12_DEVICE_TYPE      (0x0000f000)  //!< Bit mask for IOMUXC_GPR12_DEVICE_TYPE.

//! @brief Get value of IOMUXC_GPR12_DEVICE_TYPE from a register value.
#define BG_IOMUXC_GPR12_DEVICE_TYPE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_DEVICE_TYPE) >> BP_IOMUXC_GPR12_DEVICE_TYPE)

//! @brief Format value for bitfield IOMUXC_GPR12_DEVICE_TYPE.
#define BF_IOMUXC_GPR12_DEVICE_TYPE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_DEVICE_TYPE) & BM_IOMUXC_GPR12_DEVICE_TYPE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DEVICE_TYPE field to a new value.
#define BW_IOMUXC_GPR12_DEVICE_TYPE(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_DEVICE_TYPE) | BF_IOMUXC_GPR12_DEVICE_TYPE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_GPR12_DEVICE_TYPE_V(v) BF_IOMUXC_GPR12_DEVICE_TYPE(BV_IOMUXC_GPR12_DEVICE_TYPE__##v)

#define BV_IOMUXC_GPR12_DEVICE_TYPE__PCIE_EP (0x0) //!< EP Mode
#define BV_IOMUXC_GPR12_DEVICE_TYPE__PCIE_RC (0x2) //!< RC Mode
//@}

/*! @name Register IOMUXC_GPR12, field APPS_PM_XMT_TURNOFF[16] (RW)
 *
 * PCIe_CTL - Request from the application to generate a PM_Turn_Off Message.
 */
//@{
#define BP_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF      (16)      //!< Bit position for IOMUXC_GPR12_APPS_PM_XMT_TURNOFF.
#define BM_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF      (0x00010000)  //!< Bit mask for IOMUXC_GPR12_APPS_PM_XMT_TURNOFF.

//! @brief Get value of IOMUXC_GPR12_APPS_PM_XMT_TURNOFF from a register value.
#define BG_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF) >> BP_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF)

//! @brief Format value for bitfield IOMUXC_GPR12_APPS_PM_XMT_TURNOFF.
#define BF_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF) & BM_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF)

#ifndef __LANGUAGE_ASM__
//! @brief Set the APPS_PM_XMT_TURNOFF field to a new value.
#define BW_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF) | BF_IOMUXC_GPR12_APPS_PM_XMT_TURNOFF(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field DIA_STATUS_BUS_SELECT[20:17] (RW)
 *
 * PCIe_CTL - used for debug to select what part of diag_status_bus will be reflected on the 32 bits
 * of the iomux
 */
//@{
#define BP_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT      (17)      //!< Bit position for IOMUXC_GPR12_DIA_STATUS_BUS_SELECT.
#define BM_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT      (0x001e0000)  //!< Bit mask for IOMUXC_GPR12_DIA_STATUS_BUS_SELECT.

//! @brief Get value of IOMUXC_GPR12_DIA_STATUS_BUS_SELECT from a register value.
#define BG_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT) >> BP_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT)

//! @brief Format value for bitfield IOMUXC_GPR12_DIA_STATUS_BUS_SELECT.
#define BF_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT) & BM_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DIA_STATUS_BUS_SELECT field to a new value.
#define BW_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT) | BF_IOMUXC_GPR12_DIA_STATUS_BUS_SELECT(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field PCIE_CTL_7[23:21] (RW)
 *
 * PCIe control of diagnostic bus select (Drive 'cxpl_diag_ctrl' PCI controller input)
 */
//@{
#define BP_IOMUXC_GPR12_PCIE_CTL_7      (21)      //!< Bit position for IOMUXC_GPR12_PCIE_CTL_7.
#define BM_IOMUXC_GPR12_PCIE_CTL_7      (0x00e00000)  //!< Bit mask for IOMUXC_GPR12_PCIE_CTL_7.

//! @brief Get value of IOMUXC_GPR12_PCIE_CTL_7 from a register value.
#define BG_IOMUXC_GPR12_PCIE_CTL_7(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_PCIE_CTL_7) >> BP_IOMUXC_GPR12_PCIE_CTL_7)

//! @brief Format value for bitfield IOMUXC_GPR12_PCIE_CTL_7.
#define BF_IOMUXC_GPR12_PCIE_CTL_7(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_PCIE_CTL_7) & BM_IOMUXC_GPR12_PCIE_CTL_7)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PCIE_CTL_7 field to a new value.
#define BW_IOMUXC_GPR12_PCIE_CTL_7(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_PCIE_CTL_7) | BF_IOMUXC_GPR12_PCIE_CTL_7(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field ARMP_APB_CLK_EN[24] (RW)
 *
 * ARM platform APB clock enable
 *
 * Values:
 * - 0 - IPG clock is not running (gated).
 * - 1 - IPG clock is running (enabled).
 */
//@{
#define BP_IOMUXC_GPR12_ARMP_APB_CLK_EN      (24)      //!< Bit position for IOMUXC_GPR12_ARMP_APB_CLK_EN.
#define BM_IOMUXC_GPR12_ARMP_APB_CLK_EN      (0x01000000)  //!< Bit mask for IOMUXC_GPR12_ARMP_APB_CLK_EN.

//! @brief Get value of IOMUXC_GPR12_ARMP_APB_CLK_EN from a register value.
#define BG_IOMUXC_GPR12_ARMP_APB_CLK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_ARMP_APB_CLK_EN) >> BP_IOMUXC_GPR12_ARMP_APB_CLK_EN)

//! @brief Format value for bitfield IOMUXC_GPR12_ARMP_APB_CLK_EN.
#define BF_IOMUXC_GPR12_ARMP_APB_CLK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_ARMP_APB_CLK_EN) & BM_IOMUXC_GPR12_ARMP_APB_CLK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ARMP_APB_CLK_EN field to a new value.
#define BW_IOMUXC_GPR12_ARMP_APB_CLK_EN(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_ARMP_APB_CLK_EN) | BF_IOMUXC_GPR12_ARMP_APB_CLK_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field ARMP_ATB_CLK_EN[25] (RW)
 *
 * ARM platform ATB clock enable
 *
 * Values:
 * - 0 - IPG clock is not running (gated).
 * - 1 - IPG clock is running (enabled).
 */
//@{
#define BP_IOMUXC_GPR12_ARMP_ATB_CLK_EN      (25)      //!< Bit position for IOMUXC_GPR12_ARMP_ATB_CLK_EN.
#define BM_IOMUXC_GPR12_ARMP_ATB_CLK_EN      (0x02000000)  //!< Bit mask for IOMUXC_GPR12_ARMP_ATB_CLK_EN.

//! @brief Get value of IOMUXC_GPR12_ARMP_ATB_CLK_EN from a register value.
#define BG_IOMUXC_GPR12_ARMP_ATB_CLK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_ARMP_ATB_CLK_EN) >> BP_IOMUXC_GPR12_ARMP_ATB_CLK_EN)

//! @brief Format value for bitfield IOMUXC_GPR12_ARMP_ATB_CLK_EN.
#define BF_IOMUXC_GPR12_ARMP_ATB_CLK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_ARMP_ATB_CLK_EN) & BM_IOMUXC_GPR12_ARMP_ATB_CLK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ARMP_ATB_CLK_EN field to a new value.
#define BW_IOMUXC_GPR12_ARMP_ATB_CLK_EN(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_ARMP_ATB_CLK_EN) | BF_IOMUXC_GPR12_ARMP_ATB_CLK_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field ARMP_AHB_CLK_EN[26] (RW)
 *
 * ARM platform AHB clock enable
 *
 * Values:
 * - 0 - IPG clock is not running (gated).
 * - 1 - IPG clock is running (enabled).
 */
//@{
#define BP_IOMUXC_GPR12_ARMP_AHB_CLK_EN      (26)      //!< Bit position for IOMUXC_GPR12_ARMP_AHB_CLK_EN.
#define BM_IOMUXC_GPR12_ARMP_AHB_CLK_EN      (0x04000000)  //!< Bit mask for IOMUXC_GPR12_ARMP_AHB_CLK_EN.

//! @brief Get value of IOMUXC_GPR12_ARMP_AHB_CLK_EN from a register value.
#define BG_IOMUXC_GPR12_ARMP_AHB_CLK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_ARMP_AHB_CLK_EN) >> BP_IOMUXC_GPR12_ARMP_AHB_CLK_EN)

//! @brief Format value for bitfield IOMUXC_GPR12_ARMP_AHB_CLK_EN.
#define BF_IOMUXC_GPR12_ARMP_AHB_CLK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_ARMP_AHB_CLK_EN) & BM_IOMUXC_GPR12_ARMP_AHB_CLK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ARMP_AHB_CLK_EN field to a new value.
#define BW_IOMUXC_GPR12_ARMP_AHB_CLK_EN(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_ARMP_AHB_CLK_EN) | BF_IOMUXC_GPR12_ARMP_AHB_CLK_EN(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR12, field ARMP_IPG_CLK_EN[27] (RW)
 *
 * ARM platform IPG clock enable
 *
 * Values:
 * - 0 - IPG clock is not running (gated).
 * - 1 - IPG clock is running (enabled).
 */
//@{
#define BP_IOMUXC_GPR12_ARMP_IPG_CLK_EN      (27)      //!< Bit position for IOMUXC_GPR12_ARMP_IPG_CLK_EN.
#define BM_IOMUXC_GPR12_ARMP_IPG_CLK_EN      (0x08000000)  //!< Bit mask for IOMUXC_GPR12_ARMP_IPG_CLK_EN.

//! @brief Get value of IOMUXC_GPR12_ARMP_IPG_CLK_EN from a register value.
#define BG_IOMUXC_GPR12_ARMP_IPG_CLK_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR12_ARMP_IPG_CLK_EN) >> BP_IOMUXC_GPR12_ARMP_IPG_CLK_EN)

//! @brief Format value for bitfield IOMUXC_GPR12_ARMP_IPG_CLK_EN.
#define BF_IOMUXC_GPR12_ARMP_IPG_CLK_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR12_ARMP_IPG_CLK_EN) & BM_IOMUXC_GPR12_ARMP_IPG_CLK_EN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ARMP_IPG_CLK_EN field to a new value.
#define BW_IOMUXC_GPR12_ARMP_IPG_CLK_EN(v)   (HW_IOMUXC_GPR12_WR((HW_IOMUXC_GPR12_RD() & ~BM_IOMUXC_GPR12_ARMP_IPG_CLK_EN) | BF_IOMUXC_GPR12_ARMP_IPG_CLK_EN(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_GPR13 - GPR
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_GPR13 - GPR (RW)
 *
 * Reset value: 0x059124c4
 *
 * SATA_PHY_6 PHUG FRUG fast_startup Frequency Tolerance (ppm) 000 1 1 None 780 001 2 2 None 780 010
 * 1 4 None 6,250 011 2 4 None 6,250 1xx Reserved
 */
typedef union _hw_iomuxc_gpr13
{
    reg32_t U;
    struct _hw_iomuxc_gpr13_bitfields
    {
        unsigned SATA_PHY_1 : 2; //!< [1:0] SATA PHY - Tx Edge rate control enables the SATA PHY to meet the edge rate requirements for all SATA variants
        unsigned SATA_PHY_2 : 5; //!< [6:2] SATA PHY - Transmit level settings.
        unsigned SATA_PHY_3 : 4; //!< [10:7] SATA PHY Tx -Transmit Boost Control, ratio of drive level of transmission bit to non transmission bit.
        unsigned SATA_PHY_4 : 3; //!< [13:11] SATA PHY -Transmit Attenuation control, provides discrete driver attenuation factors (from full driver level).
        unsigned SATA_PHY_5 : 1; //!< [14] SATA PHY - Spread Spectrum Enable.
        unsigned SATA_SPEED : 1; //!< [15] Indicates SATA PHY speed mode
        unsigned SATA_PHY_6 : 3; //!< [18:16] SATA PHY Rx - DPLL mode control, sets phase and frequency gain of receiver DPLL
        unsigned SATA_PHY_7 : 5; //!< [23:19] SATA PHY Rx - Loss of signal detector level.
        unsigned SATA_PHY_8 : 3; //!< [26:24] SATA _PHY Rx - Receiver Equalization control
        unsigned ENET_STOP_REQ : 1; //!< [27] ENET stop request
        unsigned CAN1_STOP_REQ : 1; //!< [28] CAN1 stop request
        unsigned CAN2_STOP_REQ : 1; //!< [29] CAN2 stop request
        unsigned SDMA_STOP_REQ : 1; //!< [30] SDMA stop request
        unsigned RESERVED0 : 1; //!< [31] Reserved
    } B;
} hw_iomuxc_gpr13_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_GPR13 register
 */
//@{
#define HW_IOMUXC_GPR13_ADDR      (REGS_IOMUXC_BASE + 0x34)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_GPR13           (*(volatile hw_iomuxc_gpr13_t *) HW_IOMUXC_GPR13_ADDR)
#define HW_IOMUXC_GPR13_RD()      (HW_IOMUXC_GPR13.U)
#define HW_IOMUXC_GPR13_WR(v)     (HW_IOMUXC_GPR13.U = (v))
#define HW_IOMUXC_GPR13_SET(v)    (HW_IOMUXC_GPR13_WR(HW_IOMUXC_GPR13_RD() |  (v)))
#define HW_IOMUXC_GPR13_CLR(v)    (HW_IOMUXC_GPR13_WR(HW_IOMUXC_GPR13_RD() & ~(v)))
#define HW_IOMUXC_GPR13_TOG(v)    (HW_IOMUXC_GPR13_WR(HW_IOMUXC_GPR13_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_GPR13 bitfields
 */

/*! @name Register IOMUXC_GPR13, field SATA_PHY_1[1:0] (RW)
 *
 * SATA PHY - Tx Edge rate control enables the SATA PHY to meet the edge rate requirements for all
 * SATA variants
 *
 * Values:
 * - 00 - Fast edge rate
 * - 01 - Medium edge rate
 * - 10 - Slow edge rate
 * - 11 - Reserved
 */
//@{
#define BP_IOMUXC_GPR13_SATA_PHY_1      (0)      //!< Bit position for IOMUXC_GPR13_SATA_PHY_1.
#define BM_IOMUXC_GPR13_SATA_PHY_1      (0x00000003)  //!< Bit mask for IOMUXC_GPR13_SATA_PHY_1.

//! @brief Get value of IOMUXC_GPR13_SATA_PHY_1 from a register value.
#define BG_IOMUXC_GPR13_SATA_PHY_1(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SATA_PHY_1) >> BP_IOMUXC_GPR13_SATA_PHY_1)

//! @brief Format value for bitfield IOMUXC_GPR13_SATA_PHY_1.
#define BF_IOMUXC_GPR13_SATA_PHY_1(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SATA_PHY_1) & BM_IOMUXC_GPR13_SATA_PHY_1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SATA_PHY_1 field to a new value.
#define BW_IOMUXC_GPR13_SATA_PHY_1(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SATA_PHY_1) | BF_IOMUXC_GPR13_SATA_PHY_1(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field SATA_PHY_2[6:2] (RW)
 *
 * SATA PHY - Transmit level settings. Fine resolution settings of transmit signal level, common to
 * all lanes connected to one clock module.
 *
 * Values:
 * - 00000 - 0.937 V
 * - 00001 - 0.947 V
 * - 00010 - 0.957 V
 * - 00011 - 0.966 V
 * - 00100 - 0.976 V
 * - 00101 - 0.986 V
 * - 00110 - 0.996 V
 * - 00111 - 1.005 V
 * - 01000 - 1.015 V
 * - 01001 - 1.025 V
 * - 01010 - 1.035 V
 * - 01011 - 1.045 V
 * - 01100 - 1.054 V
 * - 01101 - 1.064 V
 * - 01110 - 1.074 V
 * - 01111 - 1.084 V
 * - 10000 - 1.094 V
 * - 10001 - 1.104 V (default)
 * - 10010 - 1.113 V
 * - 10011 - 1.123 V
 * - 10100 - 1.133 V
 * - 10101 - 1.143 V
 * - 10110 - 1.152 V
 * - 10111 - 1.162 V
 * - 11000 - 1.172 V
 * - 11001 - 1.182 V
 * - 11010 - 1.191 V
 * - 11011 - 1.201 V
 * - 11100 - 1.211 V
 * - 11101 - 1.221 V
 * - 11110 - 1.230 V
 * - 11111 - 1.240 V
 */
//@{
#define BP_IOMUXC_GPR13_SATA_PHY_2      (2)      //!< Bit position for IOMUXC_GPR13_SATA_PHY_2.
#define BM_IOMUXC_GPR13_SATA_PHY_2      (0x0000007c)  //!< Bit mask for IOMUXC_GPR13_SATA_PHY_2.

//! @brief Get value of IOMUXC_GPR13_SATA_PHY_2 from a register value.
#define BG_IOMUXC_GPR13_SATA_PHY_2(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SATA_PHY_2) >> BP_IOMUXC_GPR13_SATA_PHY_2)

//! @brief Format value for bitfield IOMUXC_GPR13_SATA_PHY_2.
#define BF_IOMUXC_GPR13_SATA_PHY_2(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SATA_PHY_2) & BM_IOMUXC_GPR13_SATA_PHY_2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SATA_PHY_2 field to a new value.
#define BW_IOMUXC_GPR13_SATA_PHY_2(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SATA_PHY_2) | BF_IOMUXC_GPR13_SATA_PHY_2(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field SATA_PHY_3[10:7] (RW)
 *
 * SATA PHY Tx -Transmit Boost Control, ratio of drive level of transmission bit to non transmission
 * bit.
 *
 * Values:
 * - 0000 - 0dB
 * - 0001 - 0.37 dB
 * - 0010 - 0.74 dB
 * - 0011 - 1.11 dB
 * - 0100 - 1.48 dB
 * - 0101 - 1.85 dB
 * - 0110 - 2.22 dB
 * - 0111 - 2.59 dB
 * - 1000 - 2.96 dB
 * - 1001 - 3.33 dB (default)
 * - 1010 - 3.70 dB
 * - 1011 - 4.07 dB
 * - 1100 - 4.44 dB
 * - 1101 - 4.81 dB
 * - 1110 - 5.28 dB
 * - 1111 - 5.75 dB
 */
//@{
#define BP_IOMUXC_GPR13_SATA_PHY_3      (7)      //!< Bit position for IOMUXC_GPR13_SATA_PHY_3.
#define BM_IOMUXC_GPR13_SATA_PHY_3      (0x00000780)  //!< Bit mask for IOMUXC_GPR13_SATA_PHY_3.

//! @brief Get value of IOMUXC_GPR13_SATA_PHY_3 from a register value.
#define BG_IOMUXC_GPR13_SATA_PHY_3(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SATA_PHY_3) >> BP_IOMUXC_GPR13_SATA_PHY_3)

//! @brief Format value for bitfield IOMUXC_GPR13_SATA_PHY_3.
#define BF_IOMUXC_GPR13_SATA_PHY_3(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SATA_PHY_3) & BM_IOMUXC_GPR13_SATA_PHY_3)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SATA_PHY_3 field to a new value.
#define BW_IOMUXC_GPR13_SATA_PHY_3(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SATA_PHY_3) | BF_IOMUXC_GPR13_SATA_PHY_3(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field SATA_PHY_4[13:11] (RW)
 *
 * SATA PHY -Transmit Attenuation control, provides discrete driver attenuation factors (from full
 * driver level).
 *
 * Values:
 * - 000 - 16/16
 * - 001 - 14/16
 * - 010 - 12/16
 * - 011 - 10/16
 * - 100 - 9/16 (default)
 * - 101 - 8/16
 * - 110 - Reserved
 * - 111 - Reserved
 */
//@{
#define BP_IOMUXC_GPR13_SATA_PHY_4      (11)      //!< Bit position for IOMUXC_GPR13_SATA_PHY_4.
#define BM_IOMUXC_GPR13_SATA_PHY_4      (0x00003800)  //!< Bit mask for IOMUXC_GPR13_SATA_PHY_4.

//! @brief Get value of IOMUXC_GPR13_SATA_PHY_4 from a register value.
#define BG_IOMUXC_GPR13_SATA_PHY_4(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SATA_PHY_4) >> BP_IOMUXC_GPR13_SATA_PHY_4)

//! @brief Format value for bitfield IOMUXC_GPR13_SATA_PHY_4.
#define BF_IOMUXC_GPR13_SATA_PHY_4(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SATA_PHY_4) & BM_IOMUXC_GPR13_SATA_PHY_4)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SATA_PHY_4 field to a new value.
#define BW_IOMUXC_GPR13_SATA_PHY_4(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SATA_PHY_4) | BF_IOMUXC_GPR13_SATA_PHY_4(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field SATA_PHY_5[14] (RW)
 *
 * SATA PHY - Spread Spectrum Enable. Enables spead spectrum clock production. If the applied RefClk
 * is already spread spectrum, this bit must be deasserted.
 *
 * Values:
 * - 0 - Spread Spectrum disabled
 * - 1 - Spread spectrum enabled
 */
//@{
#define BP_IOMUXC_GPR13_SATA_PHY_5      (14)      //!< Bit position for IOMUXC_GPR13_SATA_PHY_5.
#define BM_IOMUXC_GPR13_SATA_PHY_5      (0x00004000)  //!< Bit mask for IOMUXC_GPR13_SATA_PHY_5.

//! @brief Get value of IOMUXC_GPR13_SATA_PHY_5 from a register value.
#define BG_IOMUXC_GPR13_SATA_PHY_5(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SATA_PHY_5) >> BP_IOMUXC_GPR13_SATA_PHY_5)

//! @brief Format value for bitfield IOMUXC_GPR13_SATA_PHY_5.
#define BF_IOMUXC_GPR13_SATA_PHY_5(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SATA_PHY_5) & BM_IOMUXC_GPR13_SATA_PHY_5)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SATA_PHY_5 field to a new value.
#define BW_IOMUXC_GPR13_SATA_PHY_5(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SATA_PHY_5) | BF_IOMUXC_GPR13_SATA_PHY_5(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field SATA_SPEED[15] (RW)
 *
 * Indicates SATA PHY speed mode
 *
 * Values:
 * - 0 - 1.5 GHz
 * - 1 - 3.0 GHz
 */
//@{
#define BP_IOMUXC_GPR13_SATA_SPEED      (15)      //!< Bit position for IOMUXC_GPR13_SATA_SPEED.
#define BM_IOMUXC_GPR13_SATA_SPEED      (0x00008000)  //!< Bit mask for IOMUXC_GPR13_SATA_SPEED.

//! @brief Get value of IOMUXC_GPR13_SATA_SPEED from a register value.
#define BG_IOMUXC_GPR13_SATA_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SATA_SPEED) >> BP_IOMUXC_GPR13_SATA_SPEED)

//! @brief Format value for bitfield IOMUXC_GPR13_SATA_SPEED.
#define BF_IOMUXC_GPR13_SATA_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SATA_SPEED) & BM_IOMUXC_GPR13_SATA_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SATA_SPEED field to a new value.
#define BW_IOMUXC_GPR13_SATA_SPEED(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SATA_SPEED) | BF_IOMUXC_GPR13_SATA_SPEED(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field SATA_PHY_6[18:16] (RW)
 *
 * SATA PHY Rx - DPLL mode control, sets phase and frequency gain of receiver DPLL For bits encoding
 * see below.
 */
//@{
#define BP_IOMUXC_GPR13_SATA_PHY_6      (16)      //!< Bit position for IOMUXC_GPR13_SATA_PHY_6.
#define BM_IOMUXC_GPR13_SATA_PHY_6      (0x00070000)  //!< Bit mask for IOMUXC_GPR13_SATA_PHY_6.

//! @brief Get value of IOMUXC_GPR13_SATA_PHY_6 from a register value.
#define BG_IOMUXC_GPR13_SATA_PHY_6(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SATA_PHY_6) >> BP_IOMUXC_GPR13_SATA_PHY_6)

//! @brief Format value for bitfield IOMUXC_GPR13_SATA_PHY_6.
#define BF_IOMUXC_GPR13_SATA_PHY_6(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SATA_PHY_6) & BM_IOMUXC_GPR13_SATA_PHY_6)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SATA_PHY_6 field to a new value.
#define BW_IOMUXC_GPR13_SATA_PHY_6(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SATA_PHY_6) | BF_IOMUXC_GPR13_SATA_PHY_6(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field SATA_PHY_7[23:19] (RW)
 *
 * SATA PHY Rx - Loss of signal detector level. Below the recommended value are shown
 *
 * Values:
 * - 10000 - SATA1i
 * - 10000 - SATA1m
 * - 10010 - SATA2i
 * - 10010 - (default) SATA2m
 * - 11010 - SATA1x
 * - 11010 - SATA2x
 */
//@{
#define BP_IOMUXC_GPR13_SATA_PHY_7      (19)      //!< Bit position for IOMUXC_GPR13_SATA_PHY_7.
#define BM_IOMUXC_GPR13_SATA_PHY_7      (0x00f80000)  //!< Bit mask for IOMUXC_GPR13_SATA_PHY_7.

//! @brief Get value of IOMUXC_GPR13_SATA_PHY_7 from a register value.
#define BG_IOMUXC_GPR13_SATA_PHY_7(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SATA_PHY_7) >> BP_IOMUXC_GPR13_SATA_PHY_7)

//! @brief Format value for bitfield IOMUXC_GPR13_SATA_PHY_7.
#define BF_IOMUXC_GPR13_SATA_PHY_7(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SATA_PHY_7) & BM_IOMUXC_GPR13_SATA_PHY_7)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SATA_PHY_7 field to a new value.
#define BW_IOMUXC_GPR13_SATA_PHY_7(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SATA_PHY_7) | BF_IOMUXC_GPR13_SATA_PHY_7(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field SATA_PHY_8[26:24] (RW)
 *
 * SATA _PHY Rx - Receiver Equalization control
 *
 * Values:
 * - 000 - 0.5 dB
 * - 001 - 1.0 dB
 * - 010 - 1.5 dB
 * - 011 - 2.0 dB
 * - 100 - 2.5 dB
 * - 101 - 3.0 dB (default)
 * - 110 - 3.5 dB
 * - 111 - 4.0 dB
 */
//@{
#define BP_IOMUXC_GPR13_SATA_PHY_8      (24)      //!< Bit position for IOMUXC_GPR13_SATA_PHY_8.
#define BM_IOMUXC_GPR13_SATA_PHY_8      (0x07000000)  //!< Bit mask for IOMUXC_GPR13_SATA_PHY_8.

//! @brief Get value of IOMUXC_GPR13_SATA_PHY_8 from a register value.
#define BG_IOMUXC_GPR13_SATA_PHY_8(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SATA_PHY_8) >> BP_IOMUXC_GPR13_SATA_PHY_8)

//! @brief Format value for bitfield IOMUXC_GPR13_SATA_PHY_8.
#define BF_IOMUXC_GPR13_SATA_PHY_8(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SATA_PHY_8) & BM_IOMUXC_GPR13_SATA_PHY_8)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SATA_PHY_8 field to a new value.
#define BW_IOMUXC_GPR13_SATA_PHY_8(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SATA_PHY_8) | BF_IOMUXC_GPR13_SATA_PHY_8(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field ENET_STOP_REQ[27] (RW)
 *
 * ENET stop request
 *
 * Values:
 * - 0 - Stop request off.
 * - 1 - Stop request on.
 */
//@{
#define BP_IOMUXC_GPR13_ENET_STOP_REQ      (27)      //!< Bit position for IOMUXC_GPR13_ENET_STOP_REQ.
#define BM_IOMUXC_GPR13_ENET_STOP_REQ      (0x08000000)  //!< Bit mask for IOMUXC_GPR13_ENET_STOP_REQ.

//! @brief Get value of IOMUXC_GPR13_ENET_STOP_REQ from a register value.
#define BG_IOMUXC_GPR13_ENET_STOP_REQ(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_ENET_STOP_REQ) >> BP_IOMUXC_GPR13_ENET_STOP_REQ)

//! @brief Format value for bitfield IOMUXC_GPR13_ENET_STOP_REQ.
#define BF_IOMUXC_GPR13_ENET_STOP_REQ(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_ENET_STOP_REQ) & BM_IOMUXC_GPR13_ENET_STOP_REQ)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ENET_STOP_REQ field to a new value.
#define BW_IOMUXC_GPR13_ENET_STOP_REQ(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_ENET_STOP_REQ) | BF_IOMUXC_GPR13_ENET_STOP_REQ(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field CAN1_STOP_REQ[28] (RW)
 *
 * CAN1 stop request
 *
 * Values:
 * - 0 - Stop request off.
 * - 1 - Stop request on.
 */
//@{
#define BP_IOMUXC_GPR13_CAN1_STOP_REQ      (28)      //!< Bit position for IOMUXC_GPR13_CAN1_STOP_REQ.
#define BM_IOMUXC_GPR13_CAN1_STOP_REQ      (0x10000000)  //!< Bit mask for IOMUXC_GPR13_CAN1_STOP_REQ.

//! @brief Get value of IOMUXC_GPR13_CAN1_STOP_REQ from a register value.
#define BG_IOMUXC_GPR13_CAN1_STOP_REQ(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_CAN1_STOP_REQ) >> BP_IOMUXC_GPR13_CAN1_STOP_REQ)

//! @brief Format value for bitfield IOMUXC_GPR13_CAN1_STOP_REQ.
#define BF_IOMUXC_GPR13_CAN1_STOP_REQ(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_CAN1_STOP_REQ) & BM_IOMUXC_GPR13_CAN1_STOP_REQ)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CAN1_STOP_REQ field to a new value.
#define BW_IOMUXC_GPR13_CAN1_STOP_REQ(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_CAN1_STOP_REQ) | BF_IOMUXC_GPR13_CAN1_STOP_REQ(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field CAN2_STOP_REQ[29] (RW)
 *
 * CAN2 stop request
 *
 * Values:
 * - 0 - Stop request off.
 * - 1 - Stop request on.
 */
//@{
#define BP_IOMUXC_GPR13_CAN2_STOP_REQ      (29)      //!< Bit position for IOMUXC_GPR13_CAN2_STOP_REQ.
#define BM_IOMUXC_GPR13_CAN2_STOP_REQ      (0x20000000)  //!< Bit mask for IOMUXC_GPR13_CAN2_STOP_REQ.

//! @brief Get value of IOMUXC_GPR13_CAN2_STOP_REQ from a register value.
#define BG_IOMUXC_GPR13_CAN2_STOP_REQ(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_CAN2_STOP_REQ) >> BP_IOMUXC_GPR13_CAN2_STOP_REQ)

//! @brief Format value for bitfield IOMUXC_GPR13_CAN2_STOP_REQ.
#define BF_IOMUXC_GPR13_CAN2_STOP_REQ(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_CAN2_STOP_REQ) & BM_IOMUXC_GPR13_CAN2_STOP_REQ)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CAN2_STOP_REQ field to a new value.
#define BW_IOMUXC_GPR13_CAN2_STOP_REQ(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_CAN2_STOP_REQ) | BF_IOMUXC_GPR13_CAN2_STOP_REQ(v)))
#endif
//@}

/*! @name Register IOMUXC_GPR13, field SDMA_STOP_REQ[30] (RW)
 *
 * SDMA stop request
 *
 * Values:
 * - 0 - Stop request off.
 * - 1 - Stop request on.
 */
//@{
#define BP_IOMUXC_GPR13_SDMA_STOP_REQ      (30)      //!< Bit position for IOMUXC_GPR13_SDMA_STOP_REQ.
#define BM_IOMUXC_GPR13_SDMA_STOP_REQ      (0x40000000)  //!< Bit mask for IOMUXC_GPR13_SDMA_STOP_REQ.

//! @brief Get value of IOMUXC_GPR13_SDMA_STOP_REQ from a register value.
#define BG_IOMUXC_GPR13_SDMA_STOP_REQ(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_GPR13_SDMA_STOP_REQ) >> BP_IOMUXC_GPR13_SDMA_STOP_REQ)

//! @brief Format value for bitfield IOMUXC_GPR13_SDMA_STOP_REQ.
#define BF_IOMUXC_GPR13_SDMA_STOP_REQ(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_GPR13_SDMA_STOP_REQ) & BM_IOMUXC_GPR13_SDMA_STOP_REQ)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SDMA_STOP_REQ field to a new value.
#define BW_IOMUXC_GPR13_SDMA_STOP_REQ(v)   (HW_IOMUXC_GPR13_WR((HW_IOMUXC_GPR13_RD() & ~BM_IOMUXC_GPR13_SDMA_STOP_REQ) | BF_IOMUXC_GPR13_SDMA_STOP_REQ(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd2_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd2_data1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd2_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x4c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd2_data1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: SD2_DAT1. NOTE: Pad SD2_DAT1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD2_DATA1.
 * - ALT1 = 001 - Select signal ECSPI5_SS0. - Configure register IOMUXC_ECSPI5_SS0_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal EIM_CS2.
 * - ALT3 = 011 - Select signal AUD4_TXFS. - Configure register IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal KEY_COL7. - Configure register IOMUXC_KEY_COL7_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO1_IO14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE__ALT0 (0x0) //!< Select signal SD2_DATA1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_SS0. - Configure register IOMUXC_ECSPI5_SS0_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE__ALT2 (0x2) //!< Select signal EIM_CS2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_TXFS. - Configure register IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE__ALT4 (0x4) //!< Select signal KEY_COL7. - Configure register IOMUXC_KEY_COL7_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO14.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD2_DAT1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION__ENABLED (0x1) //!< Force input path of pad SD2_DAT1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd2_data2
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd2_data2_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd2_data2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_ADDR      (REGS_IOMUXC_BASE + 0x50)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd2_data2_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: SD2_DAT2. NOTE: Pad SD2_DAT2 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD2_DATA2.
 * - ALT1 = 001 - Select signal ECSPI5_SS1. - Configure register IOMUXC_ECSPI5_SS1_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal EIM_CS3.
 * - ALT3 = 011 - Select signal AUD4_TXD. - Configure register IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal KEY_ROW6. - Configure register IOMUXC_KEY_ROW6_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO1_IO13.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE__ALT0 (0x0) //!< Select signal SD2_DATA2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_SS1. - Configure register IOMUXC_ECSPI5_SS1_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE__ALT2 (0x2) //!< Select signal EIM_CS3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_TXD. - Configure register IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE__ALT4 (0x4) //!< Select signal KEY_ROW6. - Configure register IOMUXC_KEY_ROW6_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO13.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD2_DAT2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION__ENABLED (0x1) //!< Force input path of pad SD2_DAT2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd2_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd2_data0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd2_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x54)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd2_data0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: SD2_DAT0. NOTE: Pad SD2_DAT0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD2_DATA0.
 * - ALT1 = 001 - Select signal ECSPI5_MISO. - Configure register IOMUXC_ECSPI5_MISO_SELECT_INPUT for mode ALT1.
 * - ALT3 = 011 - Select signal AUD4_RXD. - Configure register IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal KEY_ROW7. - Configure register IOMUXC_KEY_ROW7_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO1_IO15.
 * - ALT6 = 110 - Select signal DCIC2_OUT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE__ALT0 (0x0) //!< Select signal SD2_DATA0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_MISO. - Configure register IOMUXC_ECSPI5_MISO_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_RXD. - Configure register IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE__ALT4 (0x4) //!< Select signal KEY_ROW7. - Configure register IOMUXC_KEY_ROW7_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE__ALT6 (0x6) //!< Select signal DCIC2_OUT.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD2_DAT0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION__ENABLED (0x1) //!< Force input path of pad SD2_DAT0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_txc
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_txc_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_txc_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_ADDR      (REGS_IOMUXC_BASE + 0x58)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_txc_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: RGMII_TXC. NOTE: Pad RGMII_TXC is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal USB_H2_DATA.
 * - ALT1 = 001 - Select signal RGMII_TXC.
 * - ALT2 = 010 - Select signal SPDIF_EXT_CLK. - Configure register IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO6_IO19.
 * - ALT7 = 111 - Select signal XTALOSC_REF_CLK_24M.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE__ALT0 (0x0) //!< Select signal USB_H2_DATA.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_TXC.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE__ALT2 (0x2) //!< Select signal SPDIF_EXT_CLK. - Configure register IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE__ALT7 (0x7) //!< Select signal XTALOSC_REF_CLK_24M.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_TXC.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION__ENABLED (0x1) //!< Force input path of pad RGMII_TXC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_td0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_td0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_td0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_ADDR      (REGS_IOMUXC_BASE + 0x5c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_td0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_TD0.
 *
 * Values:
 * - ALT0 = 000 - Select signal HSI_TX_READY.
 * - ALT1 = 001 - Select signal RGMII_TD0.
 * - ALT5 = 101 - Select signal GPIO6_IO20.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE__ALT0 (0x0) //!< Select signal HSI_TX_READY.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_TD0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO20.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_TD0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION__ENABLED (0x1) //!< Force input path of pad RGMII_TD0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_td1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_td1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_td1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_ADDR      (REGS_IOMUXC_BASE + 0x60)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_td1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_TD1.
 *
 * Values:
 * - ALT0 = 000 - Select signal HSI_RX_FLAG.
 * - ALT1 = 001 - Select signal RGMII_TD1.
 * - ALT5 = 101 - Select signal GPIO6_IO21.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE__ALT0 (0x0) //!< Select signal HSI_RX_FLAG.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_TD1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO21.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_TD1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION__ENABLED (0x1) //!< Force input path of pad RGMII_TD1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_td2
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_td2_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_td2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_ADDR      (REGS_IOMUXC_BASE + 0x64)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_td2_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_TD2.
 *
 * Values:
 * - ALT0 = 000 - Select signal HSI_RX_DATA.
 * - ALT1 = 001 - Select signal RGMII_TD2.
 * - ALT5 = 101 - Select signal GPIO6_IO22.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE__ALT0 (0x0) //!< Select signal HSI_RX_DATA.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_TD2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO22.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_TD2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION__ENABLED (0x1) //!< Force input path of pad RGMII_TD2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_td3
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_td3_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_td3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_ADDR      (REGS_IOMUXC_BASE + 0x68)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_td3_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_TD3.
 *
 * Values:
 * - ALT0 = 000 - Select signal HSI_RX_WAKE.
 * - ALT1 = 001 - Select signal RGMII_TD3.
 * - ALT5 = 101 - Select signal GPIO6_IO23.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE__ALT0 (0x0) //!< Select signal HSI_RX_WAKE.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_TD3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO23.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_TD3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION__ENABLED (0x1) //!< Force input path of pad RGMII_TD3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_rx_ctl
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_rx_ctl_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_rx_ctl_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_ADDR      (REGS_IOMUXC_BASE + 0x6c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rx_ctl_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_RX_CTL. NOTE: Pad RGMII_RX_CTL is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal USB_H3_DATA.
 * - ALT1 = 001 - Select signal RGMII_RX_CTL. - Configure register IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT for mode ALT1.
 * - ALT5 = 101 - Select signal GPIO6_IO24.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE__ALT0 (0x0) //!< Select signal USB_H3_DATA.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_RX_CTL. - Configure register IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO24.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_RX_CTL.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION__ENABLED (0x1) //!< Force input path of pad RGMII_RX_CTL.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_rd0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_rd0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_rd0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_ADDR      (REGS_IOMUXC_BASE + 0x70)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rd0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_RD0. NOTE: Pad RGMII_RD0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal HSI_RX_READY.
 * - ALT1 = 001 - Select signal RGMII_RD0. - Configure register IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT for mode ALT1.
 * - ALT5 = 101 - Select signal GPIO6_IO25.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE__ALT0 (0x0) //!< Select signal HSI_RX_READY.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_RD0. - Configure register IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO25.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_RD0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION__ENABLED (0x1) //!< Force input path of pad RGMII_RD0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_tx_ctl
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_tx_ctl_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_tx_ctl_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_ADDR      (REGS_IOMUXC_BASE + 0x74)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_tx_ctl_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: RGMII_TX_CTL. NOTE: Pad RGMII_TX_CTL is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal USB_H2_STROBE.
 * - ALT1 = 001 - Select signal RGMII_TX_CTL.
 * - ALT5 = 101 - Select signal GPIO6_IO26.
 * - ALT7 = 111 - Select signal ENET_REF_CLK. - Configure register IOMUXC_ENET_REF_CLK_SELECT_INPUT for mode ALT7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE__ALT0 (0x0) //!< Select signal USB_H2_STROBE.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_TX_CTL.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO26.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE__ALT7 (0x7) //!< Select signal ENET_REF_CLK. - Configure register IOMUXC_ENET_REF_CLK_SELECT_INPUT for mode ALT7.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_TX_CTL.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION__ENABLED (0x1) //!< Force input path of pad RGMII_TX_CTL.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_rd1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_rd1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_rd1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_ADDR      (REGS_IOMUXC_BASE + 0x78)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rd1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_RD1. NOTE: Pad RGMII_RD1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal HSI_TX_FLAG.
 * - ALT1 = 001 - Select signal RGMII_RD1. - Configure register IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT for mode ALT1.
 * - ALT5 = 101 - Select signal GPIO6_IO27.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE__ALT0 (0x0) //!< Select signal HSI_TX_FLAG.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_RD1. - Configure register IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO27.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_RD1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION__ENABLED (0x1) //!< Force input path of pad RGMII_RD1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_rd2
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_rd2_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_rd2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_ADDR      (REGS_IOMUXC_BASE + 0x7c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rd2_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_RD2. NOTE: Pad RGMII_RD2 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal HSI_TX_DATA.
 * - ALT1 = 001 - Select signal RGMII_RD2. - Configure register IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT for mode ALT1.
 * - ALT5 = 101 - Select signal GPIO6_IO28.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE__ALT0 (0x0) //!< Select signal HSI_TX_DATA.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_RD2. - Configure register IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO28.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_RD2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION__ENABLED (0x1) //!< Force input path of pad RGMII_RD2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_rd3
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_rd3_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_rd3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_ADDR      (REGS_IOMUXC_BASE + 0x80)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rd3_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_RD3. NOTE: Pad RGMII_RD3 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal HSI_TX_WAKE.
 * - ALT1 = 001 - Select signal RGMII_RD3. - Configure register IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT for mode ALT1.
 * - ALT5 = 101 - Select signal GPIO6_IO29.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE__ALT0 (0x0) //!< Select signal HSI_TX_WAKE.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_RD3. - Configure register IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO29.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_RD3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION__ENABLED (0x1) //!< Force input path of pad RGMII_RD3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_rgmii_rxc
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_rgmii_rxc_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_rgmii_rxc_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_ADDR      (REGS_IOMUXC_BASE + 0x84)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC           (*(volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rxc_t *) HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: RGMII_RXC. NOTE: Pad RGMII_RXC is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal USB_H3_STROBE.
 * - ALT1 = 001 - Select signal RGMII_RXC. - Configure register IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT for mode ALT1.
 * - ALT5 = 101 - Select signal GPIO6_IO30.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE__ALT0 (0x0) //!< Select signal USB_H3_STROBE.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE__ALT1 (0x1) //!< Select signal RGMII_RXC. - Configure register IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO30.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad RGMII_RXC.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION(BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION__ENABLED (0x1) //!< Force input path of pad RGMII_RXC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr25
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr25_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr25_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_ADDR      (REGS_IOMUXC_BASE + 0x88)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr25_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_A25. NOTE: Pad EIM_A25 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR25.
 * - ALT1 = 001 - Select signal ECSPI4_SS1.
 * - ALT2 = 010 - Select signal ECSPI2_RDY.
 * - ALT3 = 011 - Select signal IPU1_DI1_PIN12.
 * - ALT4 = 100 - Select signal IPU1_DI0_D1_CS.
 * - ALT5 = 101 - Select signal GPIO5_IO02.
 * - ALT6 = 110 - Select signal HDMI_TX_CEC_LINE. - Configure register IOMUXC_HDMI_ICECIN_SELECT_INPUT for mode ALT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR25.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI4_SS1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_RDY.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE__ALT3 (0x3) //!< Select signal IPU1_DI1_PIN12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE__ALT4 (0x4) //!< Select signal IPU1_DI0_D1_CS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE__ALT6 (0x6) //!< Select signal HDMI_TX_CEC_LINE. - Configure register IOMUXC_HDMI_ICECIN_SELECT_INPUT for mode ALT6.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A25.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION__ENABLED (0x1) //!< Force input path of pad EIM_A25.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_eb2
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_eb2_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_eb2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_ADDR      (REGS_IOMUXC_BASE + 0x8c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_eb2_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_EB2, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_EB2. NOTE: Pad EIM_EB2 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_EB2.
 * - ALT1 = 001 - Select signal ECSPI1_SS0. - Configure register IOMUXC_ECSPI1_SS0_SELECT_INPUT for mode ALT1.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA19. - Configure register IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal HDMI_TX_DDC_SCL. - Configure register IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO2_IO30.
 * - ALT6 = 110 - Select signal I2C2_SCL. - Configure register IOMUXC_I2C2_SCL_IN_SELECT_INPUT for mode ALT6.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG30.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_EB2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI1_SS0. - Configure register IOMUXC_ECSPI1_SS0_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA19. - Configure register IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE__ALT4 (0x4) //!< Select signal HDMI_TX_DDC_SCL. - Configure register IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO30.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE__ALT6 (0x6) //!< Select signal I2C2_SCL. - Configure register IOMUXC_I2C2_SCL_IN_SELECT_INPUT for mode ALT6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG30.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_EB2, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_EB2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION__ENABLED (0x1) //!< Force input path of pad EIM_EB2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data16
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data16_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_ADDR      (REGS_IOMUXC_BASE + 0x90)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data16_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_D16. NOTE: Pad EIM_D16 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA16.
 * - ALT1 = 001 - Select signal ECSPI1_SCLK. - Configure register IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT for mode
 *     ALT1.
 * - ALT2 = 010 - Select signal IPU1_DI0_PIN05.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA18. - Configure register IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal HDMI_TX_DDC_SDA. - Configure register IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO16.
 * - ALT6 = 110 - Select signal I2C2_SDA. - Configure register IOMUXC_I2C2_SDA_IN_SELECT_INPUT for mode ALT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI1_SCLK. - Configure register IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI0_PIN05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA18. - Configure register IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE__ALT4 (0x4) //!< Select signal HDMI_TX_DDC_SDA. - Configure register IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE__ALT6 (0x6) //!< Select signal I2C2_SDA. - Configure register IOMUXC_I2C2_SDA_IN_SELECT_INPUT for mode ALT6.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D16.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION__ENABLED (0x1) //!< Force input path of pad EIM_D16.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data17
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data17_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_ADDR      (REGS_IOMUXC_BASE + 0x94)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data17_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_D17. NOTE: Pad EIM_D17 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA17.
 * - ALT1 = 001 - Select signal ECSPI1_MISO. - Configure register IOMUXC_ECSPI1_MISO_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal IPU1_DI0_PIN06.
 * - ALT3 = 011 - Select signal IPU2_CSI1_PIXCLK. - Configure register IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal DCIC1_OUT.
 * - ALT5 = 101 - Select signal GPIO3_IO17.
 * - ALT6 = 110 - Select signal I2C3_SCL. - Configure register IOMUXC_I2C3_SCL_IN_SELECT_INPUT for mode ALT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI1_MISO. - Configure register IOMUXC_ECSPI1_MISO_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI0_PIN06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_PIXCLK. - Configure register IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE__ALT4 (0x4) //!< Select signal DCIC1_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE__ALT6 (0x6) //!< Select signal I2C3_SCL. - Configure register IOMUXC_I2C3_SCL_IN_SELECT_INPUT for mode ALT6.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION__ENABLED (0x1) //!< Force input path of pad EIM_D17.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data18
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data18_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_ADDR      (REGS_IOMUXC_BASE + 0x98)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data18_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_D18. NOTE: Pad EIM_D18 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA18.
 * - ALT1 = 001 - Select signal ECSPI1_MOSI. - Configure register IOMUXC_ECSPI1_MOSI_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal IPU1_DI0_PIN07.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA17. - Configure register IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal IPU1_DI1_D0_CS.
 * - ALT5 = 101 - Select signal GPIO3_IO18.
 * - ALT6 = 110 - Select signal I2C3_SDA. - Configure register IOMUXC_I2C3_SDA_IN_SELECT_INPUT for mode ALT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA18.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI1_MOSI. - Configure register IOMUXC_ECSPI1_MOSI_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI0_PIN07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA17. - Configure register IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE__ALT4 (0x4) //!< Select signal IPU1_DI1_D0_CS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO18.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE__ALT6 (0x6) //!< Select signal I2C3_SDA. - Configure register IOMUXC_I2C3_SDA_IN_SELECT_INPUT for mode ALT6.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D18.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION__ENABLED (0x1) //!< Force input path of pad EIM_D18.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data19
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data19_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_ADDR      (REGS_IOMUXC_BASE + 0x9c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data19_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_D19. NOTE: Pad EIM_D19 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA19.
 * - ALT1 = 001 - Select signal ECSPI1_SS1. - Configure register IOMUXC_ECSPI1_SS1_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal IPU1_DI0_PIN08.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA16. - Configure register IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal UART1_CTS_B. - Configure register IOMUXC_UART1_UART_RTS_B_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO19.
 * - ALT6 = 110 - Select signal EPIT1_OUT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI1_SS1. - Configure register IOMUXC_ECSPI1_SS1_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI0_PIN08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA16. - Configure register IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE__ALT4 (0x4) //!< Select signal UART1_CTS_B. - Configure register IOMUXC_UART1_UART_RTS_B_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE__ALT6 (0x6) //!< Select signal EPIT1_OUT.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D19.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION__ENABLED (0x1) //!< Force input path of pad EIM_D19.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data20
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data20_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data20_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_ADDR      (REGS_IOMUXC_BASE + 0xa0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data20_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_D20. NOTE: Pad EIM_D20 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA20.
 * - ALT1 = 001 - Select signal ECSPI4_SS0. - Configure register IOMUXC_ECSPI4_SS0_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal IPU1_DI0_PIN16.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA15. - Configure register IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal UART1_RTS_B. - Configure register IOMUXC_UART1_UART_RTS_B_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO20.
 * - ALT6 = 110 - Select signal EPIT2_OUT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA20.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI4_SS0. - Configure register IOMUXC_ECSPI4_SS0_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI0_PIN16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA15. - Configure register IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE__ALT4 (0x4) //!< Select signal UART1_RTS_B. - Configure register IOMUXC_UART1_UART_RTS_B_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO20.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE__ALT6 (0x6) //!< Select signal EPIT2_OUT.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D20.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION__ENABLED (0x1) //!< Force input path of pad EIM_D20.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data21
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data21_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data21_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_ADDR      (REGS_IOMUXC_BASE + 0xa4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data21_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: EIM_D21. NOTE: Pad EIM_D21 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA21.
 * - ALT1 = 001 - Select signal ECSPI4_SCLK.
 * - ALT2 = 010 - Select signal IPU1_DI0_PIN17.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA11. - Configure register IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal USB_OTG_OC. - Configure register IOMUXC_USB_OTG_OC_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO21.
 * - ALT6 = 110 - Select signal I2C1_SCL. - Configure register IOMUXC_I2C1_SCL_IN_SELECT_INPUT for mode ALT6.
 * - ALT7 = 111 - Select signal SPDIF_IN. - Configure register IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT for mode ALT7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA21.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI4_SCLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI0_PIN17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA11. - Configure register IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE__ALT4 (0x4) //!< Select signal USB_OTG_OC. - Configure register IOMUXC_USB_OTG_OC_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO21.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE__ALT6 (0x6) //!< Select signal I2C1_SCL. - Configure register IOMUXC_I2C1_SCL_IN_SELECT_INPUT for mode ALT6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE__ALT7 (0x7) //!< Select signal SPDIF_IN. - Configure register IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT for mode ALT7.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D21.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION__ENABLED (0x1) //!< Force input path of pad EIM_D21.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data22
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data22_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data22_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_ADDR      (REGS_IOMUXC_BASE + 0xa8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data22_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_D22. NOTE: Pad EIM_D22 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA22.
 * - ALT1 = 001 - Select signal ECSPI4_MISO.
 * - ALT2 = 010 - Select signal IPU1_DI0_PIN01.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA10. - Configure register IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal USB_OTG_PWR.
 * - ALT5 = 101 - Select signal GPIO3_IO22.
 * - ALT6 = 110 - Select signal SPDIF_OUT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA22.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI4_MISO.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI0_PIN01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA10. - Configure register IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE__ALT4 (0x4) //!< Select signal USB_OTG_PWR.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO22.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE__ALT6 (0x6) //!< Select signal SPDIF_OUT.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D22.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION__ENABLED (0x1) //!< Force input path of pad EIM_D22.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data23
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data23_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data23_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_ADDR      (REGS_IOMUXC_BASE + 0xac)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data23_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: EIM_D23. NOTE: Pad EIM_D23 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA23.
 * - ALT1 = 001 - Select signal IPU1_DI0_D0_CS.
 * - ALT2 = 010 - Select signal UART3_CTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal UART1_DCD_B.
 * - ALT4 = 100 - Select signal IPU2_CSI1_DATA_EN. - Configure register IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT for
 *     mode ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO23.
 * - ALT6 = 110 - Select signal IPU1_DI1_PIN02.
 * - ALT7 = 111 - Select signal IPU1_DI1_PIN14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA23.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI0_D0_CS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE__ALT2 (0x2) //!< Select signal UART3_CTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE__ALT3 (0x3) //!< Select signal UART1_DCD_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE__ALT4 (0x4) //!< Select signal IPU2_CSI1_DATA_EN. - Configure register IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO23.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE__ALT6 (0x6) //!< Select signal IPU1_DI1_PIN02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE__ALT7 (0x7) //!< Select signal IPU1_DI1_PIN14.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D23.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION__ENABLED (0x1) //!< Force input path of pad EIM_D23.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_eb3
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_eb3_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_eb3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_ADDR      (REGS_IOMUXC_BASE + 0xb0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_eb3_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_EB3, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: EIM_EB3. NOTE: Pad EIM_EB3 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_EB3.
 * - ALT1 = 001 - Select signal ECSPI4_RDY.
 * - ALT2 = 010 - Select signal UART3_RTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal UART1_RI_B.
 * - ALT4 = 100 - Select signal IPU2_CSI1_HSYNC. - Configure register IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO2_IO31.
 * - ALT6 = 110 - Select signal IPU1_DI1_PIN03.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG31.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_EB3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI4_RDY.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE__ALT2 (0x2) //!< Select signal UART3_RTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE__ALT3 (0x3) //!< Select signal UART1_RI_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE__ALT4 (0x4) //!< Select signal IPU2_CSI1_HSYNC. - Configure register IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO31.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE__ALT6 (0x6) //!< Select signal IPU1_DI1_PIN03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG31.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_EB3, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_EB3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION__ENABLED (0x1) //!< Force input path of pad EIM_EB3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data24
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data24_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data24_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_ADDR      (REGS_IOMUXC_BASE + 0xb4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data24_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: EIM_D24. NOTE: Pad EIM_D24 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA24.
 * - ALT1 = 001 - Select signal ECSPI4_SS2.
 * - ALT2 = 010 - Select signal UART3_TX_DATA. - Configure register IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal ECSPI1_SS2. - Configure register IOMUXC_ECSPI1_SS2_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal ECSPI2_SS2.
 * - ALT5 = 101 - Select signal GPIO3_IO24.
 * - ALT6 = 110 - Select signal AUD5_RXFS. - Configure register IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT for mode ALT6.
 * - ALT7 = 111 - Select signal UART1_DTR_B.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA24.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI4_SS2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE__ALT2 (0x2) //!< Select signal UART3_TX_DATA. - Configure register IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE__ALT3 (0x3) //!< Select signal ECSPI1_SS2. - Configure register IOMUXC_ECSPI1_SS2_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE__ALT4 (0x4) //!< Select signal ECSPI2_SS2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO24.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE__ALT6 (0x6) //!< Select signal AUD5_RXFS. - Configure register IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT for mode ALT6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE__ALT7 (0x7) //!< Select signal UART1_DTR_B.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D24.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION__ENABLED (0x1) //!< Force input path of pad EIM_D24.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data25
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data25_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data25_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_ADDR      (REGS_IOMUXC_BASE + 0xb8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data25_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: EIM_D25. NOTE: Pad EIM_D25 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA25.
 * - ALT1 = 001 - Select signal ECSPI4_SS3.
 * - ALT2 = 010 - Select signal UART3_RX_DATA. - Configure register IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal ECSPI1_SS3. - Configure register IOMUXC_ECSPI1_SS3_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal ECSPI2_SS3.
 * - ALT5 = 101 - Select signal GPIO3_IO25.
 * - ALT6 = 110 - Select signal AUD5_RXC. - Configure register IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT for mode ALT6.
 * - ALT7 = 111 - Select signal UART1_DSR_B.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA25.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI4_SS3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE__ALT2 (0x2) //!< Select signal UART3_RX_DATA. - Configure register IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE__ALT3 (0x3) //!< Select signal ECSPI1_SS3. - Configure register IOMUXC_ECSPI1_SS3_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE__ALT4 (0x4) //!< Select signal ECSPI2_SS3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO25.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE__ALT6 (0x6) //!< Select signal AUD5_RXC. - Configure register IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT for mode ALT6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE__ALT7 (0x7) //!< Select signal UART1_DSR_B.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D25.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION__ENABLED (0x1) //!< Force input path of pad EIM_D25.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data26
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data26_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data26_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_ADDR      (REGS_IOMUXC_BASE + 0xbc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data26_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: EIM_D26. NOTE: Pad EIM_D26 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA26.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN11.
 * - ALT2 = 010 - Select signal IPU1_CSI0_DATA01.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA14. - Configure register IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal UART2_TX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO26.
 * - ALT6 = 110 - Select signal IPU1_SISG2.
 * - ALT7 = 111 - Select signal IPU1_DISP1_DATA22.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA26.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_CSI0_DATA01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA14. - Configure register IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE__ALT4 (0x4) //!< Select signal UART2_TX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO26.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE__ALT6 (0x6) //!< Select signal IPU1_SISG2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE__ALT7 (0x7) //!< Select signal IPU1_DISP1_DATA22.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D26.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION__ENABLED (0x1) //!< Force input path of pad EIM_D26.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data27
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data27_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data27_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_ADDR      (REGS_IOMUXC_BASE + 0xc0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data27_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: EIM_D27. NOTE: Pad EIM_D27 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA27.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN13.
 * - ALT2 = 010 - Select signal IPU1_CSI0_DATA00.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA13. - Configure register IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal UART2_RX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO27.
 * - ALT6 = 110 - Select signal IPU1_SISG3.
 * - ALT7 = 111 - Select signal IPU1_DISP1_DATA23.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA27.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_CSI0_DATA00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA13. - Configure register IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE__ALT4 (0x4) //!< Select signal UART2_RX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO27.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE__ALT6 (0x6) //!< Select signal IPU1_SISG3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE__ALT7 (0x7) //!< Select signal IPU1_DISP1_DATA23.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D27.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION__ENABLED (0x1) //!< Force input path of pad EIM_D27.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data28
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data28_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data28_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_ADDR      (REGS_IOMUXC_BASE + 0xc4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data28_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: EIM_D28. NOTE: Pad EIM_D28 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA28.
 * - ALT1 = 001 - Select signal I2C1_SDA. - Configure register IOMUXC_I2C1_SDA_IN_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal ECSPI4_MOSI.
 * - ALT3 = 011 - Select signal IPU2_CSI1_DATA12. - Configure register IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal UART2_CTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO28.
 * - ALT6 = 110 - Select signal IPU1_EXT_TRIG.
 * - ALT7 = 111 - Select signal IPU1_DI0_PIN13.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA28.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE__ALT1 (0x1) //!< Select signal I2C1_SDA. - Configure register IOMUXC_I2C1_SDA_IN_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI4_MOSI.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_CSI1_DATA12. - Configure register IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE__ALT4 (0x4) //!< Select signal UART2_CTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO28.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE__ALT6 (0x6) //!< Select signal IPU1_EXT_TRIG.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE__ALT7 (0x7) //!< Select signal IPU1_DI0_PIN13.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D28.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION__ENABLED (0x1) //!< Force input path of pad EIM_D28.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data29
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data29_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data29_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_ADDR      (REGS_IOMUXC_BASE + 0xc8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data29_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_D29. NOTE: Pad EIM_D29 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA29.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN15.
 * - ALT2 = 010 - Select signal ECSPI4_SS0. - Configure register IOMUXC_ECSPI4_SS0_SELECT_INPUT for mode ALT2.
 * - ALT4 = 100 - Select signal UART2_RTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO29.
 * - ALT6 = 110 - Select signal IPU2_CSI1_VSYNC. - Configure register IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT for mode
 *     ALT6.
 * - ALT7 = 111 - Select signal IPU1_DI0_PIN14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA29.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI4_SS0. - Configure register IOMUXC_ECSPI4_SS0_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE__ALT4 (0x4) //!< Select signal UART2_RTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO29.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE__ALT6 (0x6) //!< Select signal IPU2_CSI1_VSYNC. - Configure register IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT for mode ALT6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE__ALT7 (0x7) //!< Select signal IPU1_DI0_PIN14.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D29.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION__ENABLED (0x1) //!< Force input path of pad EIM_D29.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data30
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data30_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data30_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_ADDR      (REGS_IOMUXC_BASE + 0xcc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data30_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_D30. NOTE: Pad EIM_D30 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA30.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA21.
 * - ALT2 = 010 - Select signal IPU1_DI0_PIN11.
 * - ALT3 = 011 - Select signal IPU1_CSI0_DATA03.
 * - ALT4 = 100 - Select signal UART3_CTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO30.
 * - ALT6 = 110 - Select signal USB_H1_OC. - Configure register IOMUXC_USB_H1_OC_SELECT_INPUT for mode ALT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA30.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA21.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI0_PIN11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE__ALT3 (0x3) //!< Select signal IPU1_CSI0_DATA03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE__ALT4 (0x4) //!< Select signal UART3_CTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO30.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE__ALT6 (0x6) //!< Select signal USB_H1_OC. - Configure register IOMUXC_USB_H1_OC_SELECT_INPUT for mode ALT6.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D30.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION__ENABLED (0x1) //!< Force input path of pad EIM_D30.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_data31
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_data31_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_data31_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_ADDR      (REGS_IOMUXC_BASE + 0xd0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_data31_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_D31. NOTE: Pad EIM_D31 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_DATA31.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA20.
 * - ALT2 = 010 - Select signal IPU1_DI0_PIN12.
 * - ALT3 = 011 - Select signal IPU1_CSI0_DATA02.
 * - ALT4 = 100 - Select signal UART3_RTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO3_IO31.
 * - ALT6 = 110 - Select signal USB_H1_PWR.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_DATA31.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA20.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI0_PIN12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE__ALT3 (0x3) //!< Select signal IPU1_CSI0_DATA02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE__ALT4 (0x4) //!< Select signal UART3_RTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO31.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE__ALT6 (0x6) //!< Select signal USB_H1_PWR.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_D31.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION__ENABLED (0x1) //!< Force input path of pad EIM_D31.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr24
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr24_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr24_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_ADDR      (REGS_IOMUXC_BASE + 0xd4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr24_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_A24. NOTE: Pad EIM_A24 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR24.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA19.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA19. - Configure register IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal IPU2_SISG2.
 * - ALT4 = 100 - Select signal IPU1_SISG2.
 * - ALT5 = 101 - Select signal GPIO5_IO04.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG24.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR24.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA19. - Configure register IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_SISG2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE__ALT4 (0x4) //!< Select signal IPU1_SISG2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG24.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A24.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION__ENABLED (0x1) //!< Force input path of pad EIM_A24.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr23
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr23_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr23_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_ADDR      (REGS_IOMUXC_BASE + 0xd8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr23_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: EIM_A23. NOTE: Pad EIM_A23 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR23.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA18.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA18. - Configure register IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal IPU2_SISG3.
 * - ALT4 = 100 - Select signal IPU1_SISG3.
 * - ALT5 = 101 - Select signal GPIO6_IO06.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG23.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR23.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA18.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA18. - Configure register IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE__ALT3 (0x3) //!< Select signal IPU2_SISG3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE__ALT4 (0x4) //!< Select signal IPU1_SISG3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG23.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A23.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION__ENABLED (0x1) //!< Force input path of pad EIM_A23.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr22
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr22_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr22_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_ADDR      (REGS_IOMUXC_BASE + 0xdc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr22_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_A22. NOTE: Pad EIM_A22 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR22.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA17.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA17. - Configure register IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO16.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG22.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR22.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA17. - Configure register IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG22.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A22.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION__ENABLED (0x1) //!< Force input path of pad EIM_A22.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr21
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr21_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr21_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_ADDR      (REGS_IOMUXC_BASE + 0xe0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr21_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_A21. NOTE: Pad EIM_A21 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR21.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA16.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA16. - Configure register IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO17.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG21.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR21.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA16. - Configure register IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG21.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A21.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION__ENABLED (0x1) //!< Force input path of pad EIM_A21.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr20
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr20_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr20_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_ADDR      (REGS_IOMUXC_BASE + 0xe4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr20_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_A20. NOTE: Pad EIM_A20 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR20.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA15.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA15. - Configure register IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO18.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG20.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR20.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA15. - Configure register IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO18.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG20.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A20.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION__ENABLED (0x1) //!< Force input path of pad EIM_A20.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr19
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr19_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_ADDR      (REGS_IOMUXC_BASE + 0xe8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr19_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_A19. NOTE: Pad EIM_A19 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR19.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA14.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA14. - Configure register IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO19.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG19.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA14.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA14. - Configure register IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG19.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A19.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION__ENABLED (0x1) //!< Force input path of pad EIM_A19.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr18
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr18_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_ADDR      (REGS_IOMUXC_BASE + 0xec)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr18_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_A18. NOTE: Pad EIM_A18 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR18.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA13.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA13. - Configure register IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO20.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG18.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR18.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA13. - Configure register IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO20.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG18.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A18.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION__ENABLED (0x1) //!< Force input path of pad EIM_A18.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr17
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr17_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_ADDR      (REGS_IOMUXC_BASE + 0xf0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr17_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_A17. NOTE: Pad EIM_A17 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR17.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA12.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA12. - Configure register IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO21.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA12. - Configure register IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO21.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG17.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION__ENABLED (0x1) //!< Force input path of pad EIM_A17.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_addr16
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_addr16_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_addr16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_ADDR      (REGS_IOMUXC_BASE + 0xf4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr16_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_A16. NOTE: Pad EIM_A16 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_ADDR16.
 * - ALT1 = 001 - Select signal IPU1_DI1_DISP_CLK.
 * - ALT2 = 010 - Select signal IPU2_CSI1_PIXCLK. - Configure register IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO22.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG16.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_ADDR16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_DISP_CLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_PIXCLK. - Configure register IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO22.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG16.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_A16.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION__ENABLED (0x1) //!< Force input path of pad EIM_A16.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_cs0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_cs0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_cs0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_ADDR      (REGS_IOMUXC_BASE + 0xf8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_cs0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_CS0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: EIM_CS0. NOTE: Pad EIM_CS0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_CS0.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN05.
 * - ALT2 = 010 - Select signal ECSPI2_SCLK. - Configure register IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO23.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_CS0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_SCLK. - Configure register IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO23.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_CS0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_CS0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION__ENABLED (0x1) //!< Force input path of pad EIM_CS0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_cs1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_cs1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_cs1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_ADDR      (REGS_IOMUXC_BASE + 0xfc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_cs1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_CS1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: EIM_CS1. NOTE: Pad EIM_CS1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_CS1.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN06.
 * - ALT2 = 010 - Select signal ECSPI2_MOSI. - Configure register IOMUXC_ECSPI2_MOSI_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO24.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_CS1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_MOSI. - Configure register IOMUXC_ECSPI2_MOSI_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO24.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_CS1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_CS1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION__ENABLED (0x1) //!< Force input path of pad EIM_CS1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_oe
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_oe_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_oe_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_OE register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_ADDR      (REGS_IOMUXC_BASE + 0x100)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_oe_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_OE bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_OE, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: EIM_OE. NOTE: Pad EIM_OE is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_OE.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN07.
 * - ALT2 = 010 - Select signal ECSPI2_MISO. - Configure register IOMUXC_ECSPI2_MISO_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO25.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_OE.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_MISO. - Configure register IOMUXC_ECSPI2_MISO_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO25.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_OE, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_OE.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION__ENABLED (0x1) //!< Force input path of pad EIM_OE.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_rw
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_rw_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_rw_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_RW register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_ADDR      (REGS_IOMUXC_BASE + 0x104)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_rw_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_RW bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_RW, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_RW. NOTE: Pad EIM_RW is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_RW.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN08.
 * - ALT2 = 010 - Select signal ECSPI2_SS0. - Configure register IOMUXC_ECSPI2_SS0_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO26.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG29.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_RW.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_SS0. - Configure register IOMUXC_ECSPI2_SS0_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO26.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG29.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_RW, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_RW.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION__ENABLED (0x1) //!< Force input path of pad EIM_RW.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_lba
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_lba_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_lba_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_LBA register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_ADDR      (REGS_IOMUXC_BASE + 0x108)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_lba_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_LBA bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_LBA, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_LBA. NOTE: Pad EIM_LBA is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_LBA.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN17.
 * - ALT2 = 010 - Select signal ECSPI2_SS1. - Configure register IOMUXC_ECSPI2_SS1_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO27.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG26.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_LBA.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_SS1. - Configure register IOMUXC_ECSPI2_SS1_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO27.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG26.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_LBA, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_LBA.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION__ENABLED (0x1) //!< Force input path of pad EIM_LBA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_eb0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_eb0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_eb0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_ADDR      (REGS_IOMUXC_BASE + 0x10c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_eb0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_EB0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: EIM_EB0. NOTE: Pad EIM_EB0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_EB0.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA11.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA11. - Configure register IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT for mode
 *     ALT2.
 * - ALT4 = 100 - Select signal CCM_PMIC_READY. - Configure register IOMUXC_CCM_PMIC_READY_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO2_IO28.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG27.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_EB0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA11. - Configure register IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE__ALT4 (0x4) //!< Select signal CCM_PMIC_READY. - Configure register IOMUXC_CCM_PMIC_READY_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO28.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG27.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_EB0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_EB0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION__ENABLED (0x1) //!< Force input path of pad EIM_EB0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_eb1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_eb1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_eb1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_ADDR      (REGS_IOMUXC_BASE + 0x110)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_eb1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_EB1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_EB1. NOTE: Pad EIM_EB1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_EB1.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA10.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA10. - Configure register IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO29.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG28.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_EB1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA10.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA10. - Configure register IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO29.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG28.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_EB1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_EB1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION__ENABLED (0x1) //!< Force input path of pad EIM_EB1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad00
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad00_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad00_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_ADDR      (REGS_IOMUXC_BASE + 0x114)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad00_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD00, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA0.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD00.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA09.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA09.
 * - ALT5 = 101 - Select signal GPIO3_IO00.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG00.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG00.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD00, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad01
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad01_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad01_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_ADDR      (REGS_IOMUXC_BASE + 0x118)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad01_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD01, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA1.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD01.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA08.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA08.
 * - ALT5 = 101 - Select signal GPIO3_IO01.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG01.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG01.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD01, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad02
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad02_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_ADDR      (REGS_IOMUXC_BASE + 0x11c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad02_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD02, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA2.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD02.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA07.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA07.
 * - ALT5 = 101 - Select signal GPIO3_IO02.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG02.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG02.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD02, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad03
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad03_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_ADDR      (REGS_IOMUXC_BASE + 0x120)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad03_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD03, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA3.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD03.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA06.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA06.
 * - ALT5 = 101 - Select signal GPIO3_IO03.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG03.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG03.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD03, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad04
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad04_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_ADDR      (REGS_IOMUXC_BASE + 0x124)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad04_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD04, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA4.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD04.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA05.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA05.
 * - ALT5 = 101 - Select signal GPIO3_IO04.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG04.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG04.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD04, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad05
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad05_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_ADDR      (REGS_IOMUXC_BASE + 0x128)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad05_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD05, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA5.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD05.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA04.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA04.
 * - ALT5 = 101 - Select signal GPIO3_IO05.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG05.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG05.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD05, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA5.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA5.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad06
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad06_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_ADDR      (REGS_IOMUXC_BASE + 0x12c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad06_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD06, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA6.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD06.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA03.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA03.
 * - ALT5 = 101 - Select signal GPIO3_IO06.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG06.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG06.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD06, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA6.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad07
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad07_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_ADDR      (REGS_IOMUXC_BASE + 0x130)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad07_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD07, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA7.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD07.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA02.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA02.
 * - ALT5 = 101 - Select signal GPIO3_IO07.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG07.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG07.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD07, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA7.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad08
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad08_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad08_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_ADDR      (REGS_IOMUXC_BASE + 0x134)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad08_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD08, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA8.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD08.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA01.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA01.
 * - ALT5 = 101 - Select signal GPIO3_IO08.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG08.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG08.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD08, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA8.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA8.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad09
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad09_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad09_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_ADDR      (REGS_IOMUXC_BASE + 0x138)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad09_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD09, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA9.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD09.
 * - ALT1 = 001 - Select signal IPU1_DISP1_DATA00.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA00.
 * - ALT5 = 101 - Select signal GPIO3_IO09.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG09.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DISP1_DATA00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG09.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD09, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA9.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA9.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad10
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad10_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad10_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_ADDR      (REGS_IOMUXC_BASE + 0x13c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad10_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD10, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA10. NOTE: Pad EIM_DA10 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD10.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN15.
 * - ALT2 = 010 - Select signal IPU2_CSI1_DATA_EN. - Configure register IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT for
 *     mode ALT2.
 * - ALT5 = 101 - Select signal GPIO3_IO10.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD10.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_DATA_EN. - Configure register IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO10.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG10.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD10, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA10.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad11
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad11_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad11_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_ADDR      (REGS_IOMUXC_BASE + 0x140)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad11_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD11, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA11. NOTE: Pad EIM_DA11 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD11.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN02.
 * - ALT2 = 010 - Select signal IPU2_CSI1_HSYNC. - Configure register IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO3_IO11.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG11.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_HSYNC. - Configure register IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG11.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD11, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA11.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA11.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad12
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad12_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad12_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_ADDR      (REGS_IOMUXC_BASE + 0x144)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad12_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD12, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA12. NOTE: Pad EIM_DA12 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD12.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN03.
 * - ALT2 = 010 - Select signal IPU2_CSI1_VSYNC. - Configure register IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO3_IO12.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG12.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE__ALT2 (0x2) //!< Select signal IPU2_CSI1_VSYNC. - Configure register IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG12.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD12, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA12.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA12.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad13
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad13_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad13_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_ADDR      (REGS_IOMUXC_BASE + 0x148)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad13_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD13, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: EIM_DA13.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD13.
 * - ALT1 = 001 - Select signal IPU1_DI1_D0_CS.
 * - ALT5 = 101 - Select signal GPIO3_IO13.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG13.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_D0_CS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG13.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD13, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA13.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA13.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad14
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad14_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad14_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_ADDR      (REGS_IOMUXC_BASE + 0x14c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad14_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD14, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: EIM_DA14.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD14.
 * - ALT1 = 001 - Select signal IPU1_DI1_D1_CS.
 * - ALT5 = 101 - Select signal GPIO3_IO14.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD14.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_D1_CS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO14.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG14.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD14, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA14.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_ad15
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_ad15_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_ad15_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_ADDR      (REGS_IOMUXC_BASE + 0x150)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad15_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD15, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: EIM_DA15.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_AD15.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN01.
 * - ALT2 = 010 - Select signal IPU1_DI1_PIN04.
 * - ALT5 = 101 - Select signal GPIO3_IO15.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG15.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_AD15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE__ALT2 (0x2) //!< Select signal IPU1_DI1_PIN04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO3_IO15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG15.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_AD15, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_DA15.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION__ENABLED (0x1) //!< Force input path of pad EIM_DA15.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_wait
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_wait_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_wait_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_ADDR      (REGS_IOMUXC_BASE + 0x154)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_wait_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: EIM_WAIT.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_WAIT.
 * - ALT1 = 001 - Select signal EIM_DTACK_B.
 * - ALT5 = 101 - Select signal GPIO5_IO00.
 * - ALT7 = 111 - Select signal SRC_BOOT_CFG25.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_WAIT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DTACK_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE__ALT7 (0x7) //!< Select signal SRC_BOOT_CFG25.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_WAIT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION__ENABLED (0x1) //!< Force input path of pad EIM_WAIT.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK - Pad Mux Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_eim_bclk
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_eim_bclk_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_eim_bclk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_ADDR      (REGS_IOMUXC_BASE + 0x158)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK           (*(volatile hw_iomuxc_sw_mux_ctl_pad_eim_bclk_t *) HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: EIM_BCLK.
 *
 * Values:
 * - ALT0 = 000 - Select signal EIM_BCLK.
 * - ALT1 = 001 - Select signal IPU1_DI1_PIN16.
 * - ALT5 = 101 - Select signal GPIO6_IO31.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE__ALT0 (0x0) //!< Select signal EIM_BCLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_DI1_PIN16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO31.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad EIM_BCLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION(BV_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION__ENABLED (0x1) //!< Force input path of pad EIM_BCLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_di0_disp_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_di0_disp_clk_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_di0_disp_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_ADDR      (REGS_IOMUXC_BASE + 0x15c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK           (*(volatile hw_iomuxc_sw_mux_ctl_pad_di0_disp_clk_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: DI0_DISP_CLK.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DI0_DISP_CLK.
 * - ALT1 = 001 - Select signal IPU2_DI0_DISP_CLK.
 * - ALT5 = 101 - Select signal GPIO4_IO16.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DI0_DISP_CLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DI0_DISP_CLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO16.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DI0_DISP_CLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION__ENABLED (0x1) //!< Force input path of pad DI0_DISP_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_di0_pin15
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_di0_pin15_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_di0_pin15_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_ADDR      (REGS_IOMUXC_BASE + 0x160)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15           (*(volatile hw_iomuxc_sw_mux_ctl_pad_di0_pin15_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DI0_PIN15.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DI0_PIN15.
 * - ALT1 = 001 - Select signal IPU2_DI0_PIN15.
 * - ALT2 = 010 - Select signal AUD6_TXC.
 * - ALT5 = 101 - Select signal GPIO4_IO17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DI0_PIN15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DI0_PIN15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE__ALT2 (0x2) //!< Select signal AUD6_TXC.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO17.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DI0_PIN15.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION__ENABLED (0x1) //!< Force input path of pad DI0_PIN15.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_di0_pin02
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_di0_pin02_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_di0_pin02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_ADDR      (REGS_IOMUXC_BASE + 0x164)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02           (*(volatile hw_iomuxc_sw_mux_ctl_pad_di0_pin02_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DI0_PIN2.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DI0_PIN02.
 * - ALT1 = 001 - Select signal IPU2_DI0_PIN02.
 * - ALT2 = 010 - Select signal AUD6_TXD.
 * - ALT5 = 101 - Select signal GPIO4_IO18.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DI0_PIN02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DI0_PIN02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE__ALT2 (0x2) //!< Select signal AUD6_TXD.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO18.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DI0_PIN2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION__ENABLED (0x1) //!< Force input path of pad DI0_PIN2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_di0_pin03
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_di0_pin03_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_di0_pin03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_ADDR      (REGS_IOMUXC_BASE + 0x168)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03           (*(volatile hw_iomuxc_sw_mux_ctl_pad_di0_pin03_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DI0_PIN3.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DI0_PIN03.
 * - ALT1 = 001 - Select signal IPU2_DI0_PIN03.
 * - ALT2 = 010 - Select signal AUD6_TXFS.
 * - ALT5 = 101 - Select signal GPIO4_IO19.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DI0_PIN03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DI0_PIN03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE__ALT2 (0x2) //!< Select signal AUD6_TXFS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO19.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DI0_PIN3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION__ENABLED (0x1) //!< Force input path of pad DI0_PIN3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_di0_pin04
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_di0_pin04_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_di0_pin04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_ADDR      (REGS_IOMUXC_BASE + 0x16c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04           (*(volatile hw_iomuxc_sw_mux_ctl_pad_di0_pin04_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DI0_PIN4. NOTE: Pad DI0_PIN4 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DI0_PIN04.
 * - ALT1 = 001 - Select signal IPU2_DI0_PIN04.
 * - ALT2 = 010 - Select signal AUD6_RXD.
 * - ALT3 = 011 - Select signal SD1_WP. - Configure register IOMUXC_USDHC1_WP_ON_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO4_IO20.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DI0_PIN04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DI0_PIN04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE__ALT2 (0x2) //!< Select signal AUD6_RXD.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE__ALT3 (0x3) //!< Select signal SD1_WP. - Configure register IOMUXC_USDHC1_WP_ON_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO20.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DI0_PIN4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION__ENABLED (0x1) //!< Force input path of pad DI0_PIN4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data00
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data00_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data00_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_ADDR      (REGS_IOMUXC_BASE + 0x170)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data00_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DISP0_DAT0.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA00.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA00.
 * - ALT2 = 010 - Select signal ECSPI3_SCLK.
 * - ALT5 = 101 - Select signal GPIO4_IO21.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI3_SCLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO21.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data01
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data01_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data01_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_ADDR      (REGS_IOMUXC_BASE + 0x174)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data01_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DISP0_DAT1.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA01.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA01.
 * - ALT2 = 010 - Select signal ECSPI3_MOSI.
 * - ALT5 = 101 - Select signal GPIO4_IO22.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI3_MOSI.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO22.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data02
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data02_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_ADDR      (REGS_IOMUXC_BASE + 0x178)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data02_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DISP0_DAT2.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA02.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA02.
 * - ALT2 = 010 - Select signal ECSPI3_MISO.
 * - ALT5 = 101 - Select signal GPIO4_IO23.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI3_MISO.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO23.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data03
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data03_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_ADDR      (REGS_IOMUXC_BASE + 0x17c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data03_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DISP0_DAT3.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA03.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA03.
 * - ALT2 = 010 - Select signal ECSPI3_SS0.
 * - ALT5 = 101 - Select signal GPIO4_IO24.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI3_SS0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO24.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data04
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data04_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_ADDR      (REGS_IOMUXC_BASE + 0x180)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data04_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DISP0_DAT4.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA04.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA04.
 * - ALT2 = 010 - Select signal ECSPI3_SS1.
 * - ALT5 = 101 - Select signal GPIO4_IO25.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI3_SS1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO25.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data05
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data05_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_ADDR      (REGS_IOMUXC_BASE + 0x184)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data05_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DISP0_DAT5.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA05.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA05.
 * - ALT2 = 010 - Select signal ECSPI3_SS2.
 * - ALT3 = 011 - Select signal AUD6_RXFS.
 * - ALT5 = 101 - Select signal GPIO4_IO26.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI3_SS2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE__ALT3 (0x3) //!< Select signal AUD6_RXFS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO26.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT5.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT5.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data06
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data06_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_ADDR      (REGS_IOMUXC_BASE + 0x188)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data06_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DISP0_DAT6.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA06.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA06.
 * - ALT2 = 010 - Select signal ECSPI3_SS3.
 * - ALT3 = 011 - Select signal AUD6_RXC.
 * - ALT5 = 101 - Select signal GPIO4_IO27.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI3_SS3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE__ALT3 (0x3) //!< Select signal AUD6_RXC.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO27.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT6.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data07
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data07_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_ADDR      (REGS_IOMUXC_BASE + 0x18c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data07_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DISP0_DAT7.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA07.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA07.
 * - ALT2 = 010 - Select signal ECSPI3_RDY.
 * - ALT5 = 101 - Select signal GPIO4_IO28.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI3_RDY.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO28.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT7.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data08
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data08_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data08_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_ADDR      (REGS_IOMUXC_BASE + 0x190)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data08_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DISP0_DAT8.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA08.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA08.
 * - ALT2 = 010 - Select signal PWM1_OUT.
 * - ALT3 = 011 - Select signal WDOG1_B.
 * - ALT5 = 101 - Select signal GPIO4_IO29.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE__ALT2 (0x2) //!< Select signal PWM1_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE__ALT3 (0x3) //!< Select signal WDOG1_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO29.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT8.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT8.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data09
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data09_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data09_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_ADDR      (REGS_IOMUXC_BASE + 0x194)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data09_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DISP0_DAT9.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA09.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA09.
 * - ALT2 = 010 - Select signal PWM2_OUT.
 * - ALT3 = 011 - Select signal WDOG2_B.
 * - ALT5 = 101 - Select signal GPIO4_IO30.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE__ALT2 (0x2) //!< Select signal PWM2_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE__ALT3 (0x3) //!< Select signal WDOG2_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO30.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT9.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT9.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data10
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data10_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data10_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_ADDR      (REGS_IOMUXC_BASE + 0x198)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data10_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: DISP0_DAT10.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA10.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA10.
 * - ALT5 = 101 - Select signal GPIO4_IO31.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA10.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA10.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO31.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT10.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data11
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data11_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data11_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_ADDR      (REGS_IOMUXC_BASE + 0x19c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data11_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: DISP0_DAT11.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA11.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA11.
 * - ALT5 = 101 - Select signal GPIO5_IO05.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO05.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT11.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT11.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data12
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data12_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data12_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_ADDR      (REGS_IOMUXC_BASE + 0x1a0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data12_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: DISP0_DAT12.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA12.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA12.
 * - ALT5 = 101 - Select signal GPIO5_IO06.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO06.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT12.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT12.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data13
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data13_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data13_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_ADDR      (REGS_IOMUXC_BASE + 0x1a4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data13_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DISP0_DAT13. NOTE: Pad DISP0_DAT13 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA13.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA13.
 * - ALT3 = 011 - Select signal AUD5_RXFS. - Configure register IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO07.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE__ALT3 (0x3) //!< Select signal AUD5_RXFS. - Configure register IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO07.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT13.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT13.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data14
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data14_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data14_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_ADDR      (REGS_IOMUXC_BASE + 0x1a8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data14_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: DISP0_DAT14. NOTE: Pad DISP0_DAT14 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA14.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA14.
 * - ALT3 = 011 - Select signal AUD5_RXC. - Configure register IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO08.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA14.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA14.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE__ALT3 (0x3) //!< Select signal AUD5_RXC. - Configure register IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO08.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT14.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data15
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data15_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data15_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_ADDR      (REGS_IOMUXC_BASE + 0x1ac)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data15_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DISP0_DAT15. NOTE: Pad DISP0_DAT15 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA15.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA15.
 * - ALT2 = 010 - Select signal ECSPI1_SS1. - Configure register IOMUXC_ECSPI1_SS1_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal ECSPI2_SS1. - Configure register IOMUXC_ECSPI2_SS1_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO09.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI1_SS1. - Configure register IOMUXC_ECSPI1_SS1_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE__ALT3 (0x3) //!< Select signal ECSPI2_SS1. - Configure register IOMUXC_ECSPI2_SS1_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO09.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT15.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT15.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data16
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data16_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_ADDR      (REGS_IOMUXC_BASE + 0x1b0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data16_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: DISP0_DAT16. NOTE: Pad DISP0_DAT16 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA16.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA16.
 * - ALT2 = 010 - Select signal ECSPI2_MOSI. - Configure register IOMUXC_ECSPI2_MOSI_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal AUD5_TXC. - Configure register IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal SDMA_EXT_EVENT0. - Configure register IOMUXC_SDMA_EVENTS14_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO5_IO10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_MOSI. - Configure register IOMUXC_ECSPI2_MOSI_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE__ALT3 (0x3) //!< Select signal AUD5_TXC. - Configure register IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE__ALT4 (0x4) //!< Select signal SDMA_EXT_EVENT0. - Configure register IOMUXC_SDMA_EVENTS14_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO10.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT16.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT16.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data17
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data17_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_ADDR      (REGS_IOMUXC_BASE + 0x1b4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data17_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: DISP0_DAT17. NOTE: Pad DISP0_DAT17 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA17.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA17.
 * - ALT2 = 010 - Select signal ECSPI2_MISO. - Configure register IOMUXC_ECSPI2_MISO_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal AUD5_TXD. - Configure register IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal SDMA_EXT_EVENT1. - Configure register IOMUXC_SDMA_EVENTS15_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO5_IO11.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_MISO. - Configure register IOMUXC_ECSPI2_MISO_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE__ALT3 (0x3) //!< Select signal AUD5_TXD. - Configure register IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE__ALT4 (0x4) //!< Select signal SDMA_EXT_EVENT1. - Configure register IOMUXC_SDMA_EVENTS15_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO11.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT17.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data18
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data18_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_ADDR      (REGS_IOMUXC_BASE + 0x1b8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data18_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: DISP0_DAT18. NOTE: Pad DISP0_DAT18 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA18.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA18.
 * - ALT2 = 010 - Select signal ECSPI2_SS0. - Configure register IOMUXC_ECSPI2_SS0_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal AUD5_TXFS. - Configure register IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal AUD4_RXFS. - Configure register IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO5_IO12.
 * - ALT7 = 111 - Select signal EIM_CS2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA18.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA18.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_SS0. - Configure register IOMUXC_ECSPI2_SS0_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE__ALT3 (0x3) //!< Select signal AUD5_TXFS. - Configure register IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE__ALT4 (0x4) //!< Select signal AUD4_RXFS. - Configure register IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE__ALT7 (0x7) //!< Select signal EIM_CS2.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT18.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT18.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data19
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data19_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_ADDR      (REGS_IOMUXC_BASE + 0x1bc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data19_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: DISP0_DAT19. NOTE: Pad DISP0_DAT19 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA19.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA19.
 * - ALT2 = 010 - Select signal ECSPI2_SCLK. - Configure register IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal AUD5_RXD. - Configure register IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal AUD4_RXC. - Configure register IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO5_IO13.
 * - ALT7 = 111 - Select signal EIM_CS3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_SCLK. - Configure register IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE__ALT3 (0x3) //!< Select signal AUD5_RXD. - Configure register IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE__ALT4 (0x4) //!< Select signal AUD4_RXC. - Configure register IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE__ALT7 (0x7) //!< Select signal EIM_CS3.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT19.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT19.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data20
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data20_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data20_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_ADDR      (REGS_IOMUXC_BASE + 0x1c0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data20_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DISP0_DAT20. NOTE: Pad DISP0_DAT20 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA20.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA20.
 * - ALT2 = 010 - Select signal ECSPI1_SCLK. - Configure register IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal AUD4_TXC. - Configure register IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA20.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA20.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI1_SCLK. - Configure register IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_TXC. - Configure register IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO14.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT20.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT20.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data21
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data21_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data21_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_ADDR      (REGS_IOMUXC_BASE + 0x1c4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data21_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DISP0_DAT21. NOTE: Pad DISP0_DAT21 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA21.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA21.
 * - ALT2 = 010 - Select signal ECSPI1_MOSI. - Configure register IOMUXC_ECSPI1_MOSI_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal AUD4_TXD. - Configure register IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO15.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA21.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA21.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI1_MOSI. - Configure register IOMUXC_ECSPI1_MOSI_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_TXD. - Configure register IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO15.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT21.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT21.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data22
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data22_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data22_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_ADDR      (REGS_IOMUXC_BASE + 0x1c8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data22_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DISP0_DAT22. NOTE: Pad DISP0_DAT22 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA22.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA22.
 * - ALT2 = 010 - Select signal ECSPI1_MISO. - Configure register IOMUXC_ECSPI1_MISO_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal AUD4_TXFS. - Configure register IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO16.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA22.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA22.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI1_MISO. - Configure register IOMUXC_ECSPI1_MISO_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_TXFS. - Configure register IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO16.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT22.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT22.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_disp0_data23
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_disp0_data23_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_disp0_data23_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_ADDR      (REGS_IOMUXC_BASE + 0x1cc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23           (*(volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data23_t *) HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR(HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: DISP0_DAT23. NOTE: Pad DISP0_DAT23 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_DISP0_DATA23.
 * - ALT1 = 001 - Select signal IPU2_DISP0_DATA23.
 * - ALT2 = 010 - Select signal ECSPI1_SS0. - Configure register IOMUXC_ECSPI1_SS0_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal AUD4_RXD. - Configure register IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_DISP0_DATA23.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DISP0_DATA23.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI1_SS0. - Configure register IOMUXC_ECSPI1_SS0_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_RXD. - Configure register IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO17.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad DISP0_DAT23.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION(BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION__ENABLED (0x1) //!< Force input path of pad DISP0_DAT23.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_mdio
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_mdio_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_mdio_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_ADDR      (REGS_IOMUXC_BASE + 0x1d0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_mdio_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: ENET_MDIO. NOTE: Pad ENET_MDIO is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal ENET_MDIO. - Configure register IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal ESAI_RX_CLK. - Configure register IOMUXC_ESAI_RX_CLK_SELECT_INPUT for mode ALT2.
 * - ALT4 = 100 - Select signal ENET_1588_EVENT1_OUT.
 * - ALT5 = 101 - Select signal GPIO1_IO22.
 * - ALT6 = 110 - Select signal SPDIF_LOCK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_MDIO. - Configure register IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_RX_CLK. - Configure register IOMUXC_ESAI_RX_CLK_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE__ALT4 (0x4) //!< Select signal ENET_1588_EVENT1_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO22.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE__ALT6 (0x6) //!< Select signal SPDIF_LOCK.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_MDIO.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION__ENABLED (0x1) //!< Force input path of pad ENET_MDIO.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_ref_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_ref_clk_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_ref_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_ADDR      (REGS_IOMUXC_BASE + 0x1d4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_ref_clk_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: ENET_REF_CLK. NOTE: Pad ENET_REF_CLK is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal ENET_TX_CLK.
 * - ALT2 = 010 - Select signal ESAI_RX_FS. - Configure register IOMUXC_ESAI_RX_FS_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO1_IO23.
 * - ALT6 = 110 - Select signal SPDIF_SR_CLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_TX_CLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_RX_FS. - Configure register IOMUXC_ESAI_RX_FS_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO23.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE__ALT6 (0x6) //!< Select signal SPDIF_SR_CLK.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_REF_CLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION__ENABLED (0x1) //!< Force input path of pad ENET_REF_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_rx_er
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_rx_er_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_rx_er_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_ADDR      (REGS_IOMUXC_BASE + 0x1d8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_rx_er_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: ENET_RX_ER. NOTE: Pad ENET_RX_ER is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal USB_OTG_ID.
 * - ALT1 = 001 - Select signal ENET_RX_ER.
 * - ALT2 = 010 - Select signal ESAI_RX_HF_CLK. - Configure register IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal SPDIF_IN. - Configure register IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal ENET_1588_EVENT2_OUT.
 * - ALT5 = 101 - Select signal GPIO1_IO24.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE__ALT0 (0x0) //!< Select signal USB_OTG_ID.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_RX_ER.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_RX_HF_CLK. - Configure register IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE__ALT3 (0x3) //!< Select signal SPDIF_IN. - Configure register IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE__ALT4 (0x4) //!< Select signal ENET_1588_EVENT2_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO24.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_RX_ER.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER_SION__ENABLED (0x1) //!< Force input path of pad ENET_RX_ER.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_crs_dv
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_crs_dv_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_crs_dv_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_ADDR      (REGS_IOMUXC_BASE + 0x1dc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_crs_dv_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: ENET_CRS_DV. NOTE: Pad ENET_CRS_DV is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal ENET_RX_EN. - Configure register IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal ESAI_TX_CLK. - Configure register IOMUXC_ESAI_TX_CLK_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal SPDIF_EXT_CLK. - Configure register IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO1_IO25.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_RX_EN. - Configure register IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_TX_CLK. - Configure register IOMUXC_ESAI_TX_CLK_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE__ALT3 (0x3) //!< Select signal SPDIF_EXT_CLK. - Configure register IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO25.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_CRS_DV.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION__ENABLED (0x1) //!< Force input path of pad ENET_CRS_DV.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_rx_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_rx_data1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_rx_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x1e0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_rx_data1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: ENET_RXD1. NOTE: Pad ENET_RXD1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal MLB_SIG. - Configure register IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_RX_DATA1. - Configure register IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT for mode
 *     ALT1.
 * - ALT2 = 010 - Select signal ESAI_TX_FS. - Configure register IOMUXC_ESAI_TX_FS_SELECT_INPUT for mode ALT2.
 * - ALT4 = 100 - Select signal ENET_1588_EVENT3_OUT.
 * - ALT5 = 101 - Select signal GPIO1_IO26.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE__ALT0 (0x0) //!< Select signal MLB_SIG. - Configure register IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_RX_DATA1. - Configure register IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_TX_FS. - Configure register IOMUXC_ESAI_TX_FS_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE__ALT4 (0x4) //!< Select signal ENET_1588_EVENT3_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO26.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_RXD1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION__ENABLED (0x1) //!< Force input path of pad ENET_RXD1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_rx_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_rx_data0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_rx_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x1e4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_rx_data0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: ENET_RXD0. NOTE: Pad ENET_RXD0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal ENET_RX_DATA0. - Configure register IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT for mode
 *     ALT1.
 * - ALT2 = 010 - Select signal ESAI_TX_HF_CLK. - Configure register IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal SPDIF_OUT.
 * - ALT5 = 101 - Select signal GPIO1_IO27.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_RX_DATA0. - Configure register IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_TX_HF_CLK. - Configure register IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE__ALT3 (0x3) //!< Select signal SPDIF_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO27.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_RXD0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION__ENABLED (0x1) //!< Force input path of pad ENET_RXD0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_tx_en
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_tx_en_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_tx_en_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_ADDR      (REGS_IOMUXC_BASE + 0x1e8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_tx_en_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: ENET_TX_EN. NOTE: Pad ENET_TX_EN is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal ENET_TX_EN.
 * - ALT2 = 010 - Select signal ESAI_TX3_RX2. - Configure register IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO1_IO28.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_TX_EN.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_TX3_RX2. - Configure register IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO28.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_TX_EN.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION__ENABLED (0x1) //!< Force input path of pad ENET_TX_EN.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_tx_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_tx_data1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_tx_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x1ec)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_tx_data1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: ENET_TXD1. NOTE: Pad ENET_TXD1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal MLB_CLK. - Configure register IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_TX_DATA1.
 * - ALT2 = 010 - Select signal ESAI_TX2_RX3. - Configure register IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT for mode ALT2.
 * - ALT4 = 100 - Select signal ENET_1588_EVENT0_IN.
 * - ALT5 = 101 - Select signal GPIO1_IO29.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE__ALT0 (0x0) //!< Select signal MLB_CLK. - Configure register IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_TX_DATA1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_TX2_RX3. - Configure register IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE__ALT4 (0x4) //!< Select signal ENET_1588_EVENT0_IN.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO29.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_TXD1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION__ENABLED (0x1) //!< Force input path of pad ENET_TXD1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_tx_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_tx_data0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_tx_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x1f0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_tx_data0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: ENET_TXD0. NOTE: Pad ENET_TXD0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal ENET_TX_DATA0.
 * - ALT2 = 010 - Select signal ESAI_TX4_RX1. - Configure register IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO1_IO30.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_TX_DATA0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_TX4_RX1. - Configure register IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO30.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_TXD0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION__ENABLED (0x1) //!< Force input path of pad ENET_TXD0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_enet_mdc
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_enet_mdc_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_enet_mdc_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_ENET_MDC register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_ADDR      (REGS_IOMUXC_BASE + 0x1f4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC           (*(volatile hw_iomuxc_sw_mux_ctl_pad_enet_mdc_t *) HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_ENET_MDC bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_MDC, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: ENET_MDC. NOTE: Pad ENET_MDC is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal MLB_DATA. - Configure register IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_MDC.
 * - ALT2 = 010 - Select signal ESAI_TX5_RX0. - Configure register IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT for mode ALT2.
 * - ALT4 = 100 - Select signal ENET_1588_EVENT1_IN.
 * - ALT5 = 101 - Select signal GPIO1_IO31.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE__ALT0 (0x0) //!< Select signal MLB_DATA. - Configure register IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_MDC.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_TX5_RX0. - Configure register IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE__ALT4 (0x4) //!< Select signal ENET_1588_EVENT1_IN.
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO31.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_ENET_MDC, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad ENET_MDC.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION(BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION__ENABLED (0x1) //!< Force input path of pad ENET_MDC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_col0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_col0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_col0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_ADDR      (REGS_IOMUXC_BASE + 0x1f8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_col0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: KEY_COL0. NOTE: Pad KEY_COL0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ECSPI1_SCLK. - Configure register IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT for mode
 *     ALT0.
 * - ALT1 = 001 - Select signal ENET_RX_DATA3. - Configure register IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT for mode
 *     ALT1.
 * - ALT2 = 010 - Select signal AUD5_TXC. - Configure register IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_COL0.
 * - ALT4 = 100 - Select signal UART4_TX_DATA. - Configure register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO4_IO06.
 * - ALT6 = 110 - Select signal DCIC1_OUT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE__ALT0 (0x0) //!< Select signal ECSPI1_SCLK. - Configure register IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_RX_DATA3. - Configure register IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE__ALT2 (0x2) //!< Select signal AUD5_TXC. - Configure register IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_COL0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE__ALT4 (0x4) //!< Select signal UART4_TX_DATA. - Configure register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE__ALT6 (0x6) //!< Select signal DCIC1_OUT.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_COL0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION__ENABLED (0x1) //!< Force input path of pad KEY_COL0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_row0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_row0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_row0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_ADDR      (REGS_IOMUXC_BASE + 0x1fc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_row0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: KEY_ROW0. NOTE: Pad KEY_ROW0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ECSPI1_MOSI. - Configure register IOMUXC_ECSPI1_MOSI_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_TX_DATA3.
 * - ALT2 = 010 - Select signal AUD5_TXD. - Configure register IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_ROW0.
 * - ALT4 = 100 - Select signal UART4_RX_DATA. - Configure register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO4_IO07.
 * - ALT6 = 110 - Select signal DCIC2_OUT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE__ALT0 (0x0) //!< Select signal ECSPI1_MOSI. - Configure register IOMUXC_ECSPI1_MOSI_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_TX_DATA3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE__ALT2 (0x2) //!< Select signal AUD5_TXD. - Configure register IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_ROW0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE__ALT4 (0x4) //!< Select signal UART4_RX_DATA. - Configure register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE__ALT6 (0x6) //!< Select signal DCIC2_OUT.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_ROW0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION__ENABLED (0x1) //!< Force input path of pad KEY_ROW0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_col1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_col1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_col1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_ADDR      (REGS_IOMUXC_BASE + 0x200)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_col1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: KEY_COL1. NOTE: Pad KEY_COL1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ECSPI1_MISO. - Configure register IOMUXC_ECSPI1_MISO_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_MDIO. - Configure register IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal AUD5_TXFS. - Configure register IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_COL1.
 * - ALT4 = 100 - Select signal UART5_TX_DATA. - Configure register IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO4_IO08.
 * - ALT6 = 110 - Select signal SD1_VSELECT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE__ALT0 (0x0) //!< Select signal ECSPI1_MISO. - Configure register IOMUXC_ECSPI1_MISO_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_MDIO. - Configure register IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE__ALT2 (0x2) //!< Select signal AUD5_TXFS. - Configure register IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_COL1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE__ALT4 (0x4) //!< Select signal UART5_TX_DATA. - Configure register IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE__ALT6 (0x6) //!< Select signal SD1_VSELECT.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_COL1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION__ENABLED (0x1) //!< Force input path of pad KEY_COL1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_row1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_row1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_row1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_ADDR      (REGS_IOMUXC_BASE + 0x204)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_row1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: KEY_ROW1. NOTE: Pad KEY_ROW1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ECSPI1_SS0. - Configure register IOMUXC_ECSPI1_SS0_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_COL.
 * - ALT2 = 010 - Select signal AUD5_RXD. - Configure register IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_ROW1.
 * - ALT4 = 100 - Select signal UART5_RX_DATA. - Configure register IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO4_IO09.
 * - ALT6 = 110 - Select signal SD2_VSELECT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE__ALT0 (0x0) //!< Select signal ECSPI1_SS0. - Configure register IOMUXC_ECSPI1_SS0_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_COL.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE__ALT2 (0x2) //!< Select signal AUD5_RXD. - Configure register IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_ROW1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE__ALT4 (0x4) //!< Select signal UART5_RX_DATA. - Configure register IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE__ALT6 (0x6) //!< Select signal SD2_VSELECT.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_ROW1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION__ENABLED (0x1) //!< Force input path of pad KEY_ROW1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_col2
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_col2_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_col2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_ADDR      (REGS_IOMUXC_BASE + 0x208)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_col2_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL2, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: KEY_COL2. NOTE: Pad KEY_COL2 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ECSPI1_SS1. - Configure register IOMUXC_ECSPI1_SS1_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_RX_DATA2. - Configure register IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT for mode
 *     ALT1.
 * - ALT2 = 010 - Select signal FLEXCAN1_TX.
 * - ALT3 = 011 - Select signal KEY_COL2.
 * - ALT4 = 100 - Select signal ENET_MDC.
 * - ALT5 = 101 - Select signal GPIO4_IO10.
 * - ALT6 = 110 - Select signal USB_H1_PWR_CTL_WAKE.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE__ALT0 (0x0) //!< Select signal ECSPI1_SS1. - Configure register IOMUXC_ECSPI1_SS1_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_RX_DATA2. - Configure register IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE__ALT2 (0x2) //!< Select signal FLEXCAN1_TX.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_COL2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE__ALT4 (0x4) //!< Select signal ENET_MDC.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO10.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE__ALT6 (0x6) //!< Select signal USB_H1_PWR_CTL_WAKE.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL2, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_COL2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION__ENABLED (0x1) //!< Force input path of pad KEY_COL2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_row2
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_row2_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_row2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_ADDR      (REGS_IOMUXC_BASE + 0x20c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_row2_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: KEY_ROW2. NOTE: Pad KEY_ROW2 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ECSPI1_SS2. - Configure register IOMUXC_ECSPI1_SS2_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_TX_DATA2.
 * - ALT2 = 010 - Select signal FLEXCAN1_RX. - Configure register IOMUXC_FLEXCAN1_RX_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_ROW2.
 * - ALT4 = 100 - Select signal SD2_VSELECT.
 * - ALT5 = 101 - Select signal GPIO4_IO11.
 * - ALT6 = 110 - Select signal HDMI_TX_CEC_LINE. - Configure register IOMUXC_HDMI_ICECIN_SELECT_INPUT for mode ALT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE__ALT0 (0x0) //!< Select signal ECSPI1_SS2. - Configure register IOMUXC_ECSPI1_SS2_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_TX_DATA2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE__ALT2 (0x2) //!< Select signal FLEXCAN1_RX. - Configure register IOMUXC_FLEXCAN1_RX_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_ROW2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE__ALT4 (0x4) //!< Select signal SD2_VSELECT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE__ALT6 (0x6) //!< Select signal HDMI_TX_CEC_LINE. - Configure register IOMUXC_HDMI_ICECIN_SELECT_INPUT for mode ALT6.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_ROW2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION__ENABLED (0x1) //!< Force input path of pad KEY_ROW2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_col3
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_col3_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_col3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_ADDR      (REGS_IOMUXC_BASE + 0x210)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_col3_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL3, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: KEY_COL3. NOTE: Pad KEY_COL3 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ECSPI1_SS3. - Configure register IOMUXC_ECSPI1_SS3_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_CRS.
 * - ALT2 = 010 - Select signal HDMI_TX_DDC_SCL. - Configure register IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal KEY_COL3.
 * - ALT4 = 100 - Select signal I2C2_SCL. - Configure register IOMUXC_I2C2_SCL_IN_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO4_IO12.
 * - ALT6 = 110 - Select signal SPDIF_IN. - Configure register IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT for mode ALT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE__ALT0 (0x0) //!< Select signal ECSPI1_SS3. - Configure register IOMUXC_ECSPI1_SS3_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_CRS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE__ALT2 (0x2) //!< Select signal HDMI_TX_DDC_SCL. - Configure register IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_COL3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE__ALT4 (0x4) //!< Select signal I2C2_SCL. - Configure register IOMUXC_I2C2_SCL_IN_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE__ALT6 (0x6) //!< Select signal SPDIF_IN. - Configure register IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT for mode ALT6.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL3, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_COL3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION__ENABLED (0x1) //!< Force input path of pad KEY_COL3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_row3
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_row3_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_row3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_ADDR      (REGS_IOMUXC_BASE + 0x214)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_row3_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: KEY_ROW3. NOTE: Pad KEY_ROW3 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal ASRC_EXT_CLK. - Configure register IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT for mode
 *     ALT1.
 * - ALT2 = 010 - Select signal HDMI_TX_DDC_SDA. - Configure register IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal KEY_ROW3.
 * - ALT4 = 100 - Select signal I2C2_SDA. - Configure register IOMUXC_I2C2_SDA_IN_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO4_IO13.
 * - ALT6 = 110 - Select signal SD1_VSELECT.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE__ALT1 (0x1) //!< Select signal ASRC_EXT_CLK. - Configure register IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE__ALT2 (0x2) //!< Select signal HDMI_TX_DDC_SDA. - Configure register IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_ROW3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE__ALT4 (0x4) //!< Select signal I2C2_SDA. - Configure register IOMUXC_I2C2_SDA_IN_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE__ALT6 (0x6) //!< Select signal SD1_VSELECT.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_ROW3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION__ENABLED (0x1) //!< Force input path of pad KEY_ROW3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_col4
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_col4_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_col4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_ADDR      (REGS_IOMUXC_BASE + 0x218)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_col4_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL4, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: KEY_COL4. NOTE: Pad KEY_COL4 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal FLEXCAN2_TX.
 * - ALT1 = 001 - Select signal IPU1_SISG4.
 * - ALT2 = 010 - Select signal USB_OTG_OC. - Configure register IOMUXC_USB_OTG_OC_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_COL4.
 * - ALT4 = 100 - Select signal UART5_RTS_B. - Configure register IOMUXC_UART5_UART_RTS_B_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO4_IO14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE__ALT0 (0x0) //!< Select signal FLEXCAN2_TX.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_SISG4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE__ALT2 (0x2) //!< Select signal USB_OTG_OC. - Configure register IOMUXC_USB_OTG_OC_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_COL4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE__ALT4 (0x4) //!< Select signal UART5_RTS_B. - Configure register IOMUXC_UART5_UART_RTS_B_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO14.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_COL4, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_COL4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION__ENABLED (0x1) //!< Force input path of pad KEY_COL4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_key_row4
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_key_row4_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_key_row4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_ADDR      (REGS_IOMUXC_BASE + 0x21c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4           (*(volatile hw_iomuxc_sw_mux_ctl_pad_key_row4_t *) HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: KEY_ROW4. NOTE: Pad KEY_ROW4 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal FLEXCAN2_RX. - Configure register IOMUXC_FLEXCAN2_RX_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal IPU1_SISG5.
 * - ALT2 = 010 - Select signal USB_OTG_PWR.
 * - ALT3 = 011 - Select signal KEY_ROW4.
 * - ALT4 = 100 - Select signal UART5_CTS_B. - Configure register IOMUXC_UART5_UART_RTS_B_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO4_IO15.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE__ALT0 (0x0) //!< Select signal FLEXCAN2_RX. - Configure register IOMUXC_FLEXCAN2_RX_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_SISG5.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE__ALT2 (0x2) //!< Select signal USB_OTG_PWR.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_ROW4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE__ALT4 (0x4) //!< Select signal UART5_CTS_B. - Configure register IOMUXC_UART5_UART_RTS_B_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO15.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad KEY_ROW4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION__ENABLED (0x1) //!< Force input path of pad KEY_ROW4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio00
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio00_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio00_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO00 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_ADDR      (REGS_IOMUXC_BASE + 0x220)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio00_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO00 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO00, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: GPIO_0. NOTE: Pad GPIO_0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal CCM_CLKO1.
 * - ALT2 = 010 - Select signal KEY_COL5. - Configure register IOMUXC_KEY_COL5_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal ASRC_EXT_CLK. - Configure register IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT for mode
 *     ALT3.
 * - ALT4 = 100 - Select signal EPIT1_OUT.
 * - ALT5 = 101 - Select signal GPIO1_IO00.
 * - ALT6 = 110 - Select signal USB_H1_PWR.
 * - ALT7 = 111 - Select signal SNVS_VIO_5.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__ALT0 (0x0) //!< Select signal CCM_CLKO1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__ALT2 (0x2) //!< Select signal KEY_COL5. - Configure register IOMUXC_KEY_COL5_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__ALT3 (0x3) //!< Select signal ASRC_EXT_CLK. - Configure register IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__ALT4 (0x4) //!< Select signal EPIT1_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__ALT6 (0x6) //!< Select signal USB_H1_PWR.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__ALT7 (0x7) //!< Select signal SNVS_VIO_5.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO00, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION__ENABLED (0x1) //!< Force input path of pad GPIO_0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio01
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio01_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio01_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO01 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_ADDR      (REGS_IOMUXC_BASE + 0x224)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio01_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO01 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO01, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: GPIO_1. NOTE: Pad GPIO_1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_RX_CLK. - Configure register IOMUXC_ESAI_RX_CLK_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal WDOG2_B.
 * - ALT2 = 010 - Select signal KEY_ROW5. - Configure register IOMUXC_KEY_ROW5_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal USB_OTG_ID.
 * - ALT4 = 100 - Select signal PWM2_OUT.
 * - ALT5 = 101 - Select signal GPIO1_IO01.
 * - ALT6 = 110 - Select signal SD1_CD_B.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_RX_CLK. - Configure register IOMUXC_ESAI_RX_CLK_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE__ALT1 (0x1) //!< Select signal WDOG2_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE__ALT2 (0x2) //!< Select signal KEY_ROW5. - Configure register IOMUXC_KEY_ROW5_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE__ALT3 (0x3) //!< Select signal USB_OTG_ID.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE__ALT4 (0x4) //!< Select signal PWM2_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE__ALT6 (0x6) //!< Select signal SD1_CD_B.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO01, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION__ENABLED (0x1) //!< Force input path of pad GPIO_1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio09
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio09_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio09_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO09 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_ADDR      (REGS_IOMUXC_BASE + 0x228)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio09_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO09 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO09, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: GPIO_9. NOTE: Pad GPIO_9 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_RX_FS. - Configure register IOMUXC_ESAI_RX_FS_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal WDOG1_B.
 * - ALT2 = 010 - Select signal KEY_COL6. - Configure register IOMUXC_KEY_COL6_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal CCM_REF_EN_B.
 * - ALT4 = 100 - Select signal PWM1_OUT.
 * - ALT5 = 101 - Select signal GPIO1_IO09.
 * - ALT6 = 110 - Select signal SD1_WP. - Configure register IOMUXC_USDHC1_WP_ON_SELECT_INPUT for mode ALT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_RX_FS. - Configure register IOMUXC_ESAI_RX_FS_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE__ALT1 (0x1) //!< Select signal WDOG1_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE__ALT2 (0x2) //!< Select signal KEY_COL6. - Configure register IOMUXC_KEY_COL6_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE__ALT3 (0x3) //!< Select signal CCM_REF_EN_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE__ALT4 (0x4) //!< Select signal PWM1_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE__ALT6 (0x6) //!< Select signal SD1_WP. - Configure register IOMUXC_USDHC1_WP_ON_SELECT_INPUT for mode ALT6.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO09, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_9.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION__ENABLED (0x1) //!< Force input path of pad GPIO_9.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio03
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio03_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO03 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_ADDR      (REGS_IOMUXC_BASE + 0x22c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio03_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO03 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO03, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: GPIO_3. NOTE: Pad GPIO_3 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_RX_HF_CLK. - Configure register IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT for mode ALT0.
 * - ALT2 = 010 - Select signal I2C3_SCL. - Configure register IOMUXC_I2C3_SCL_IN_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal XTALOSC_REF_CLK_24M.
 * - ALT4 = 100 - Select signal CCM_CLKO2.
 * - ALT5 = 101 - Select signal GPIO1_IO03.
 * - ALT6 = 110 - Select signal USB_H1_OC. - Configure register IOMUXC_USB_H1_OC_SELECT_INPUT for mode ALT6.
 * - ALT7 = 111 - Select signal MLB_CLK. - Configure register IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT for mode ALT7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_RX_HF_CLK. - Configure register IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE__ALT2 (0x2) //!< Select signal I2C3_SCL. - Configure register IOMUXC_I2C3_SCL_IN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE__ALT3 (0x3) //!< Select signal XTALOSC_REF_CLK_24M.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE__ALT4 (0x4) //!< Select signal CCM_CLKO2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE__ALT6 (0x6) //!< Select signal USB_H1_OC. - Configure register IOMUXC_USB_H1_OC_SELECT_INPUT for mode ALT6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE__ALT7 (0x7) //!< Select signal MLB_CLK. - Configure register IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT for mode ALT7.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO03, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION__ENABLED (0x1) //!< Force input path of pad GPIO_3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio06
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio06_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO06 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_ADDR      (REGS_IOMUXC_BASE + 0x230)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio06_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO06 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO06, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: GPIO_6. NOTE: Pad GPIO_6 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_TX_CLK. - Configure register IOMUXC_ESAI_TX_CLK_SELECT_INPUT for mode ALT0.
 * - ALT2 = 010 - Select signal I2C3_SDA. - Configure register IOMUXC_I2C3_SDA_IN_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO1_IO06.
 * - ALT6 = 110 - Select signal SD2_LCTL.
 * - ALT7 = 111 - Select signal MLB_SIG. - Configure register IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT for mode ALT7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_TX_CLK. - Configure register IOMUXC_ESAI_TX_CLK_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE__ALT2 (0x2) //!< Select signal I2C3_SDA. - Configure register IOMUXC_I2C3_SDA_IN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE__ALT6 (0x6) //!< Select signal SD2_LCTL.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE__ALT7 (0x7) //!< Select signal MLB_SIG. - Configure register IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT for mode ALT7.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO06, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION__ENABLED (0x1) //!< Force input path of pad GPIO_6.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio02
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio02_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO02 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_ADDR      (REGS_IOMUXC_BASE + 0x234)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio02_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO02 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO02, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: GPIO_2. NOTE: Pad GPIO_2 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_TX_FS. - Configure register IOMUXC_ESAI_TX_FS_SELECT_INPUT for mode ALT0.
 * - ALT2 = 010 - Select signal KEY_ROW6. - Configure register IOMUXC_KEY_ROW6_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO1_IO02.
 * - ALT6 = 110 - Select signal SD2_WP.
 * - ALT7 = 111 - Select signal MLB_DATA. - Configure register IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT for mode ALT7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_TX_FS. - Configure register IOMUXC_ESAI_TX_FS_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE__ALT2 (0x2) //!< Select signal KEY_ROW6. - Configure register IOMUXC_KEY_ROW6_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE__ALT6 (0x6) //!< Select signal SD2_WP.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE__ALT7 (0x7) //!< Select signal MLB_DATA. - Configure register IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT for mode ALT7.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO02, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION__ENABLED (0x1) //!< Force input path of pad GPIO_2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio04
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio04_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO04 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_ADDR      (REGS_IOMUXC_BASE + 0x238)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio04_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO04 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO04, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: GPIO_4. NOTE: Pad GPIO_4 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_TX_HF_CLK. - Configure register IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT for mode ALT0.
 * - ALT2 = 010 - Select signal KEY_COL7. - Configure register IOMUXC_KEY_COL7_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO1_IO04.
 * - ALT6 = 110 - Select signal SD2_CD_B.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_TX_HF_CLK. - Configure register IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE__ALT2 (0x2) //!< Select signal KEY_COL7. - Configure register IOMUXC_KEY_COL7_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE__ALT6 (0x6) //!< Select signal SD2_CD_B.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO04, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION__ENABLED (0x1) //!< Force input path of pad GPIO_4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio05
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio05_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO05 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_ADDR      (REGS_IOMUXC_BASE + 0x23c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio05_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO05 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO05, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: GPIO_5. NOTE: Pad GPIO_5 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_TX2_RX3. - Configure register IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT for mode ALT0.
 * - ALT2 = 010 - Select signal KEY_ROW7. - Configure register IOMUXC_KEY_ROW7_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal CCM_CLKO1.
 * - ALT5 = 101 - Select signal GPIO1_IO05.
 * - ALT6 = 110 - Select signal I2C3_SCL. - Configure register IOMUXC_I2C3_SCL_IN_SELECT_INPUT for mode ALT6.
 * - ALT7 = 111 - Select signal ARM_EVENTI.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_TX2_RX3. - Configure register IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE__ALT2 (0x2) //!< Select signal KEY_ROW7. - Configure register IOMUXC_KEY_ROW7_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE__ALT3 (0x3) //!< Select signal CCM_CLKO1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE__ALT6 (0x6) //!< Select signal I2C3_SCL. - Configure register IOMUXC_I2C3_SCL_IN_SELECT_INPUT for mode ALT6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_EVENTI.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO05, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_5.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION__ENABLED (0x1) //!< Force input path of pad GPIO_5.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio07
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio07_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO07 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_ADDR      (REGS_IOMUXC_BASE + 0x240)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio07_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO07 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO07, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: GPIO_7. NOTE: Pad GPIO_7 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_TX4_RX1. - Configure register IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ECSPI5_RDY.
 * - ALT2 = 010 - Select signal EPIT1_OUT.
 * - ALT3 = 011 - Select signal FLEXCAN1_TX.
 * - ALT4 = 100 - Select signal UART2_TX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO1_IO07.
 * - ALT6 = 110 - Select signal SPDIF_LOCK.
 * - ALT7 = 111 - Select signal USB_OTG_HOST_MODE.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_TX4_RX1. - Configure register IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_RDY.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE__ALT2 (0x2) //!< Select signal EPIT1_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE__ALT3 (0x3) //!< Select signal FLEXCAN1_TX.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE__ALT4 (0x4) //!< Select signal UART2_TX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE__ALT6 (0x6) //!< Select signal SPDIF_LOCK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE__ALT7 (0x7) //!< Select signal USB_OTG_HOST_MODE.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO07, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION__ENABLED (0x1) //!< Force input path of pad GPIO_7.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio08
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio08_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio08_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO08 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_ADDR      (REGS_IOMUXC_BASE + 0x244)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio08_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO08 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO08, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: GPIO_8. NOTE: Pad GPIO_8 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_TX5_RX0. - Configure register IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal XTALOSC_REF_CLK_32K.
 * - ALT2 = 010 - Select signal EPIT2_OUT.
 * - ALT3 = 011 - Select signal FLEXCAN1_RX. - Configure register IOMUXC_FLEXCAN1_RX_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal UART2_RX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO1_IO08.
 * - ALT6 = 110 - Select signal SPDIF_SR_CLK.
 * - ALT7 = 111 - Select signal USB_OTG_PWR_CTL_WAKE.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_TX5_RX0. - Configure register IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE__ALT1 (0x1) //!< Select signal XTALOSC_REF_CLK_32K.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE__ALT2 (0x2) //!< Select signal EPIT2_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE__ALT3 (0x3) //!< Select signal FLEXCAN1_RX. - Configure register IOMUXC_FLEXCAN1_RX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE__ALT4 (0x4) //!< Select signal UART2_RX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE__ALT6 (0x6) //!< Select signal SPDIF_SR_CLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE__ALT7 (0x7) //!< Select signal USB_OTG_PWR_CTL_WAKE.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO08, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_8.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION__ENABLED (0x1) //!< Force input path of pad GPIO_8.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio16
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio16_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO16 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_ADDR      (REGS_IOMUXC_BASE + 0x248)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio16_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO16 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO16, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 8 iomux modes to be used for pad: GPIO_16. NOTE: Pad GPIO_16 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_TX3_RX2. - Configure register IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_1588_EVENT2_IN.
 * - ALT2 = 010 - Select signal ENET_REF_CLK. - Configure register IOMUXC_ENET_REF_CLK_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal SD1_LCTL.
 * - ALT4 = 100 - Select signal SPDIF_IN. - Configure register IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO7_IO11.
 * - ALT6 = 110 - Select signal I2C3_SDA. - Configure register IOMUXC_I2C3_SDA_IN_SELECT_INPUT for mode ALT6.
 * - ALT7 = 111 - Select signal JTAG_DE_B.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_TX3_RX2. - Configure register IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_1588_EVENT2_IN.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE__ALT2 (0x2) //!< Select signal ENET_REF_CLK. - Configure register IOMUXC_ENET_REF_CLK_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE__ALT3 (0x3) //!< Select signal SD1_LCTL.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE__ALT4 (0x4) //!< Select signal SPDIF_IN. - Configure register IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE__ALT6 (0x6) //!< Select signal I2C3_SDA. - Configure register IOMUXC_I2C3_SDA_IN_SELECT_INPUT for mode ALT6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_MUX_MODE__ALT7 (0x7) //!< Select signal JTAG_DE_B.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO16, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_16.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO16_SION__ENABLED (0x1) //!< Force input path of pad GPIO_16.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio17
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio17_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO17 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_ADDR      (REGS_IOMUXC_BASE + 0x24c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio17_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO17 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO17, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: GPIO_17. NOTE: Pad GPIO_17 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_TX0. - Configure register IOMUXC_ESAI_SDO0_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_1588_EVENT3_IN.
 * - ALT2 = 010 - Select signal CCM_PMIC_READY. - Configure register IOMUXC_CCM_PMIC_READY_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal SDMA_EXT_EVENT0. - Configure register IOMUXC_SDMA_EVENTS14_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal SPDIF_OUT.
 * - ALT5 = 101 - Select signal GPIO7_IO12.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_TX0. - Configure register IOMUXC_ESAI_SDO0_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_1588_EVENT3_IN.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE__ALT2 (0x2) //!< Select signal CCM_PMIC_READY. - Configure register IOMUXC_CCM_PMIC_READY_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE__ALT3 (0x3) //!< Select signal SDMA_EXT_EVENT0. - Configure register IOMUXC_SDMA_EVENTS14_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE__ALT4 (0x4) //!< Select signal SPDIF_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO12.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO17, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION__ENABLED (0x1) //!< Force input path of pad GPIO_17.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio18
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio18_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO18 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_ADDR      (REGS_IOMUXC_BASE + 0x250)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio18_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO18 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO18, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: GPIO_18. NOTE: Pad GPIO_18 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal ESAI_TX1. - Configure register IOMUXC_ESAI_SDO1_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_RX_CLK. - Configure register IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal SD3_VSELECT.
 * - ALT3 = 011 - Select signal SDMA_EXT_EVENT1. - Configure register IOMUXC_SDMA_EVENTS15_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal ASRC_EXT_CLK. - Configure register IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT for mode
 *     ALT4.
 * - ALT5 = 101 - Select signal GPIO7_IO13.
 * - ALT6 = 110 - Select signal SNVS_VIO_5_CTL.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE__ALT0 (0x0) //!< Select signal ESAI_TX1. - Configure register IOMUXC_ESAI_SDO1_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_RX_CLK. - Configure register IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE__ALT2 (0x2) //!< Select signal SD3_VSELECT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE__ALT3 (0x3) //!< Select signal SDMA_EXT_EVENT1. - Configure register IOMUXC_SDMA_EVENTS15_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE__ALT4 (0x4) //!< Select signal ASRC_EXT_CLK. - Configure register IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE__ALT6 (0x6) //!< Select signal SNVS_VIO_5_CTL.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO18, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_18.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION__ENABLED (0x1) //!< Force input path of pad GPIO_18.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_gpio19
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_gpio19_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_gpio19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_GPIO19 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_ADDR      (REGS_IOMUXC_BASE + 0x254)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19           (*(volatile hw_iomuxc_sw_mux_ctl_pad_gpio19_t *) HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_GPIO19 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO19, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: GPIO_19. NOTE: Pad GPIO_19 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal KEY_COL5. - Configure register IOMUXC_KEY_COL5_SELECT_INPUT for mode ALT0.
 * - ALT1 = 001 - Select signal ENET_1588_EVENT0_OUT.
 * - ALT2 = 010 - Select signal SPDIF_OUT.
 * - ALT3 = 011 - Select signal CCM_CLKO1.
 * - ALT4 = 100 - Select signal ECSPI1_RDY.
 * - ALT5 = 101 - Select signal GPIO4_IO05.
 * - ALT6 = 110 - Select signal ENET_TX_ER.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE__ALT0 (0x0) //!< Select signal KEY_COL5. - Configure register IOMUXC_KEY_COL5_SELECT_INPUT for mode ALT0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE__ALT1 (0x1) //!< Select signal ENET_1588_EVENT0_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE__ALT2 (0x2) //!< Select signal SPDIF_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE__ALT3 (0x3) //!< Select signal CCM_CLKO1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE__ALT4 (0x4) //!< Select signal ECSPI1_RDY.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO4_IO05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE__ALT6 (0x6) //!< Select signal ENET_TX_ER.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_GPIO19, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad GPIO_19.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION__ENABLED (0x1) //!< Force input path of pad GPIO_19.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_pixclk
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_pixclk_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_pixclk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_ADDR      (REGS_IOMUXC_BASE + 0x258)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_pixclk_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: CSI0_PIXCLK.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_PIXCLK.
 * - ALT5 = 101 - Select signal GPIO5_IO18.
 * - ALT7 = 111 - Select signal ARM_EVENTO.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_PIXCLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO18.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_EVENTO.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_PIXCLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION__ENABLED (0x1) //!< Force input path of pad CSI0_PIXCLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_hsync
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_hsync_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_hsync_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_ADDR      (REGS_IOMUXC_BASE + 0x25c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_hsync_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: CSI0_MCLK.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_HSYNC.
 * - ALT3 = 011 - Select signal CCM_CLKO1.
 * - ALT5 = 101 - Select signal GPIO5_IO19.
 * - ALT7 = 111 - Select signal ARM_TRACE_CTL.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_HSYNC.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE__ALT3 (0x3) //!< Select signal CCM_CLKO1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE_CTL.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_MCLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION__ENABLED (0x1) //!< Force input path of pad CSI0_MCLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data_en
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data_en_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data_en_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_ADDR      (REGS_IOMUXC_BASE + 0x260)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data_en_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: CSI0_DATA_EN.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA_EN.
 * - ALT1 = 001 - Select signal EIM_DATA00.
 * - ALT5 = 101 - Select signal GPIO5_IO20.
 * - ALT7 = 111 - Select signal ARM_TRACE_CLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA_EN.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO20.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE_CLK.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DATA_EN.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DATA_EN.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_vsync
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_vsync_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_vsync_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_ADDR      (REGS_IOMUXC_BASE + 0x264)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_vsync_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: CSI0_VSYNC.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_VSYNC.
 * - ALT1 = 001 - Select signal EIM_DATA01.
 * - ALT5 = 101 - Select signal GPIO5_IO21.
 * - ALT7 = 111 - Select signal ARM_TRACE00.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_VSYNC.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO21.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE00.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_VSYNC.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION__ENABLED (0x1) //!< Force input path of pad CSI0_VSYNC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data04
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data04_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_ADDR      (REGS_IOMUXC_BASE + 0x268)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data04_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: CSI0_DAT4. NOTE: Pad CSI0_DAT4 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA04.
 * - ALT1 = 001 - Select signal EIM_DATA02.
 * - ALT2 = 010 - Select signal ECSPI1_SCLK. - Configure register IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal KEY_COL5. - Configure register IOMUXC_KEY_COL5_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal AUD3_TXC.
 * - ALT5 = 101 - Select signal GPIO5_IO22.
 * - ALT7 = 111 - Select signal ARM_TRACE01.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI1_SCLK. - Configure register IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_COL5. - Configure register IOMUXC_KEY_COL5_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE__ALT4 (0x4) //!< Select signal AUD3_TXC.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO22.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE01.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data05
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data05_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_ADDR      (REGS_IOMUXC_BASE + 0x26c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data05_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: CSI0_DAT5. NOTE: Pad CSI0_DAT5 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA05.
 * - ALT1 = 001 - Select signal EIM_DATA03.
 * - ALT2 = 010 - Select signal ECSPI1_MOSI. - Configure register IOMUXC_ECSPI1_MOSI_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_ROW5. - Configure register IOMUXC_KEY_ROW5_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal AUD3_TXD.
 * - ALT5 = 101 - Select signal GPIO5_IO23.
 * - ALT7 = 111 - Select signal ARM_TRACE02.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI1_MOSI. - Configure register IOMUXC_ECSPI1_MOSI_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_ROW5. - Configure register IOMUXC_KEY_ROW5_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE__ALT4 (0x4) //!< Select signal AUD3_TXD.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO23.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE02.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT5.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT5.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data06
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data06_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_ADDR      (REGS_IOMUXC_BASE + 0x270)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data06_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: CSI0_DAT6. NOTE: Pad CSI0_DAT6 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA06.
 * - ALT1 = 001 - Select signal EIM_DATA04.
 * - ALT2 = 010 - Select signal ECSPI1_MISO. - Configure register IOMUXC_ECSPI1_MISO_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_COL6. - Configure register IOMUXC_KEY_COL6_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal AUD3_TXFS.
 * - ALT5 = 101 - Select signal GPIO5_IO24.
 * - ALT7 = 111 - Select signal ARM_TRACE03.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI1_MISO. - Configure register IOMUXC_ECSPI1_MISO_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_COL6. - Configure register IOMUXC_KEY_COL6_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE__ALT4 (0x4) //!< Select signal AUD3_TXFS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO24.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE03.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT6.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data07
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data07_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_ADDR      (REGS_IOMUXC_BASE + 0x274)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data07_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: CSI0_DAT7. NOTE: Pad CSI0_DAT7 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA07.
 * - ALT1 = 001 - Select signal EIM_DATA05.
 * - ALT2 = 010 - Select signal ECSPI1_SS0. - Configure register IOMUXC_ECSPI1_SS0_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_ROW6. - Configure register IOMUXC_KEY_ROW6_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal AUD3_RXD.
 * - ALT5 = 101 - Select signal GPIO5_IO25.
 * - ALT7 = 111 - Select signal ARM_TRACE04.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI1_SS0. - Configure register IOMUXC_ECSPI1_SS0_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_ROW6. - Configure register IOMUXC_KEY_ROW6_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE__ALT4 (0x4) //!< Select signal AUD3_RXD.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO25.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE04.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT7.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data08
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data08_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data08_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_ADDR      (REGS_IOMUXC_BASE + 0x278)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data08_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: CSI0_DAT8. NOTE: Pad CSI0_DAT8 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA08.
 * - ALT1 = 001 - Select signal EIM_DATA06.
 * - ALT2 = 010 - Select signal ECSPI2_SCLK. - Configure register IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT for mode
 *     ALT2.
 * - ALT3 = 011 - Select signal KEY_COL7. - Configure register IOMUXC_KEY_COL7_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal I2C1_SDA. - Configure register IOMUXC_I2C1_SDA_IN_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO5_IO26.
 * - ALT7 = 111 - Select signal ARM_TRACE05.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_SCLK. - Configure register IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_COL7. - Configure register IOMUXC_KEY_COL7_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE__ALT4 (0x4) //!< Select signal I2C1_SDA. - Configure register IOMUXC_I2C1_SDA_IN_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO26.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE05.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT8.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT8.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data09
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data09_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data09_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_ADDR      (REGS_IOMUXC_BASE + 0x27c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data09_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: CSI0_DAT9. NOTE: Pad CSI0_DAT9 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA09.
 * - ALT1 = 001 - Select signal EIM_DATA07.
 * - ALT2 = 010 - Select signal ECSPI2_MOSI. - Configure register IOMUXC_ECSPI2_MOSI_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal KEY_ROW7. - Configure register IOMUXC_KEY_ROW7_SELECT_INPUT for mode ALT3.
 * - ALT4 = 100 - Select signal I2C1_SCL. - Configure register IOMUXC_I2C1_SCL_IN_SELECT_INPUT for mode ALT4.
 * - ALT5 = 101 - Select signal GPIO5_IO27.
 * - ALT7 = 111 - Select signal ARM_TRACE06.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_MOSI. - Configure register IOMUXC_ECSPI2_MOSI_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE__ALT3 (0x3) //!< Select signal KEY_ROW7. - Configure register IOMUXC_KEY_ROW7_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE__ALT4 (0x4) //!< Select signal I2C1_SCL. - Configure register IOMUXC_I2C1_SCL_IN_SELECT_INPUT for mode ALT4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO27.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE06.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT9.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT9.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data10
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data10_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data10_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_ADDR      (REGS_IOMUXC_BASE + 0x280)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data10_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: CSI0_DAT10. NOTE: Pad CSI0_DAT10 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA10.
 * - ALT1 = 001 - Select signal AUD3_RXC.
 * - ALT2 = 010 - Select signal ECSPI2_MISO. - Configure register IOMUXC_ECSPI2_MISO_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal UART1_TX_DATA. - Configure register IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO28.
 * - ALT7 = 111 - Select signal ARM_TRACE07.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA10.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE__ALT1 (0x1) //!< Select signal AUD3_RXC.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_MISO. - Configure register IOMUXC_ECSPI2_MISO_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE__ALT3 (0x3) //!< Select signal UART1_TX_DATA. - Configure register IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO28.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE07.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT10.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data11
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data11_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data11_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_ADDR      (REGS_IOMUXC_BASE + 0x284)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data11_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: CSI0_DAT11. NOTE: Pad CSI0_DAT11 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA11.
 * - ALT1 = 001 - Select signal AUD3_RXFS.
 * - ALT2 = 010 - Select signal ECSPI2_SS0. - Configure register IOMUXC_ECSPI2_SS0_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal UART1_RX_DATA. - Configure register IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO29.
 * - ALT7 = 111 - Select signal ARM_TRACE08.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE__ALT1 (0x1) //!< Select signal AUD3_RXFS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE__ALT2 (0x2) //!< Select signal ECSPI2_SS0. - Configure register IOMUXC_ECSPI2_SS0_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE__ALT3 (0x3) //!< Select signal UART1_RX_DATA. - Configure register IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO29.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE08.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT11.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT11.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data12
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data12_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data12_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_ADDR      (REGS_IOMUXC_BASE + 0x288)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data12_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: CSI0_DAT12. NOTE: Pad CSI0_DAT12 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA12.
 * - ALT1 = 001 - Select signal EIM_DATA08.
 * - ALT3 = 011 - Select signal UART4_TX_DATA. - Configure register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO30.
 * - ALT7 = 111 - Select signal ARM_TRACE09.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA08.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE__ALT3 (0x3) //!< Select signal UART4_TX_DATA. - Configure register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO30.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE09.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT12.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT12.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data13
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data13_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data13_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_ADDR      (REGS_IOMUXC_BASE + 0x28c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data13_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: CSI0_DAT13. NOTE: Pad CSI0_DAT13 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA13.
 * - ALT1 = 001 - Select signal EIM_DATA09.
 * - ALT3 = 011 - Select signal UART4_RX_DATA. - Configure register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT3.
 * - ALT5 = 101 - Select signal GPIO5_IO31.
 * - ALT7 = 111 - Select signal ARM_TRACE10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA09.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE__ALT3 (0x3) //!< Select signal UART4_RX_DATA. - Configure register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO5_IO31.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE10.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT13.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT13.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data14
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data14_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data14_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_ADDR      (REGS_IOMUXC_BASE + 0x290)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data14_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: CSI0_DAT14. NOTE: Pad CSI0_DAT14 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA14.
 * - ALT1 = 001 - Select signal EIM_DATA10.
 * - ALT3 = 011 - Select signal UART5_TX_DATA. - Configure register IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT3.
 * - ALT5 = 101 - Select signal GPIO6_IO00.
 * - ALT7 = 111 - Select signal ARM_TRACE11.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA14.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA10.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE__ALT3 (0x3) //!< Select signal UART5_TX_DATA. - Configure register IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE11.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT14.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data15
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data15_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data15_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_ADDR      (REGS_IOMUXC_BASE + 0x294)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data15_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: CSI0_DAT15. NOTE: Pad CSI0_DAT15 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA15.
 * - ALT1 = 001 - Select signal EIM_DATA11.
 * - ALT3 = 011 - Select signal UART5_RX_DATA. - Configure register IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT3.
 * - ALT5 = 101 - Select signal GPIO6_IO01.
 * - ALT7 = 111 - Select signal ARM_TRACE12.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA11.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE__ALT3 (0x3) //!< Select signal UART5_RX_DATA. - Configure register IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE12.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT15.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT15.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data16
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data16_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_ADDR      (REGS_IOMUXC_BASE + 0x298)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data16_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: CSI0_DAT16. NOTE: Pad CSI0_DAT16 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA16.
 * - ALT1 = 001 - Select signal EIM_DATA12.
 * - ALT3 = 011 - Select signal UART4_RTS_B. - Configure register IOMUXC_UART4_UART_RTS_B_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO6_IO02.
 * - ALT7 = 111 - Select signal ARM_TRACE13.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA12.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE__ALT3 (0x3) //!< Select signal UART4_RTS_B. - Configure register IOMUXC_UART4_UART_RTS_B_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE13.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT16.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT16.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data17
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data17_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_ADDR      (REGS_IOMUXC_BASE + 0x29c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data17_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: CSI0_DAT17. NOTE: Pad CSI0_DAT17 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA17.
 * - ALT1 = 001 - Select signal EIM_DATA13.
 * - ALT3 = 011 - Select signal UART4_CTS_B. - Configure register IOMUXC_UART4_UART_RTS_B_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO6_IO03.
 * - ALT7 = 111 - Select signal ARM_TRACE14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA17.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA13.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE__ALT3 (0x3) //!< Select signal UART4_CTS_B. - Configure register IOMUXC_UART4_UART_RTS_B_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE14.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT17.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data18
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data18_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_ADDR      (REGS_IOMUXC_BASE + 0x2a0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data18_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: CSI0_DAT18. NOTE: Pad CSI0_DAT18 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA18.
 * - ALT1 = 001 - Select signal EIM_DATA14.
 * - ALT3 = 011 - Select signal UART5_RTS_B. - Configure register IOMUXC_UART5_UART_RTS_B_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO6_IO04.
 * - ALT7 = 111 - Select signal ARM_TRACE15.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA18.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA14.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE__ALT3 (0x3) //!< Select signal UART5_RTS_B. - Configure register IOMUXC_UART5_UART_RTS_B_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE__ALT7 (0x7) //!< Select signal ARM_TRACE15.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT18.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT18.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_csi0_data19
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_csi0_data19_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_csi0_data19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_ADDR      (REGS_IOMUXC_BASE + 0x2a4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19           (*(volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data19_t *) HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR(HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: CSI0_DAT19. NOTE: Pad CSI0_DAT19 is involved in
 * Daisy Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal IPU1_CSI0_DATA19.
 * - ALT1 = 001 - Select signal EIM_DATA15.
 * - ALT3 = 011 - Select signal UART5_CTS_B. - Configure register IOMUXC_UART5_UART_RTS_B_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO6_IO05.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE__ALT0 (0x0) //!< Select signal IPU1_CSI0_DATA19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE__ALT1 (0x1) //!< Select signal EIM_DATA15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE__ALT3 (0x3) //!< Select signal UART5_CTS_B. - Configure register IOMUXC_UART5_UART_RTS_B_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO05.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad CSI0_DAT19.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION(BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION__ENABLED (0x1) //!< Force input path of pad CSI0_DAT19.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_data7
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_data7_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_data7_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_ADDR      (REGS_IOMUXC_BASE + 0x2a8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data7_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD3_DAT7. NOTE: Pad SD3_DAT7 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_DATA7.
 * - ALT1 = 001 - Select signal UART1_TX_DATA. - Configure register IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT1.
 * - ALT5 = 101 - Select signal GPIO6_IO17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_DATA7.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE__ALT1 (0x1) //!< Select signal UART1_TX_DATA. - Configure register IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO17.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_DAT7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION__ENABLED (0x1) //!< Force input path of pad SD3_DAT7.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_data6
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_data6_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_data6_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_ADDR      (REGS_IOMUXC_BASE + 0x2ac)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data6_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD3_DAT6. NOTE: Pad SD3_DAT6 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_DATA6.
 * - ALT1 = 001 - Select signal UART1_RX_DATA. - Configure register IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT1.
 * - ALT5 = 101 - Select signal GPIO6_IO18.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_DATA6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE__ALT1 (0x1) //!< Select signal UART1_RX_DATA. - Configure register IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO18.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_DAT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION__ENABLED (0x1) //!< Force input path of pad SD3_DAT6.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_data5
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_data5_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_data5_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_ADDR      (REGS_IOMUXC_BASE + 0x2b0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data5_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD3_DAT5. NOTE: Pad SD3_DAT5 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_DATA5.
 * - ALT1 = 001 - Select signal UART2_TX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT1.
 * - ALT5 = 101 - Select signal GPIO7_IO00.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_DATA5.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE__ALT1 (0x1) //!< Select signal UART2_TX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO00.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_DAT5.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION__ENABLED (0x1) //!< Force input path of pad SD3_DAT5.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_data4
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_data4_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_data4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_ADDR      (REGS_IOMUXC_BASE + 0x2b4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data4_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD3_DAT4. NOTE: Pad SD3_DAT4 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_DATA4.
 * - ALT1 = 001 - Select signal UART2_RX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT1.
 * - ALT5 = 101 - Select signal GPIO7_IO01.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_DATA4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE__ALT1 (0x1) //!< Select signal UART2_RX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO01.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_DAT4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION__ENABLED (0x1) //!< Force input path of pad SD3_DAT4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_cmd
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_cmd_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_cmd_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_CMD register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_ADDR      (REGS_IOMUXC_BASE + 0x2b8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_cmd_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_CMD bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_CMD, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: SD3_CMD. NOTE: Pad SD3_CMD is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_CMD.
 * - ALT1 = 001 - Select signal UART2_CTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal FLEXCAN1_TX.
 * - ALT5 = 101 - Select signal GPIO7_IO02.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_CMD.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE__ALT1 (0x1) //!< Select signal UART2_CTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE__ALT2 (0x2) //!< Select signal FLEXCAN1_TX.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO02.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_CMD, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_CMD.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION__ENABLED (0x1) //!< Force input path of pad SD3_CMD.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_clk_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_CLK register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_ADDR      (REGS_IOMUXC_BASE + 0x2bc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_clk_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_CLK bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_CLK, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: SD3_CLK. NOTE: Pad SD3_CLK is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_CLK.
 * - ALT1 = 001 - Select signal UART2_RTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal FLEXCAN1_RX. - Configure register IOMUXC_FLEXCAN1_RX_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO7_IO03.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_CLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE__ALT1 (0x1) //!< Select signal UART2_RTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE__ALT2 (0x2) //!< Select signal FLEXCAN1_RX. - Configure register IOMUXC_FLEXCAN1_RX_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO03.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_CLK, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_CLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION__ENABLED (0x1) //!< Force input path of pad SD3_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_data0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x2c0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: SD3_DAT0. NOTE: Pad SD3_DAT0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_DATA0.
 * - ALT1 = 001 - Select signal UART1_CTS_B. - Configure register IOMUXC_UART1_UART_RTS_B_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal FLEXCAN2_TX.
 * - ALT5 = 101 - Select signal GPIO7_IO04.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_DATA0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE__ALT1 (0x1) //!< Select signal UART1_CTS_B. - Configure register IOMUXC_UART1_UART_RTS_B_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE__ALT2 (0x2) //!< Select signal FLEXCAN2_TX.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO04.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_DAT0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION__ENABLED (0x1) //!< Force input path of pad SD3_DAT0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_data1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x2c4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: SD3_DAT1. NOTE: Pad SD3_DAT1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_DATA1.
 * - ALT1 = 001 - Select signal UART1_RTS_B. - Configure register IOMUXC_UART1_UART_RTS_B_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal FLEXCAN2_RX. - Configure register IOMUXC_FLEXCAN2_RX_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO7_IO05.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_DATA1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE__ALT1 (0x1) //!< Select signal UART1_RTS_B. - Configure register IOMUXC_UART1_UART_RTS_B_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE__ALT2 (0x2) //!< Select signal FLEXCAN2_RX. - Configure register IOMUXC_FLEXCAN2_RX_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO05.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_DAT1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION__ENABLED (0x1) //!< Force input path of pad SD3_DAT1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_data2
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_data2_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_data2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_ADDR      (REGS_IOMUXC_BASE + 0x2c8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data2_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 2 iomux modes to be used for pad: SD3_DAT2.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_DATA2.
 * - ALT5 = 101 - Select signal GPIO7_IO06.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_DATA2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO06.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_DAT2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION__ENABLED (0x1) //!< Force input path of pad SD3_DAT2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_data3
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_data3_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_data3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_ADDR      (REGS_IOMUXC_BASE + 0x2cc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data3_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD3_DAT3. NOTE: Pad SD3_DAT3 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_DATA3.
 * - ALT1 = 001 - Select signal UART3_CTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT1.
 * - ALT5 = 101 - Select signal GPIO7_IO07.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_DATA3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE__ALT1 (0x1) //!< Select signal UART3_CTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO07.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_DAT3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION__ENABLED (0x1) //!< Force input path of pad SD3_DAT3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd3_reset
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd3_reset_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd3_reset_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD3_RESET register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_ADDR      (REGS_IOMUXC_BASE + 0x2d0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd3_reset_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD3_RESET bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_RESET, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD3_RST. NOTE: Pad SD3_RST is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD3_RESET.
 * - ALT1 = 001 - Select signal UART3_RTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT1.
 * - ALT5 = 101 - Select signal GPIO7_IO08.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE__ALT0 (0x0) //!< Select signal SD3_RESET.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE__ALT1 (0x1) //!< Select signal UART3_RTS_B. - Configure register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO08.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD3_RESET, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD3_RST.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION__ENABLED (0x1) //!< Force input path of pad SD3_RST.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_cle
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_cle_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_cle_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_CLE register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_ADDR      (REGS_IOMUXC_BASE + 0x2d4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_cle_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_CLE bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_CLE.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_CLE.
 * - ALT1 = 001 - Select signal IPU2_SISG4.
 * - ALT5 = 101 - Select signal GPIO6_IO07.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_CLE.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_SISG4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO07.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_CLE.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION__ENABLED (0x1) //!< Force input path of pad NANDF_CLE.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_ale
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_ale_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_ale_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_ALE register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_ADDR      (REGS_IOMUXC_BASE + 0x2d8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_ale_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_ALE bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_ALE.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_ALE.
 * - ALT1 = 001 - Select signal SD4_RESET.
 * - ALT5 = 101 - Select signal GPIO6_IO08.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_ALE.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_RESET.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO08.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_ALE.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION__ENABLED (0x1) //!< Force input path of pad NANDF_ALE.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_wp_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_wp_b_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_wp_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_ADDR      (REGS_IOMUXC_BASE + 0x2dc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_wp_b_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_WP_B.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_WP_B.
 * - ALT1 = 001 - Select signal IPU2_SISG5.
 * - ALT5 = 101 - Select signal GPIO6_IO09.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_WP_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_SISG5.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO09.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_WP_B.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION__ENABLED (0x1) //!< Force input path of pad NANDF_WP_B.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_ready
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_ready_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_ready_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_READY register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_ADDR      (REGS_IOMUXC_BASE + 0x2e0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_ready_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_READY bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_READY, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_RB0.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_READY.
 * - ALT1 = 001 - Select signal IPU2_DI0_PIN01.
 * - ALT5 = 101 - Select signal GPIO6_IO10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_READY.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE__ALT1 (0x1) //!< Select signal IPU2_DI0_PIN01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO10.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_READY, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_RB0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION__ENABLED (0x1) //!< Force input path of pad NANDF_RB0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_cs0_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_cs0_b_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_cs0_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_ADDR      (REGS_IOMUXC_BASE + 0x2e4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_cs0_b_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 2 iomux modes to be used for pad: NANDF_CS0.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_CE0_B.
 * - ALT5 = 101 - Select signal GPIO6_IO11.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_CE0_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO11.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_CS0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION__ENABLED (0x1) //!< Force input path of pad NANDF_CS0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_cs1_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_cs1_b_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_cs1_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_ADDR      (REGS_IOMUXC_BASE + 0x2e8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_cs1_b_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: NANDF_CS1.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_CE1_B.
 * - ALT1 = 001 - Select signal SD4_VSELECT.
 * - ALT2 = 010 - Select signal SD3_VSELECT.
 * - ALT5 = 101 - Select signal GPIO6_IO14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_CE1_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_VSELECT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE__ALT2 (0x2) //!< Select signal SD3_VSELECT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO14.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_CS1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION__ENABLED (0x1) //!< Force input path of pad NANDF_CS1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_cs2_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_cs2_b_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_cs2_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_ADDR      (REGS_IOMUXC_BASE + 0x2ec)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_cs2_b_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: NANDF_CS2. NOTE: Pad NANDF_CS2 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_CE2_B.
 * - ALT1 = 001 - Select signal IPU1_SISG0.
 * - ALT2 = 010 - Select signal ESAI_TX0. - Configure register IOMUXC_ESAI_SDO0_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal EIM_CRE.
 * - ALT4 = 100 - Select signal CCM_CLKO2.
 * - ALT5 = 101 - Select signal GPIO6_IO15.
 * - ALT6 = 110 - Select signal IPU2_SISG0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_CE2_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_SISG0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_TX0. - Configure register IOMUXC_ESAI_SDO0_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE__ALT3 (0x3) //!< Select signal EIM_CRE.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE__ALT4 (0x4) //!< Select signal CCM_CLKO2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO15.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE__ALT6 (0x6) //!< Select signal IPU2_SISG0.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_CS2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION__ENABLED (0x1) //!< Force input path of pad NANDF_CS2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_cs3_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_cs3_b_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_cs3_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_ADDR      (REGS_IOMUXC_BASE + 0x2f0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_cs3_b_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 6 iomux modes to be used for pad: NANDF_CS3. NOTE: Pad NANDF_CS3 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_CE3_B.
 * - ALT1 = 001 - Select signal IPU1_SISG1.
 * - ALT2 = 010 - Select signal ESAI_TX1. - Configure register IOMUXC_ESAI_SDO1_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal EIM_ADDR26.
 * - ALT5 = 101 - Select signal GPIO6_IO16.
 * - ALT6 = 110 - Select signal IPU2_SISG1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_CE3_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE__ALT1 (0x1) //!< Select signal IPU1_SISG1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE__ALT2 (0x2) //!< Select signal ESAI_TX1. - Configure register IOMUXC_ESAI_SDO1_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE__ALT3 (0x3) //!< Select signal EIM_ADDR26.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO6_IO16.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE__ALT6 (0x6) //!< Select signal IPU2_SISG1.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_CS3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION__ENABLED (0x1) //!< Force input path of pad NANDF_CS3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_cmd
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_cmd_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_cmd_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_CMD register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_ADDR      (REGS_IOMUXC_BASE + 0x2f4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_cmd_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_CMD bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_CMD, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: SD4_CMD. NOTE: Pad SD4_CMD is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD4_CMD.
 * - ALT1 = 001 - Select signal NAND_RE_B.
 * - ALT2 = 010 - Select signal UART3_TX_DATA. - Configure register IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO7_IO09.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE__ALT0 (0x0) //!< Select signal SD4_CMD.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE__ALT1 (0x1) //!< Select signal NAND_RE_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE__ALT2 (0x2) //!< Select signal UART3_TX_DATA. - Configure register IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO09.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_CMD, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_CMD.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION__ENABLED (0x1) //!< Force input path of pad SD4_CMD.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_clk_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_CLK register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_ADDR      (REGS_IOMUXC_BASE + 0x2f8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_clk_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_CLK bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_CLK, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: SD4_CLK. NOTE: Pad SD4_CLK is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD4_CLK.
 * - ALT1 = 001 - Select signal NAND_WE_B.
 * - ALT2 = 010 - Select signal UART3_RX_DATA. - Configure register IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO7_IO10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE__ALT0 (0x0) //!< Select signal SD4_CLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE__ALT1 (0x1) //!< Select signal NAND_WE_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE__ALT2 (0x2) //!< Select signal UART3_RX_DATA. - Configure register IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO7_IO10.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_CLK, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_CLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION__ENABLED (0x1) //!< Force input path of pad SD4_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_data00
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_data00_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_data00_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_ADDR      (REGS_IOMUXC_BASE + 0x2fc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_data00_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_D0.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_DATA00.
 * - ALT1 = 001 - Select signal SD1_DATA4.
 * - ALT5 = 101 - Select signal GPIO2_IO00.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_DATA00.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE__ALT1 (0x1) //!< Select signal SD1_DATA4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO00.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_D0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION__ENABLED (0x1) //!< Force input path of pad NANDF_D0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_data01
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_data01_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_data01_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_ADDR      (REGS_IOMUXC_BASE + 0x300)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_data01_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_D1.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_DATA01.
 * - ALT1 = 001 - Select signal SD1_DATA5.
 * - ALT5 = 101 - Select signal GPIO2_IO01.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_DATA01.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE__ALT1 (0x1) //!< Select signal SD1_DATA5.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO01.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_D1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION__ENABLED (0x1) //!< Force input path of pad NANDF_D1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_data02
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_data02_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_data02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_ADDR      (REGS_IOMUXC_BASE + 0x304)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_data02_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_D2.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_DATA02.
 * - ALT1 = 001 - Select signal SD1_DATA6.
 * - ALT5 = 101 - Select signal GPIO2_IO02.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_DATA02.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE__ALT1 (0x1) //!< Select signal SD1_DATA6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO02.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_D2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION__ENABLED (0x1) //!< Force input path of pad NANDF_D2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_data03
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_data03_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_data03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_ADDR      (REGS_IOMUXC_BASE + 0x308)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_data03_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_D3.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_DATA03.
 * - ALT1 = 001 - Select signal SD1_DATA7.
 * - ALT5 = 101 - Select signal GPIO2_IO03.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_DATA03.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE__ALT1 (0x1) //!< Select signal SD1_DATA7.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO03.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_D3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION__ENABLED (0x1) //!< Force input path of pad NANDF_D3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_data04
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_data04_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_data04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_ADDR      (REGS_IOMUXC_BASE + 0x30c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_data04_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_D4.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_DATA04.
 * - ALT1 = 001 - Select signal SD2_DATA4.
 * - ALT5 = 101 - Select signal GPIO2_IO04.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_DATA04.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE__ALT1 (0x1) //!< Select signal SD2_DATA4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO04.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_D4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION__ENABLED (0x1) //!< Force input path of pad NANDF_D4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_data05
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_data05_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_data05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_ADDR      (REGS_IOMUXC_BASE + 0x310)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_data05_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_D5.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_DATA05.
 * - ALT1 = 001 - Select signal SD2_DATA5.
 * - ALT5 = 101 - Select signal GPIO2_IO05.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_DATA05.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE__ALT1 (0x1) //!< Select signal SD2_DATA5.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO05.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_D5.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION__ENABLED (0x1) //!< Force input path of pad NANDF_D5.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_data06
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_data06_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_data06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_ADDR      (REGS_IOMUXC_BASE + 0x314)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_data06_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_D6.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_DATA06.
 * - ALT1 = 001 - Select signal SD2_DATA6.
 * - ALT5 = 101 - Select signal GPIO2_IO06.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_DATA06.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE__ALT1 (0x1) //!< Select signal SD2_DATA6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO06.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_D6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION__ENABLED (0x1) //!< Force input path of pad NANDF_D6.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_nand_data07
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_nand_data07_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_nand_data07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_ADDR      (REGS_IOMUXC_BASE + 0x318)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07           (*(volatile hw_iomuxc_sw_mux_ctl_pad_nand_data07_t *) HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR(HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: NANDF_D7.
 *
 * Values:
 * - ALT0 = 000 - Select signal NAND_DATA07.
 * - ALT1 = 001 - Select signal SD2_DATA7.
 * - ALT5 = 101 - Select signal GPIO2_IO07.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE__ALT0 (0x0) //!< Select signal NAND_DATA07.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE__ALT1 (0x1) //!< Select signal SD2_DATA7.
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO07.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad NANDF_D7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION(BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION__ENABLED (0x1) //!< Force input path of pad NANDF_D7.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_data0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x31c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD4_DAT0.
 *
 * Values:
 * - ALT1 = 001 - Select signal SD4_DATA0.
 * - ALT2 = 010 - Select signal NAND_DQS.
 * - ALT5 = 101 - Select signal GPIO2_IO08.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_DATA0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE__ALT2 (0x2) //!< Select signal NAND_DQS.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO08.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_DAT0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION__ENABLED (0x1) //!< Force input path of pad SD4_DAT0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_data1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x320)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD4_DAT1.
 *
 * Values:
 * - ALT1 = 001 - Select signal SD4_DATA1.
 * - ALT2 = 010 - Select signal PWM3_OUT.
 * - ALT5 = 101 - Select signal GPIO2_IO09.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_DATA1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE__ALT2 (0x2) //!< Select signal PWM3_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO09.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_DAT1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION__ENABLED (0x1) //!< Force input path of pad SD4_DAT1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_data2
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_data2_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_data2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_ADDR      (REGS_IOMUXC_BASE + 0x324)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data2_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD4_DAT2.
 *
 * Values:
 * - ALT1 = 001 - Select signal SD4_DATA2.
 * - ALT2 = 010 - Select signal PWM4_OUT.
 * - ALT5 = 101 - Select signal GPIO2_IO10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_DATA2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE__ALT2 (0x2) //!< Select signal PWM4_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO10.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_DAT2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION__ENABLED (0x1) //!< Force input path of pad SD4_DAT2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_data3
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_data3_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_data3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_ADDR      (REGS_IOMUXC_BASE + 0x328)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data3_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 2 iomux modes to be used for pad: SD4_DAT3.
 *
 * Values:
 * - ALT1 = 001 - Select signal SD4_DATA3.
 * - ALT5 = 101 - Select signal GPIO2_IO11.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_DATA3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO11.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_DAT3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION__ENABLED (0x1) //!< Force input path of pad SD4_DAT3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_data4
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_data4_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_data4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_ADDR      (REGS_IOMUXC_BASE + 0x32c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data4_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD4_DAT4. NOTE: Pad SD4_DAT4 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal SD4_DATA4.
 * - ALT2 = 010 - Select signal UART2_RX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO12.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_DATA4.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE__ALT2 (0x2) //!< Select signal UART2_RX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO12.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_DAT4.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION__ENABLED (0x1) //!< Force input path of pad SD4_DAT4.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_data5
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_data5_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_data5_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_ADDR      (REGS_IOMUXC_BASE + 0x330)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data5_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD4_DAT5. NOTE: Pad SD4_DAT5 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal SD4_DATA5.
 * - ALT2 = 010 - Select signal UART2_RTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO13.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_DATA5.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE__ALT2 (0x2) //!< Select signal UART2_RTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO13.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_DAT5.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION__ENABLED (0x1) //!< Force input path of pad SD4_DAT5.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_data6
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_data6_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_data6_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_ADDR      (REGS_IOMUXC_BASE + 0x334)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data6_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD4_DAT6. NOTE: Pad SD4_DAT6 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal SD4_DATA6.
 * - ALT2 = 010 - Select signal UART2_CTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO14.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_DATA6.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE__ALT2 (0x2) //!< Select signal UART2_CTS_B. - Configure register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO14.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_DAT6.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION__ENABLED (0x1) //!< Force input path of pad SD4_DAT6.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd4_data7
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd4_data7_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd4_data7_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_ADDR      (REGS_IOMUXC_BASE + 0x338)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data7_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 3 iomux modes to be used for pad: SD4_DAT7. NOTE: Pad SD4_DAT7 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT1 = 001 - Select signal SD4_DATA7.
 * - ALT2 = 010 - Select signal UART2_TX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode
 *     ALT2.
 * - ALT5 = 101 - Select signal GPIO2_IO15.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE__ALT1 (0x1) //!< Select signal SD4_DATA7.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE__ALT2 (0x2) //!< Select signal UART2_TX_DATA. - Configure register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO2_IO15.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD4_DAT7.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION__ENABLED (0x1) //!< Force input path of pad SD4_DAT7.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd1_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd1_data1_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd1_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x33c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd1_data1_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: SD1_DAT1. NOTE: Pad SD1_DAT1 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD1_DATA1.
 * - ALT1 = 001 - Select signal ECSPI5_SS0. - Configure register IOMUXC_ECSPI5_SS0_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal PWM3_OUT.
 * - ALT3 = 011 - Select signal GPT_CAPTURE2.
 * - ALT5 = 101 - Select signal GPIO1_IO17.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE__ALT0 (0x0) //!< Select signal SD1_DATA1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_SS0. - Configure register IOMUXC_ECSPI5_SS0_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE__ALT2 (0x2) //!< Select signal PWM3_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE__ALT3 (0x3) //!< Select signal GPT_CAPTURE2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO17.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD1_DAT1.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION__ENABLED (0x1) //!< Force input path of pad SD1_DAT1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd1_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd1_data0_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd1_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x340)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd1_data0_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: SD1_DAT0. NOTE: Pad SD1_DAT0 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD1_DATA0.
 * - ALT1 = 001 - Select signal ECSPI5_MISO. - Configure register IOMUXC_ECSPI5_MISO_SELECT_INPUT for mode ALT1.
 * - ALT3 = 011 - Select signal GPT_CAPTURE1.
 * - ALT5 = 101 - Select signal GPIO1_IO16.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE__ALT0 (0x0) //!< Select signal SD1_DATA0.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_MISO. - Configure register IOMUXC_ECSPI5_MISO_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE__ALT3 (0x3) //!< Select signal GPT_CAPTURE1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO16.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD1_DAT0.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION__ENABLED (0x1) //!< Force input path of pad SD1_DAT0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd1_data3
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd1_data3_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd1_data3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_ADDR      (REGS_IOMUXC_BASE + 0x344)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd1_data3_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: SD1_DAT3.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD1_DATA3.
 * - ALT1 = 001 - Select signal ECSPI5_SS2.
 * - ALT2 = 010 - Select signal GPT_COMPARE3.
 * - ALT3 = 011 - Select signal PWM1_OUT.
 * - ALT4 = 100 - Select signal WDOG2_B.
 * - ALT5 = 101 - Select signal GPIO1_IO21.
 * - ALT6 = 110 - Select signal WDOG2_RESET_B_DEB.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE__ALT0 (0x0) //!< Select signal SD1_DATA3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_SS2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE__ALT2 (0x2) //!< Select signal GPT_COMPARE3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE__ALT3 (0x3) //!< Select signal PWM1_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE__ALT4 (0x4) //!< Select signal WDOG2_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO21.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE__ALT6 (0x6) //!< Select signal WDOG2_RESET_B_DEB.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD1_DAT3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION__ENABLED (0x1) //!< Force input path of pad SD1_DAT3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd1_cmd
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd1_cmd_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd1_cmd_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD1_CMD register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_ADDR      (REGS_IOMUXC_BASE + 0x348)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd1_cmd_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD1_CMD bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_CMD, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: SD1_CMD. NOTE: Pad SD1_CMD is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD1_CMD.
 * - ALT1 = 001 - Select signal ECSPI5_MOSI. - Configure register IOMUXC_ECSPI5_MOSI_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal PWM4_OUT.
 * - ALT3 = 011 - Select signal GPT_COMPARE1.
 * - ALT5 = 101 - Select signal GPIO1_IO18.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE__ALT0 (0x0) //!< Select signal SD1_CMD.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_MOSI. - Configure register IOMUXC_ECSPI5_MOSI_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE__ALT2 (0x2) //!< Select signal PWM4_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE__ALT3 (0x3) //!< Select signal GPT_COMPARE1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO18.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_CMD, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD1_CMD.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION__ENABLED (0x1) //!< Force input path of pad SD1_CMD.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd1_data2
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd1_data2_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd1_data2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_ADDR      (REGS_IOMUXC_BASE + 0x34c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd1_data2_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 7 iomux modes to be used for pad: SD1_DAT2. NOTE: Pad SD1_DAT2 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD1_DATA2.
 * - ALT1 = 001 - Select signal ECSPI5_SS1. - Configure register IOMUXC_ECSPI5_SS1_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal GPT_COMPARE2.
 * - ALT3 = 011 - Select signal PWM2_OUT.
 * - ALT4 = 100 - Select signal WDOG1_B.
 * - ALT5 = 101 - Select signal GPIO1_IO19.
 * - ALT6 = 110 - Select signal WDOG1_RESET_B_DEB.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE__ALT0 (0x0) //!< Select signal SD1_DATA2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_SS1. - Configure register IOMUXC_ECSPI5_SS1_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE__ALT2 (0x2) //!< Select signal GPT_COMPARE2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE__ALT3 (0x3) //!< Select signal PWM2_OUT.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE__ALT4 (0x4) //!< Select signal WDOG1_B.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO19.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE__ALT6 (0x6) //!< Select signal WDOG1_RESET_B_DEB.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD1_DAT2.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION__ENABLED (0x1) //!< Force input path of pad SD1_DAT2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd1_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd1_clk_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd1_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD1_CLK register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_ADDR      (REGS_IOMUXC_BASE + 0x350)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd1_clk_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD1_CLK bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_CLK, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 4 iomux modes to be used for pad: SD1_CLK. NOTE: Pad SD1_CLK is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD1_CLK.
 * - ALT1 = 001 - Select signal ECSPI5_SCLK. - Configure register IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT for mode
 *     ALT1.
 * - ALT3 = 011 - Select signal GPT_CLKIN.
 * - ALT5 = 101 - Select signal GPIO1_IO20.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE__ALT0 (0x0) //!< Select signal SD1_CLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_SCLK. - Configure register IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE__ALT3 (0x3) //!< Select signal GPT_CLKIN.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO20.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD1_CLK, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD1_CLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION__ENABLED (0x1) //!< Force input path of pad SD1_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd2_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd2_clk_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd2_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD2_CLK register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_ADDR      (REGS_IOMUXC_BASE + 0x354)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd2_clk_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD2_CLK bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_CLK, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: SD2_CLK. NOTE: Pad SD2_CLK is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD2_CLK.
 * - ALT1 = 001 - Select signal ECSPI5_SCLK. - Configure register IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT for mode
 *     ALT1.
 * - ALT2 = 010 - Select signal KEY_COL5. - Configure register IOMUXC_KEY_COL5_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal AUD4_RXFS. - Configure register IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO1_IO10.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE__ALT0 (0x0) //!< Select signal SD2_CLK.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_SCLK. - Configure register IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE__ALT2 (0x2) //!< Select signal KEY_COL5. - Configure register IOMUXC_KEY_COL5_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_RXFS. - Configure register IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO10.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_CLK, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD2_CLK.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION__ENABLED (0x1) //!< Force input path of pad SD2_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd2_cmd
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd2_cmd_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd2_cmd_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD2_CMD register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_ADDR      (REGS_IOMUXC_BASE + 0x358)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd2_cmd_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD2_CMD bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_CMD, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: SD2_CMD. NOTE: Pad SD2_CMD is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD2_CMD.
 * - ALT1 = 001 - Select signal ECSPI5_MOSI. - Configure register IOMUXC_ECSPI5_MOSI_SELECT_INPUT for mode ALT1.
 * - ALT2 = 010 - Select signal KEY_ROW5. - Configure register IOMUXC_KEY_ROW5_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal AUD4_RXC. - Configure register IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO1_IO11.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE__ALT0 (0x0) //!< Select signal SD2_CMD.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_MOSI. - Configure register IOMUXC_ECSPI5_MOSI_SELECT_INPUT for mode ALT1.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE__ALT2 (0x2) //!< Select signal KEY_ROW5. - Configure register IOMUXC_KEY_ROW5_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_RXC. - Configure register IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO11.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_CMD, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD2_CMD.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION__ENABLED (0x1) //!< Force input path of pad SD2_CMD.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 - Pad Mux Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 - Pad Mux Register (RW)
 *
 * Reset value: 0x00000005
 */
typedef union _hw_iomuxc_sw_mux_ctl_pad_sd2_data3
{
    reg32_t U;
    struct _hw_iomuxc_sw_mux_ctl_pad_sd2_data3_bitfields
    {
        unsigned MUX_MODE : 3; //!< [2:0] MUX Mode Select Field.
        unsigned RESERVED0 : 1; //!< [3] Reserved
        unsigned SION : 1; //!< [4] Software Input On Field.
        unsigned RESERVED1 : 27; //!< [31:5] Reserved
    } B;
} hw_iomuxc_sw_mux_ctl_pad_sd2_data3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 register
 */
//@{
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_ADDR      (REGS_IOMUXC_BASE + 0x35c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3           (*(volatile hw_iomuxc_sw_mux_ctl_pad_sd2_data3_t *) HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_ADDR)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_RD()      (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3.U)
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_WR(v)     (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3.U = (v))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SET(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_RD() |  (v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_CLR(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_RD() & ~(v)))
#define HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_TOG(v)    (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_WR(HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 bitfields
 */

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3, field MUX_MODE[2:0] (RW)
 *
 * Select 1 of 5 iomux modes to be used for pad: SD2_DAT3. NOTE: Pad SD2_DAT3 is involved in Daisy
 * Chain.
 *
 * Values:
 * - ALT0 = 000 - Select signal SD2_DATA3.
 * - ALT1 = 001 - Select signal ECSPI5_SS3.
 * - ALT2 = 010 - Select signal KEY_COL6. - Configure register IOMUXC_KEY_COL6_SELECT_INPUT for mode ALT2.
 * - ALT3 = 011 - Select signal AUD4_TXC. - Configure register IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT for mode ALT3.
 * - ALT5 = 101 - Select signal GPIO1_IO12.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE      (0)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE      (0x00000007)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MUX_MODE field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE__ALT0 (0x0) //!< Select signal SD2_DATA3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE__ALT1 (0x1) //!< Select signal ECSPI5_SS3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE__ALT2 (0x2) //!< Select signal KEY_COL6. - Configure register IOMUXC_KEY_COL6_SELECT_INPUT for mode ALT2.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE__ALT3 (0x3) //!< Select signal AUD4_TXC. - Configure register IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT for mode ALT3.
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE__ALT5 (0x5) //!< Select signal GPIO1_IO12.
//@}

/*! @name Register IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3, field SION[4] (RW)
 *
 * Force the selected mux mode input path no matter of MUX_MODE functionality.
 *
 * Values:
 * - DISABLED = 0 - Input Path is determined by functionality of the selected mux mode (regular).
 * - ENABLED = 1 - Force input path of pad SD2_DAT3.
 */
//@{
#define BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION      (4)      //!< Bit position for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION.
#define BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION      (0x00000010)  //!< Bit mask for IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION.

//! @brief Get value of IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION from a register value.
#define BG_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION) >> BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION)

//! @brief Format value for bitfield IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION) & BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SION field to a new value.
#define BW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION(v)   (HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION) | BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_V(v) BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION(BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION__##v)

#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION__DISABLED (0x0) //!< Input Path is determined by functionality of the selected mux mode (regular).
#define BV_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION__ENABLED (0x1) //!< Force input path of pad SD2_DAT3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd2_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd2_data1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd2_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x360)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd2_data1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD2_DAT1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD2_DAT1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD2_DAT1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD2_DAT1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD2_DAT1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD2_DAT1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd2_data2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd2_data2_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd2_data2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ADDR      (REGS_IOMUXC_BASE + 0x364)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd2_data2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD2_DAT2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD2_DAT2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD2_DAT2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD2_DAT2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD2_DAT2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD2_DAT2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd2_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd2_data0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd2_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x368)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd2_data0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD2_DAT0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD2_DAT0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD2_DAT0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD2_DAT0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD2_DAT0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD2_DAT0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC - Pad Control Register (RW)
 *
 * Reset value: 0x00013030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_txc
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_txc_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_txc_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ADDR      (REGS_IOMUXC_BASE + 0x36c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_txc_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_TXC.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC, field ODT[10:8] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_ODT__DISABLED (0x0) //!< Disabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_TXC.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_TXC.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_TXC.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_TXC.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_td0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_td0_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_td0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ADDR      (REGS_IOMUXC_BASE + 0x370)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_td0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_TD0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0, field ODT[10:8] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_ODT__DISABLED (0x0) //!< Disabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_TD0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_TD0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_TD0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_TD0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_td1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_td1_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_td1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ADDR      (REGS_IOMUXC_BASE + 0x374)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_td1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_TD1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1, field ODT[10:8] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_ODT__DISABLED (0x0) //!< Disabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_TD1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_TD1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_TD1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_TD1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_td2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_td2_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_td2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ADDR      (REGS_IOMUXC_BASE + 0x378)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_td2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_TD2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2, field ODT[10:8] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_ODT__DISABLED (0x0) //!< Disabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_TD2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_TD2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_TD2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_TD2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_td3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_td3_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_td3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ADDR      (REGS_IOMUXC_BASE + 0x37c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_td3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_TD3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3, field ODT[10:8] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_ODT__DISABLED (0x0) //!< Disabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_TD3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_TD3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_TD3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_TD3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL - Pad Control Register (RW)
 *
 * Reset value: 0x00013030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_rx_ctl
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_rx_ctl_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_rx_ctl_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ADDR      (REGS_IOMUXC_BASE + 0x380)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rx_ctl_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_RX_CTL.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL, field ODT[10:8] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_ODT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_RX_CTL.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_RX_CTL.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_RX_CTL.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_RX_CTL.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_rd0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_rd0_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_rd0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ADDR      (REGS_IOMUXC_BASE + 0x384)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rd0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_RD0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0, field ODT[10:8] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_ODT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_RD0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_RD0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_RD0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_RD0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL - Pad Control Register (RW)
 *
 * Reset value: 0x00013030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_tx_ctl
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_tx_ctl_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_tx_ctl_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ADDR      (REGS_IOMUXC_BASE + 0x388)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_tx_ctl_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_TX_CTL.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL, field ODT[10:8] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_ODT__DISABLED (0x0) //!< Disabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_TX_CTL.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_TX_CTL.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_TX_CTL.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_TX_CTL.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_rd1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_rd1_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_rd1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ADDR      (REGS_IOMUXC_BASE + 0x38c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rd1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_RD1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1, field ODT[10:8] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_ODT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_RD1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_RD1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_RD1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_RD1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_rd2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_rd2_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_rd2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ADDR      (REGS_IOMUXC_BASE + 0x390)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rd2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_RD2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2, field ODT[10:8] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_ODT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_RD2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_RD2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_RD2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_RD2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_rd3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_rd3_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_rd3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ADDR      (REGS_IOMUXC_BASE + 0x394)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rd3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_RD3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3, field ODT[10:8] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_ODT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_RD3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_RD3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_RD3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_RD3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC - Pad Control Register (RW)
 *
 * Reset value: 0x00013030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_rgmii_rxc
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_rgmii_rxc_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED3 : 1; //!< [17] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED4 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_rgmii_rxc_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ADDR      (REGS_IOMUXC_BASE + 0x398)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC           (*(volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rxc_t *) HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: RGMII_RXC.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC, field ODT[10:8] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_ODT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC, field PKE[12] (RW)
 *
 * Select one of next values for pad: RGMII_RXC.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC, field PUE[13] (RW)
 *
 * Select one of next values for pad: RGMII_RXC.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: RGMII_RXC.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC, field HYS[16] (RW)
 *
 * Select one of next values for pad: RGMII_RXC.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC, field DDR_SEL_RGMII[19:18] (RO)
 *
 * This property can be configured using Group Control Register:
 * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII Note: The value of this field does not reflect the value of
 * the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DDR_SEL_RGMII)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr25
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr25_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr25_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ADDR      (REGS_IOMUXC_BASE + 0x39c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr25_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A25.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A25.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A25.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A25.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A25.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A25.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_eb2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_eb2_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_eb2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ADDR      (REGS_IOMUXC_BASE + 0x3a0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_eb2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB2, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_EB2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB2, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_EB2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB2, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB2, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_EB2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB2, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_EB2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB2, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_EB2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB2, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_EB2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data16
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data16_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ADDR      (REGS_IOMUXC_BASE + 0x3a4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data16_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D16.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D16.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D16.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D16.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D16.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D16.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data17
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data17_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ADDR      (REGS_IOMUXC_BASE + 0x3a8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data17_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D17.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D17.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D17.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D17.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D17.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D17.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data18
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data18_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ADDR      (REGS_IOMUXC_BASE + 0x3ac)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data18_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D18.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D18.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D18.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D18.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D18.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D18.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data19
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data19_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ADDR      (REGS_IOMUXC_BASE + 0x3b0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data19_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D19.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D19.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D19.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D19.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D19.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D19.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data20
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data20_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data20_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ADDR      (REGS_IOMUXC_BASE + 0x3b4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data20_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D20.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D20.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D20.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D20.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D20.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D20.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data21
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data21_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data21_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ADDR      (REGS_IOMUXC_BASE + 0x3b8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data21_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D21.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D21.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D21.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D21.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D21.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D21.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data22
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data22_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data22_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ADDR      (REGS_IOMUXC_BASE + 0x3bc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data22_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D22.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D22.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D22.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D22.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D22.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D22.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data23
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data23_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data23_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ADDR      (REGS_IOMUXC_BASE + 0x3c0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data23_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D23.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D23.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D23.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D23.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D23.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D23.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_eb3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_eb3_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_eb3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ADDR      (REGS_IOMUXC_BASE + 0x3c4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_eb3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB3, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_EB3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB3, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_EB3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB3, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB3, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_EB3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB3, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_EB3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB3, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_EB3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB3, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_EB3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data24
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data24_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data24_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ADDR      (REGS_IOMUXC_BASE + 0x3c8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data24_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D24.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D24.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D24.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D24.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D24.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D24.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data25
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data25_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data25_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ADDR      (REGS_IOMUXC_BASE + 0x3cc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data25_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D25.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D25.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D25.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D25.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D25.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D25.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data26
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data26_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data26_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ADDR      (REGS_IOMUXC_BASE + 0x3d0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data26_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D26.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D26.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D26.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D26.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D26.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D26.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data27
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data27_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data27_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ADDR      (REGS_IOMUXC_BASE + 0x3d4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data27_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D27.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D27.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D27.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D27.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D27.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D27.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data28
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data28_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data28_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ADDR      (REGS_IOMUXC_BASE + 0x3d8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data28_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D28.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D28.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D28.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D28.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D28.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D28.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data29
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data29_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data29_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ADDR      (REGS_IOMUXC_BASE + 0x3dc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data29_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D29.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D29.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D29.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D29.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D29.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D29.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data30
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data30_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data30_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ADDR      (REGS_IOMUXC_BASE + 0x3e0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data30_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D30.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D30.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D30.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D30.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D30.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D30.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_data31
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_data31_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_data31_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ADDR      (REGS_IOMUXC_BASE + 0x3e4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_data31_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_D31.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_D31.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_D31.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_D31.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_D31.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_D31.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr24
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr24_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr24_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ADDR      (REGS_IOMUXC_BASE + 0x3e8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr24_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A24.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A24.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A24.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A24.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A24.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A24.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr23
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr23_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr23_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ADDR      (REGS_IOMUXC_BASE + 0x3ec)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr23_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A23.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A23.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A23.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A23.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A23.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A23.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr22
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr22_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr22_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ADDR      (REGS_IOMUXC_BASE + 0x3f0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr22_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A22.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A22.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A22.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A22.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A22.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A22.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr21
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr21_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr21_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ADDR      (REGS_IOMUXC_BASE + 0x3f4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr21_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A21.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A21.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A21.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A21.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A21.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A21.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr20
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr20_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr20_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ADDR      (REGS_IOMUXC_BASE + 0x3f8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr20_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A20.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A20.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A20.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A20.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A20.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A20.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr19
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr19_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ADDR      (REGS_IOMUXC_BASE + 0x3fc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr19_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A19.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A19.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A19.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A19.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A19.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A19.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr18
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr18_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ADDR      (REGS_IOMUXC_BASE + 0x400)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr18_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A18.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A18.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A18.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A18.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A18.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A18.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr17
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr17_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ADDR      (REGS_IOMUXC_BASE + 0x404)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr17_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A17.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A17.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A17.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A17.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A17.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A17.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_addr16
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_addr16_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_addr16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ADDR      (REGS_IOMUXC_BASE + 0x408)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr16_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_A16.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_A16.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_A16.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_A16.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_A16.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_A16.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_cs0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_cs0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_cs0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ADDR      (REGS_IOMUXC_BASE + 0x40c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_cs0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_CS0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS0, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_CS0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS0, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_CS0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS0, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_CS0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_CS0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS0, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_CS0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_cs1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_cs1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_cs1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ADDR      (REGS_IOMUXC_BASE + 0x410)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_cs1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_CS1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_CS1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS1, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_CS1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS1, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_CS1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_CS1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_CS1, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_CS1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_oe
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_oe_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_oe_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_OE register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ADDR      (REGS_IOMUXC_BASE + 0x414)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_oe_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_OE bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_OE, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_OE, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_OE.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_OE, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_OE.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_OE, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_OE, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_OE.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_OE, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_OE.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_OE, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_OE.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_OE, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_OE.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_rw
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_rw_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_rw_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_RW register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ADDR      (REGS_IOMUXC_BASE + 0x418)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_rw_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_RW bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_RW, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_RW, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_RW.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_RW, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_RW.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_RW, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_RW, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_RW.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_RW, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_RW.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_RW, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_RW.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_RW, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_RW.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_lba
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_lba_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_lba_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_LBA register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ADDR      (REGS_IOMUXC_BASE + 0x41c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_lba_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_LBA bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_LBA, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_LBA, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_LBA.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_LBA, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_LBA.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_LBA, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_LBA, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_LBA.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_LBA, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_LBA.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_LBA, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_LBA.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_LBA, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_LBA.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_eb0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_eb0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_eb0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ADDR      (REGS_IOMUXC_BASE + 0x420)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_eb0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_EB0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB0, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_EB0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB0, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_EB0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB0, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_EB0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_EB0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB0, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_EB0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_eb1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_eb1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_eb1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ADDR      (REGS_IOMUXC_BASE + 0x424)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_eb1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_EB1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_EB1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB1, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_EB1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB1, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_EB1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_EB1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_EB1, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_EB1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad00
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad00_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad00_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ADDR      (REGS_IOMUXC_BASE + 0x428)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad00_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad01
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad01_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad01_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ADDR      (REGS_IOMUXC_BASE + 0x42c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad01_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad02
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad02_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ADDR      (REGS_IOMUXC_BASE + 0x430)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad02_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad03
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad03_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ADDR      (REGS_IOMUXC_BASE + 0x434)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad03_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad04
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad04_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ADDR      (REGS_IOMUXC_BASE + 0x438)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad04_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad05
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad05_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ADDR      (REGS_IOMUXC_BASE + 0x43c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad05_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA5.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA5.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA5.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA5.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA5.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA5.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad06
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad06_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ADDR      (REGS_IOMUXC_BASE + 0x440)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad06_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA6.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA6.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA6.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA6.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA6.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA6.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad07
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad07_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ADDR      (REGS_IOMUXC_BASE + 0x444)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad07_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA7.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA7.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA7.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA7.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA7.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA7.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad08
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad08_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad08_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ADDR      (REGS_IOMUXC_BASE + 0x448)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad08_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA8.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA8.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA8.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA8.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA8.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA8.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad09
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad09_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad09_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ADDR      (REGS_IOMUXC_BASE + 0x44c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad09_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA9.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA9.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA9.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA9.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA9.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA9.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad10
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad10_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad10_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ADDR      (REGS_IOMUXC_BASE + 0x450)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad10_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA10.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA10.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA10.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA10.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA10.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA10.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad11
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad11_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad11_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ADDR      (REGS_IOMUXC_BASE + 0x454)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad11_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA11.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA11.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA11.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA11.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA11.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA11.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad12
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad12_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad12_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ADDR      (REGS_IOMUXC_BASE + 0x458)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad12_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA12.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA12.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA12.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA12.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA12.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA12.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad13
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad13_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad13_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ADDR      (REGS_IOMUXC_BASE + 0x45c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad13_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA13.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA13.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA13.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA13.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA13.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA13.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad14
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad14_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad14_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ADDR      (REGS_IOMUXC_BASE + 0x460)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad14_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA14.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA14.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA14.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA14.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA14.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA14.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_ad15
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_ad15_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_ad15_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ADDR      (REGS_IOMUXC_BASE + 0x464)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad15_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_DA15.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_DA15.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_DA15.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_DA15.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_DA15.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_DA15.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT - Pad Control Register (RW)
 *
 * Reset value: 0x0000b060
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_wait
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_wait_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_wait_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ADDR      (REGS_IOMUXC_BASE + 0x468)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_wait_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_WAIT.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_WAIT.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_WAIT.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_WAIT.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_WAIT.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_WAIT.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK - Pad Control Register (RW)
 *
 * Reset value: 0x0000b0b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_eim_bclk
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_eim_bclk_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_eim_bclk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ADDR      (REGS_IOMUXC_BASE + 0x46c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK           (*(volatile hw_iomuxc_sw_pad_ctl_pad_eim_bclk_t *) HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: EIM_BCLK.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: EIM_BCLK.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, field PKE[12] (RW)
 *
 * Select one of next values for pad: EIM_BCLK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, field PUE[13] (RW)
 *
 * Select one of next values for pad: EIM_BCLK.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: EIM_BCLK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, field HYS[16] (RW)
 *
 * Select one of next values for pad: EIM_BCLK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_di0_disp_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_di0_disp_clk_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_di0_disp_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ADDR      (REGS_IOMUXC_BASE + 0x470)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK           (*(volatile hw_iomuxc_sw_pad_ctl_pad_di0_disp_clk_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DI0_DISP_CLK.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DI0_DISP_CLK.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, field PKE[12] (RW)
 *
 * Select one of next values for pad: DI0_DISP_CLK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, field PUE[13] (RW)
 *
 * Select one of next values for pad: DI0_DISP_CLK.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DI0_DISP_CLK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, field HYS[16] (RW)
 *
 * Select one of next values for pad: DI0_DISP_CLK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_di0_pin15
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_di0_pin15_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_di0_pin15_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ADDR      (REGS_IOMUXC_BASE + 0x474)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15           (*(volatile hw_iomuxc_sw_pad_ctl_pad_di0_pin15_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DI0_PIN15.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DI0_PIN15.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15, field PKE[12] (RW)
 *
 * Select one of next values for pad: DI0_PIN15.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15, field PUE[13] (RW)
 *
 * Select one of next values for pad: DI0_PIN15.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DI0_PIN15.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15, field HYS[16] (RW)
 *
 * Select one of next values for pad: DI0_PIN15.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_di0_pin02
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_di0_pin02_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_di0_pin02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ADDR      (REGS_IOMUXC_BASE + 0x478)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02           (*(volatile hw_iomuxc_sw_pad_ctl_pad_di0_pin02_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DI0_PIN2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DI0_PIN2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02, field PKE[12] (RW)
 *
 * Select one of next values for pad: DI0_PIN2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02, field PUE[13] (RW)
 *
 * Select one of next values for pad: DI0_PIN2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DI0_PIN2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02, field HYS[16] (RW)
 *
 * Select one of next values for pad: DI0_PIN2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_di0_pin03
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_di0_pin03_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_di0_pin03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ADDR      (REGS_IOMUXC_BASE + 0x47c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03           (*(volatile hw_iomuxc_sw_pad_ctl_pad_di0_pin03_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DI0_PIN3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DI0_PIN3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03, field PKE[12] (RW)
 *
 * Select one of next values for pad: DI0_PIN3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03, field PUE[13] (RW)
 *
 * Select one of next values for pad: DI0_PIN3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DI0_PIN3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03, field HYS[16] (RW)
 *
 * Select one of next values for pad: DI0_PIN3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_di0_pin04
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_di0_pin04_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_di0_pin04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ADDR      (REGS_IOMUXC_BASE + 0x480)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04           (*(volatile hw_iomuxc_sw_pad_ctl_pad_di0_pin04_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DI0_PIN4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DI0_PIN4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04, field PKE[12] (RW)
 *
 * Select one of next values for pad: DI0_PIN4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04, field PUE[13] (RW)
 *
 * Select one of next values for pad: DI0_PIN4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DI0_PIN4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04, field HYS[16] (RW)
 *
 * Select one of next values for pad: DI0_PIN4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data00
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data00_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data00_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ADDR      (REGS_IOMUXC_BASE + 0x484)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data00_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data01
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data01_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data01_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ADDR      (REGS_IOMUXC_BASE + 0x488)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data01_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data02
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data02_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ADDR      (REGS_IOMUXC_BASE + 0x48c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data02_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data03
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data03_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ADDR      (REGS_IOMUXC_BASE + 0x490)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data03_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data04
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data04_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ADDR      (REGS_IOMUXC_BASE + 0x494)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data04_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data05
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data05_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ADDR      (REGS_IOMUXC_BASE + 0x498)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data05_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT5.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT5.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT5.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT5.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT5.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT5.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data06
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data06_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ADDR      (REGS_IOMUXC_BASE + 0x49c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data06_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT6.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT6.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT6.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT6.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT6.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT6.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data07
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data07_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ADDR      (REGS_IOMUXC_BASE + 0x4a0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data07_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT7.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT7.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT7.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT7.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT7.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT7.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data08
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data08_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data08_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ADDR      (REGS_IOMUXC_BASE + 0x4a4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data08_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT8.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT8.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT8.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT8.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT8.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT8.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data09
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data09_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data09_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ADDR      (REGS_IOMUXC_BASE + 0x4a8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data09_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT9.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT9.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT9.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT9.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT9.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT9.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data10
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data10_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data10_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ADDR      (REGS_IOMUXC_BASE + 0x4ac)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data10_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT10.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT10.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT10.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT10.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT10.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT10.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data11
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data11_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data11_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ADDR      (REGS_IOMUXC_BASE + 0x4b0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data11_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT11.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT11.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT11.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT11.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT11.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT11.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data12
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data12_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data12_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ADDR      (REGS_IOMUXC_BASE + 0x4b4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data12_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT12.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT12.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT12.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT12.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT12.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT12.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data13
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data13_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data13_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ADDR      (REGS_IOMUXC_BASE + 0x4b8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data13_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT13.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT13.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT13.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT13.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT13.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT13.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data14
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data14_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data14_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ADDR      (REGS_IOMUXC_BASE + 0x4bc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data14_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT14.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT14.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT14.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT14.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT14.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT14.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data15
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data15_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data15_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ADDR      (REGS_IOMUXC_BASE + 0x4c0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data15_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT15.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT15.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT15.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT15.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT15.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT15.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data16
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data16_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ADDR      (REGS_IOMUXC_BASE + 0x4c4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data16_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT16.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT16.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT16.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT16.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT16.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT16.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data17
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data17_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ADDR      (REGS_IOMUXC_BASE + 0x4c8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data17_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT17.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT17.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT17.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT17.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT17.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT17.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data18
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data18_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ADDR      (REGS_IOMUXC_BASE + 0x4cc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data18_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT18.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT18.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT18.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT18.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT18.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT18.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data19
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data19_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ADDR      (REGS_IOMUXC_BASE + 0x4d0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data19_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT19.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT19.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT19.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT19.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT19.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT19.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data20
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data20_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data20_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ADDR      (REGS_IOMUXC_BASE + 0x4d4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data20_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT20.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT20.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT20.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT20.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT20.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT20.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data21
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data21_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data21_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ADDR      (REGS_IOMUXC_BASE + 0x4d8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data21_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT21.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT21.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT21.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT21.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT21.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT21.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data22
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data22_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data22_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ADDR      (REGS_IOMUXC_BASE + 0x4dc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data22_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT22.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT22.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT22.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT22.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT22.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT22.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_disp0_data23
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_disp0_data23_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_disp0_data23_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ADDR      (REGS_IOMUXC_BASE + 0x4e0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23           (*(volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data23_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DISP0_DAT23.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: DISP0_DAT23.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23, field PKE[12] (RW)
 *
 * Select one of next values for pad: DISP0_DAT23.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23, field PUE[13] (RW)
 *
 * Select one of next values for pad: DISP0_DAT23.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DISP0_DAT23.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23, field HYS[16] (RW)
 *
 * Select one of next values for pad: DISP0_DAT23.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_mdio
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_mdio_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_mdio_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ADDR      (REGS_IOMUXC_BASE + 0x4e4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_mdio_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_MDIO.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: ENET_MDIO.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_MDIO.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_MDIO.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_MDIO.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_MDIO.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_ref_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_ref_clk_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_ref_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ADDR      (REGS_IOMUXC_BASE + 0x4e8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_ref_clk_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_REF_CLK.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: ENET_REF_CLK.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_REF_CLK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_REF_CLK.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_REF_CLK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_REF_CLK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_rx_er
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_rx_er_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_rx_er_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ADDR      (REGS_IOMUXC_BASE + 0x4ec)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_rx_er_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_RX_ER.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: ENET_RX_ER.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_RX_ER.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_RX_ER.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_RX_ER.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_RX_ER.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_crs_dv
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_crs_dv_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_crs_dv_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ADDR      (REGS_IOMUXC_BASE + 0x4f0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_crs_dv_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_CRS_DV.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100MHZ = 10 - Medium (100 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_CRS_DV.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_CRS_DV.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_CRS_DV.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_CRS_DV.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_rx_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_rx_data1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_rx_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x4f4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_rx_data1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_RXD1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: ENET_RXD1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_RXD1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_RXD1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_RXD1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_RXD1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_rx_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_rx_data0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_rx_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x4f8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_rx_data0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_RXD0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100MHZ = 10 - Medium (100 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_RXD0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_RXD0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_RXD0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_RXD0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_tx_en
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_tx_en_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_tx_en_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ADDR      (REGS_IOMUXC_BASE + 0x4fc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_tx_en_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_TX_EN.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: ENET_TX_EN.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_TX_EN.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_TX_EN.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_TX_EN.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_TX_EN.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_tx_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_tx_data1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_tx_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x500)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_tx_data1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_TXD1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: ENET_TXD1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_TXD1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_TXD1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_TXD1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_TXD1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_tx_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_tx_data0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_tx_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x504)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_tx_data0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_TXD0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: ENET_TXD0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_TXD0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_TXD0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_TXD0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_TXD0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_enet_mdc
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_enet_mdc_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_enet_mdc_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_ENET_MDC register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ADDR      (REGS_IOMUXC_BASE + 0x508)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC           (*(volatile hw_iomuxc_sw_pad_ctl_pad_enet_mdc_t *) HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_ENET_MDC bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDC, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDC, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: ENET_MDC.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDC, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: ENET_MDC.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDC, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDC, field PKE[12] (RW)
 *
 * Select one of next values for pad: ENET_MDC.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDC, field PUE[13] (RW)
 *
 * Select one of next values for pad: ENET_MDC.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDC, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: ENET_MDC.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_ENET_MDC, field HYS[16] (RW)
 *
 * Select one of next values for pad: ENET_MDC.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P - Pad Control Register (RW)
 *
 * Reset value: 0x00002030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs5_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs5_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdqs5_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ADDR      (REGS_IOMUXC_BASE + 0x50c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs5_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS5.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS5.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS5.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS5.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS5.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, field HYS[16] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRHYS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_HYS)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, field DDR_INPUT[17] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_INPUT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_dqm5
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_dqm5_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_dqm5_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ADDR      (REGS_IOMUXC_BASE + 0x510)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm5_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_DQM5.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_DQM5.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_DQM5.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_DQM5.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_dqm4
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_dqm4_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_dqm4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ADDR      (REGS_IOMUXC_BASE + 0x514)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm4_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_DQM4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_DQM4.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_DQM4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_DQM4.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P - Pad Control Register (RW)
 *
 * Reset value: 0x00002030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs4_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs4_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdqs4_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ADDR      (REGS_IOMUXC_BASE + 0x518)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs4_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS4.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, field HYS[16] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRHYS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_HYS)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, field DDR_INPUT[17] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_INPUT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P - Pad Control Register (RW)
 *
 * Reset value: 0x00002030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs3_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs3_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdqs3_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ADDR      (REGS_IOMUXC_BASE + 0x51c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs3_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS3.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, field HYS[16] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRHYS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, field DDR_INPUT[17] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_dqm3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_dqm3_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_dqm3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ADDR      (REGS_IOMUXC_BASE + 0x520)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_DQM3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_DQM3.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_DQM3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_DQM3.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P - Pad Control Register (RW)
 *
 * Reset value: 0x00002030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs2_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs2_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdqs2_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ADDR      (REGS_IOMUXC_BASE + 0x524)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs2_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS2.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, field HYS[16] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRHYS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, field DDR_INPUT[17] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_dqm2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_dqm2_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_dqm2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ADDR      (REGS_IOMUXC_BASE + 0x528)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_DQM2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_DQM2.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_DQM2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_DQM2.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr00
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr00_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr00_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ADDR      (REGS_IOMUXC_BASE + 0x52c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr00_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A0.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A0.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr01
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr01_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr01_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ADDR      (REGS_IOMUXC_BASE + 0x530)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr01_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A1.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A1.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr02
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr02_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ADDR      (REGS_IOMUXC_BASE + 0x534)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr02_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A2.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A2.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr03
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr03_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ADDR      (REGS_IOMUXC_BASE + 0x538)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr03_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A3.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A3.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr04
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr04_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ADDR      (REGS_IOMUXC_BASE + 0x53c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr04_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A4.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A4.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr05
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr05_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ADDR      (REGS_IOMUXC_BASE + 0x540)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr05_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A5.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A5.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A5.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr06
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr06_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ADDR      (REGS_IOMUXC_BASE + 0x544)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr06_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A6.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A6.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A6.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr07
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr07_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ADDR      (REGS_IOMUXC_BASE + 0x548)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr07_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A7.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A7.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A7.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr08
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr08_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr08_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ADDR      (REGS_IOMUXC_BASE + 0x54c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr08_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A8.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A8.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A8.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr09
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr09_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr09_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ADDR      (REGS_IOMUXC_BASE + 0x550)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr09_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A9.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_A9.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A9.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A9.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr10
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr10_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr10_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ADDR      (REGS_IOMUXC_BASE + 0x554)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr10_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A10.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A10.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A10.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr11
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr11_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr11_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ADDR      (REGS_IOMUXC_BASE + 0x558)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr11_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A11.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A11.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A11.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr12
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr12_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr12_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ADDR      (REGS_IOMUXC_BASE + 0x55c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr12_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A12.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A12.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A12.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr13
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr13_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr13_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ADDR      (REGS_IOMUXC_BASE + 0x560)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr13_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A13.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A13.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A13.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr14
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr14_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr14_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ADDR      (REGS_IOMUXC_BASE + 0x564)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr14_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A14.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A14.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A14.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_addr15
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_addr15_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_addr15_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ADDR      (REGS_IOMUXC_BASE + 0x568)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr15_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_A15.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_A15.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_A15.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_cas
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_cas_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_cas_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ADDR      (REGS_IOMUXC_BASE + 0x56c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_cas_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_CAS.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_CAS.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_CAS.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_CAS.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_cs0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_cs0_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_cs0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ADDR      (REGS_IOMUXC_BASE + 0x570)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_cs0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_CS0.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_CS0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_CS0.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_cs1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_cs1_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_cs1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ADDR      (REGS_IOMUXC_BASE + 0x574)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_cs1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_CS1.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_CS1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_CS1.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_ras
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_ras_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_ras_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ADDR      (REGS_IOMUXC_BASE + 0x578)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_ras_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_RAS.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_RAS.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_RAS.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_RAS.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET - Pad Control Register (RW)
 *
 * Reset value: 0x00083030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_reset
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_reset_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_reset_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ADDR      (REGS_IOMUXC_BASE + 0x57c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_reset_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_RESET.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_RESET.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_RESET.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_RESET.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_RESET.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_RESET.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_RESET.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, field DDR_SEL[19:18] (RW)
 *
 * Select one of next values for pad: DRAM_RESET.
 *
 * Values:
 * - RESERVED0 = 00 - Reserved
 * - RESERVED1 = 01 - Reserved
 * - LPDDR2 = 10 - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at
 *     1.2V)
 * - DDR3 = 11 - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at
 *     1.5V)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_SEL field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL__RESERVED0 (0x0) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL__RESERVED1 (0x1) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL__LPDDR2 (0x2) //!< LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL__DDR3 (0x3) //!< DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdba0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdba0_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdba0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ADDR      (REGS_IOMUXC_BASE + 0x580)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdba0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA0.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA0.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdba1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdba1_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdba1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ADDR      (REGS_IOMUXC_BASE + 0x584)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdba1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_ADDDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA1.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA1.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdclk0_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdclk0_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdclk0_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ADDR      (REGS_IOMUXC_BASE + 0x588)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdclk0_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDCLK_0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDCLK_0.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDCLK_0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDCLK_0.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - Pad Control Register (RW)
 *
 * Reset value: 0x0000b000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdba2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdba2_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdba2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ADDR      (REGS_IOMUXC_BASE + 0x58c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdba2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA2.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDBA2.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 - Pad Control Register (RW)
 *
 * Reset value: 0x00003000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdcke0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdcke0_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdcke0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ADDR      (REGS_IOMUXC_BASE + 0x590)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdcke0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE0.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE0.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdclk1_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdclk1_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdclk1_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ADDR      (REGS_IOMUXC_BASE + 0x594)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdclk1_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDCLK_1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDCLK_1.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDCLK_1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDCLK_1.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 - Pad Control Register (RW)
 *
 * Reset value: 0x00003000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdcke1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdcke1_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdcke1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ADDR      (REGS_IOMUXC_BASE + 0x598)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdcke1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE1.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDCKE1.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 - Pad Control Register (RW)
 *
 * Reset value: 0x00003030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_odt0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_odt0_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_odt0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ADDR      (REGS_IOMUXC_BASE + 0x59c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_odt0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT0.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT0.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 - Pad Control Register (RW)
 *
 * Reset value: 0x00003030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_odt1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_odt1_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_odt1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ADDR      (REGS_IOMUXC_BASE + 0x5a0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_odt1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT1.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDODT1.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE - Pad Control Register (RW)
 *
 * Reset value: 0x00008000
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdwe
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdwe_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdwe_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ADDR      (REGS_IOMUXC_BASE + 0x5a4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdwe_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE, field DSE[5:3] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DSE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDWE.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_SDWE.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_SDWE.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P - Pad Control Register (RW)
 *
 * Reset value: 0x00002030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs0_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs0_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdqs0_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ADDR      (REGS_IOMUXC_BASE + 0x5a8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs0_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS0.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, field HYS[16] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRHYS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, field DDR_INPUT[17] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_dqm0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_dqm0_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_dqm0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ADDR      (REGS_IOMUXC_BASE + 0x5ac)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_DQM0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_DQM0.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_DQM0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_DQM0.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P - Pad Control Register (RW)
 *
 * Reset value: 0x00002030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs1_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs1_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdqs1_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ADDR      (REGS_IOMUXC_BASE + 0x5b0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs1_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS1.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, field HYS[16] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRHYS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, field DDR_INPUT[17] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_dqm1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_dqm1_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_dqm1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ADDR      (REGS_IOMUXC_BASE + 0x5b4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_DQM1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_DQM1.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_DQM1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_DQM1.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P - Pad Control Register (RW)
 *
 * Reset value: 0x00002030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs6_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs6_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdqs6_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ADDR      (REGS_IOMUXC_BASE + 0x5b8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs6_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS6.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS6.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS6.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS6.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS6.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, field HYS[16] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRHYS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_HYS)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, field DDR_INPUT[17] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_INPUT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_dqm6
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_dqm6_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_dqm6_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ADDR      (REGS_IOMUXC_BASE + 0x5bc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm6_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_DQM6.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_DQM6.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_DQM6.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_DQM6.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P - Pad Control Register (RW)
 *
 * Reset value: 0x00002030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs7_p
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_sdqs7_p_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_sdqs7_p_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ADDR      (REGS_IOMUXC_BASE + 0x5c0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs7_p_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS7.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS7.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, field PKE[12] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS7.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, field PUE[13] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS7.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: DRAM_SDQS7.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, field HYS[16] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRHYS Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_HYS)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, field DDR_INPUT[17] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_INPUT)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 - Pad Control Register (RW)
 *
 * Reset value: 0x00008030
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_dram_dqm7
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_dram_dqm7_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 2; //!< [7:6] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED2 : 1; //!< [11] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED3 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_dram_dqm7_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ADDR      (REGS_IOMUXC_BASE + 0x5c4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7           (*(volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm7_t *) HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR(HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: DRAM_DQM7.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, field ODT[10:8] (RW)
 *
 * Select one of next values for pad: DRAM_DQM7.
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT__RESERVED1 (0x7) //!< Reserved
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, field PKE[12] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPKE Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PKE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, field PUE[13] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDRPK Note:
 * The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUE)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, field HYS[16] (RW)
 *
 * Select one of next values for pad: DRAM_DQM7.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for pad: DRAM_DQM7.
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, field DDR_SEL[19:18] (RO)
 *
 * This property can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
 * Note: The value of this field does not reflect the value of the Group Control Register.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_SEL)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_col0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_col0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_col0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ADDR      (REGS_IOMUXC_BASE + 0x5c8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_col0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_COL0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL0, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_COL0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL0, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_COL0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL0, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_COL0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_COL0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL0, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_COL0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_row0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_row0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_row0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ADDR      (REGS_IOMUXC_BASE + 0x5cc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_row0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_ROW0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_ROW0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_ROW0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_ROW0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_ROW0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_ROW0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_col1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_col1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_col1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ADDR      (REGS_IOMUXC_BASE + 0x5d0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_col1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_COL1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_COL1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL1, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_COL1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL1, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_COL1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_COL1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL1, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_COL1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_row1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_row1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_row1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ADDR      (REGS_IOMUXC_BASE + 0x5d4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_row1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_ROW1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_ROW1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_ROW1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_ROW1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_ROW1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_ROW1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_col2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_col2_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_col2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ADDR      (REGS_IOMUXC_BASE + 0x5d8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_col2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL2, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_COL2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL2, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_COL2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL2, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL2, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_COL2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL2, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_COL2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL2, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_COL2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL2, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_COL2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_row2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_row2_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_row2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ADDR      (REGS_IOMUXC_BASE + 0x5dc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_row2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_ROW2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_ROW2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_ROW2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_ROW2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_ROW2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_ROW2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_col3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_col3_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_col3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ADDR      (REGS_IOMUXC_BASE + 0x5e0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_col3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL3, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_COL3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL3, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_COL3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL3, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL3, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_COL3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL3, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_COL3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL3, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_COL3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL3, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_COL3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_row3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_row3_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_row3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ADDR      (REGS_IOMUXC_BASE + 0x5e4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_row3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_ROW3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_ROW3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_ROW3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_ROW3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_ROW3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_ROW3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_col4
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_col4_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_col4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ADDR      (REGS_IOMUXC_BASE + 0x5e8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_col4_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL4, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL4, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_COL4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL4, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_COL4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL4, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL4, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_COL4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL4, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_COL4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL4, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_COL4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_COL4, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_COL4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_key_row4
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_key_row4_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_key_row4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ADDR      (REGS_IOMUXC_BASE + 0x5ec)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4           (*(volatile hw_iomuxc_sw_pad_ctl_pad_key_row4_t *) HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: KEY_ROW4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: KEY_ROW4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4, field PKE[12] (RW)
 *
 * Select one of next values for pad: KEY_ROW4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4, field PUE[13] (RW)
 *
 * Select one of next values for pad: KEY_ROW4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: KEY_ROW4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4, field HYS[16] (RW)
 *
 * Select one of next values for pad: KEY_ROW4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio00
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio00_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio00_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO00 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ADDR      (REGS_IOMUXC_BASE + 0x5f0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio00_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO00 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO00, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO00, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO00, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100MHZ = 10 - Medium (100 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO00, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO00, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO00, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO00, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO00, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio01
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio01_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio01_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO01 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ADDR      (REGS_IOMUXC_BASE + 0x5f4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio01_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO01 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO01, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO01, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO01, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO01, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO01, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO01, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO01, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO01, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio09
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio09_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio09_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO09 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ADDR      (REGS_IOMUXC_BASE + 0x5f8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio09_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO09 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO09, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO09, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_9.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO09, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_9.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO09, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO09, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_9.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO09, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_9.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO09, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_9.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO09, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_9.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio03
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio03_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO03 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ADDR      (REGS_IOMUXC_BASE + 0x5fc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio03_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO03 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO03, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO03, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO03, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO03, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO03, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO03, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO03, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO03, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio06
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio06_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO06 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ADDR      (REGS_IOMUXC_BASE + 0x600)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio06_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO06 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO06, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO06, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_6.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO06, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_6.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO06, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO06, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_6.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO06, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_6.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO06, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_6.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO06, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_6.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio02
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio02_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO02 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ADDR      (REGS_IOMUXC_BASE + 0x604)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio02_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO02 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO02, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO02, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO02, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO02, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO02, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO02, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO02, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO02, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio04
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio04_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO04 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ADDR      (REGS_IOMUXC_BASE + 0x608)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio04_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO04 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO04, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO04, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO04, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO04, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO04, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO04, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO04, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO04, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio05
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio05_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO05 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ADDR      (REGS_IOMUXC_BASE + 0x60c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio05_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO05 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO05, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO05, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_5.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO05, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_5.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO05, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO05, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_5.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO05, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_5.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO05, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_5.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO05, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_5.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio07
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio07_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO07 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ADDR      (REGS_IOMUXC_BASE + 0x610)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio07_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO07 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO07, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO07, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_7.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO07, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_7.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO07, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO07, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_7.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO07, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_7.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO07, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_7.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO07, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_7.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio08
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio08_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio08_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO08 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ADDR      (REGS_IOMUXC_BASE + 0x614)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio08_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO08 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO08, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO08, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_8.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO08, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_8.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO08, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO08, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_8.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO08, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_8.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO08, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_8.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO08, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_8.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio16
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio16_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO16 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ADDR      (REGS_IOMUXC_BASE + 0x618)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio16_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO16 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO16, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO16, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_16.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO16, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_16.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO16, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO16, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_16.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO16, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_16.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO16, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_16.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO16, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_16.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO16_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio17
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio17_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO17 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ADDR      (REGS_IOMUXC_BASE + 0x61c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio17_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO17 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO17, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO17, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_17.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO17, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100MHZ = 10 - Medium (100 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO17, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO17, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_17.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO17, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_17.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO17, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_17.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO17, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_17.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio18
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio18_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO18 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ADDR      (REGS_IOMUXC_BASE + 0x620)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio18_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO18 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO18, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO18, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_18.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO18, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_18.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO18, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO18, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_18.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO18, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_18.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO18, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_18.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO18, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_18.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_gpio19
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_gpio19_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_gpio19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_GPIO19 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ADDR      (REGS_IOMUXC_BASE + 0x624)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19           (*(volatile hw_iomuxc_sw_pad_ctl_pad_gpio19_t *) HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_GPIO19 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO19, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO19, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: GPIO_19.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO19, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: GPIO_19.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO19, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO19, field PKE[12] (RW)
 *
 * Select one of next values for pad: GPIO_19.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO19, field PUE[13] (RW)
 *
 * Select one of next values for pad: GPIO_19.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO19, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: GPIO_19.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_GPIO19, field HYS[16] (RW)
 *
 * Select one of next values for pad: GPIO_19.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_pixclk
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_pixclk_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_pixclk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ADDR      (REGS_IOMUXC_BASE + 0x628)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_pixclk_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_PIXCLK.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_PIXCLK.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_PIXCLK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_PIXCLK.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_PIXCLK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_PIXCLK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_hsync
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_hsync_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_hsync_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ADDR      (REGS_IOMUXC_BASE + 0x62c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_hsync_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_MCLK.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_MCLK.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_MCLK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_MCLK.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_MCLK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_MCLK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data_en
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data_en_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data_en_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ADDR      (REGS_IOMUXC_BASE + 0x630)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data_en_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DATA_EN.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DATA_EN.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DATA_EN.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DATA_EN.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DATA_EN.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DATA_EN.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_vsync
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_vsync_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_vsync_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ADDR      (REGS_IOMUXC_BASE + 0x634)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_vsync_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_VSYNC.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_VSYNC.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_VSYNC.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_VSYNC.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_VSYNC.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_VSYNC.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data04
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data04_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ADDR      (REGS_IOMUXC_BASE + 0x638)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data04_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data05
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data05_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ADDR      (REGS_IOMUXC_BASE + 0x63c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data05_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT5.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT5.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT5.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT5.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT5.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT5.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data06
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data06_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ADDR      (REGS_IOMUXC_BASE + 0x640)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data06_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT6.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT6.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT6.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT6.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT6.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT6.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data07
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data07_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ADDR      (REGS_IOMUXC_BASE + 0x644)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data07_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT7.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT7.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT7.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT7.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT7.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT7.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data08
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data08_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data08_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ADDR      (REGS_IOMUXC_BASE + 0x648)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data08_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT8.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT8.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT8.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT8.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT8.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT8.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data09
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data09_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data09_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ADDR      (REGS_IOMUXC_BASE + 0x64c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data09_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT9.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT9.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT9.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT9.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT9.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT9.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data10
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data10_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data10_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ADDR      (REGS_IOMUXC_BASE + 0x650)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data10_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT10.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT10.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT10.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT10.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT10.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT10.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data11
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data11_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data11_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ADDR      (REGS_IOMUXC_BASE + 0x654)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data11_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT11.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT11.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT11.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT11.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT11.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT11.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data12
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data12_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data12_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ADDR      (REGS_IOMUXC_BASE + 0x658)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data12_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT12.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT12.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT12.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT12.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT12.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT12.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data13
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data13_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data13_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ADDR      (REGS_IOMUXC_BASE + 0x65c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data13_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT13.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT13.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT13.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT13.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT13.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT13.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data14
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data14_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data14_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ADDR      (REGS_IOMUXC_BASE + 0x660)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data14_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT14.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT14.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT14.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT14.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT14.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT14.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data15
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data15_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data15_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ADDR      (REGS_IOMUXC_BASE + 0x664)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data15_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT15.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT15.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT15.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT15.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT15.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT15.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data16
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data16_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data16_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ADDR      (REGS_IOMUXC_BASE + 0x668)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data16_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT16.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT16.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT16.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT16.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT16.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT16.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data17
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data17_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data17_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ADDR      (REGS_IOMUXC_BASE + 0x66c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data17_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT17.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT17.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT17.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT17.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT17.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT17.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data18
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data18_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data18_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ADDR      (REGS_IOMUXC_BASE + 0x670)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data18_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT18.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT18.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT18.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT18.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT18.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT18.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_csi0_data19
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_csi0_data19_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_csi0_data19_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ADDR      (REGS_IOMUXC_BASE + 0x674)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19           (*(volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data19_t *) HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR(HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: CSI0_DAT19.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: CSI0_DAT19.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19, field PKE[12] (RW)
 *
 * Select one of next values for pad: CSI0_DAT19.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19, field PUE[13] (RW)
 *
 * Select one of next values for pad: CSI0_DAT19.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: CSI0_DAT19.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19, field HYS[16] (RW)
 *
 * Select one of next values for pad: CSI0_DAT19.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR((HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS - Pad Control Register (RW)
 *
 * Reset value: 0x00007060
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_jtag_tms
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_jtag_tms_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_jtag_tms_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ADDR      (REGS_IOMUXC_BASE + 0x678)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS           (*(volatile hw_iomuxc_sw_pad_ctl_pad_jtag_tms_t *) HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS, field SRE[0] (RO)
 *
 * Slew rate control. Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE__SLOW (0x0) //!< Slow Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS, field DSE[5:3] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 60_OHM = 100 - 60 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE__60_OHM (0x4) //!< 60 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 50MHZ = 01 - Low (50 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED__50MHZ (0x1) //!< Low (50 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS, field ODE[11] (RO)
 *
 * Enables open drain of the pin. Read Only Field The value of this field is fixed and cannot be
 * changed.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE__DISABLED (0x0) //!< Output is CMOS.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS, field PKE[12] (RW)
 *
 * Select one of next values for pad: JTAG_TMS.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS, field PUE[13] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: JTAG_TMS.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS, field HYS[16] (RW)
 *
 * Select one of next values for pad: JTAG_TMS.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD - Pad Control Register (RW)
 *
 * Reset value: 0x0000b060
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_jtag_mod
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_jtag_mod_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_jtag_mod_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ADDR      (REGS_IOMUXC_BASE + 0x67c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD           (*(volatile hw_iomuxc_sw_pad_ctl_pad_jtag_mod_t *) HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD, field SRE[0] (RO)
 *
 * Slew rate control. Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE__SLOW (0x0) //!< Slow Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD, field DSE[5:3] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 60_OHM = 100 - 60 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE__60_OHM (0x4) //!< 60 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 50MHZ = 01 - Low (50 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED__50MHZ (0x1) //!< Low (50 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD, field ODE[11] (RO)
 *
 * Enables open drain of the pin. Read Only Field The value of this field is fixed and cannot be
 * changed.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE__DISABLED (0x0) //!< Output is CMOS.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD, field PKE[12] (RW)
 *
 * Select one of next values for pad: JTAG_MOD.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD, field PUE[13] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: JTAG_MOD.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD, field HYS[16] (RW)
 *
 * Select one of next values for pad: JTAG_MOD.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB - Pad Control Register (RW)
 *
 * Reset value: 0x00007060
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_jtag_trstb
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_jtag_trstb_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_jtag_trstb_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ADDR      (REGS_IOMUXC_BASE + 0x680)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB           (*(volatile hw_iomuxc_sw_pad_ctl_pad_jtag_trstb_t *) HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB, field SRE[0] (RO)
 *
 * Slew rate control. Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SRE__SLOW (0x0) //!< Slow Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB, field DSE[5:3] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 60_OHM = 100 - 60 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_DSE__60_OHM (0x4) //!< 60 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 50MHZ = 01 - Low (50 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_SPEED__50MHZ (0x1) //!< Low (50 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB, field ODE[11] (RO)
 *
 * Enables open drain of the pin. Read Only Field The value of this field is fixed and cannot be
 * changed.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_ODE__DISABLED (0x0) //!< Output is CMOS.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB, field PKE[12] (RW)
 *
 * Select one of next values for pad: JTAG_TRSTB.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB, field PUE[13] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: JTAG_TRSTB.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB, field HYS[16] (RW)
 *
 * Select one of next values for pad: JTAG_TRSTB.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI - Pad Control Register (RW)
 *
 * Reset value: 0x00007060
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_jtag_tdi
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_jtag_tdi_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_jtag_tdi_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ADDR      (REGS_IOMUXC_BASE + 0x684)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI           (*(volatile hw_iomuxc_sw_pad_ctl_pad_jtag_tdi_t *) HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI, field SRE[0] (RO)
 *
 * Slew rate control. Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE__SLOW (0x0) //!< Slow Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI, field DSE[5:3] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 60_OHM = 100 - 60 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE__60_OHM (0x4) //!< 60 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 50MHZ = 01 - Low (50 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED__50MHZ (0x1) //!< Low (50 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI, field ODE[11] (RO)
 *
 * Enables open drain of the pin. Read Only Field The value of this field is fixed and cannot be
 * changed.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE__DISABLED (0x0) //!< Output is CMOS.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI, field PKE[12] (RW)
 *
 * Select one of next values for pad: JTAG_TDI.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI, field PUE[13] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: JTAG_TDI.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI, field HYS[16] (RW)
 *
 * Select one of next values for pad: JTAG_TDI.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK - Pad Control Register (RW)
 *
 * Reset value: 0x00007060
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_jtag_tck
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_jtag_tck_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_jtag_tck_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ADDR      (REGS_IOMUXC_BASE + 0x688)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK           (*(volatile hw_iomuxc_sw_pad_ctl_pad_jtag_tck_t *) HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK, field SRE[0] (RO)
 *
 * Slew rate control. Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE__SLOW (0x0) //!< Slow Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK, field DSE[5:3] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 60_OHM = 100 - 60 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE__60_OHM (0x4) //!< 60 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 50MHZ = 01 - Low (50 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED__50MHZ (0x1) //!< Low (50 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK, field ODE[11] (RO)
 *
 * Enables open drain of the pin. Read Only Field The value of this field is fixed and cannot be
 * changed.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE__DISABLED (0x0) //!< Output is CMOS.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK, field PKE[12] (RW)
 *
 * Select one of next values for pad: JTAG_TCK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK, field PUE[13] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: JTAG_TCK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK, field HYS[16] (RW)
 *
 * Select one of next values for pad: JTAG_TCK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO - Pad Control Register (RW)
 *
 * Reset value: 0x000090b1
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_jtag_tdo
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_jtag_tdo_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_jtag_tdo_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ADDR      (REGS_IOMUXC_BASE + 0x68c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO           (*(volatile hw_iomuxc_sw_pad_ctl_pad_jtag_tdo_t *) HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_WR(HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO, field SRE[0] (RO)
 *
 * Slew rate control. Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO, field DSE[5:3] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 40_OHM = 110 - 40 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE__40_OHM (0x6) //!< 40 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO, field SPEED[7:6] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100MHZ = 10 - Medium (100 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO, field ODE[11] (RO)
 *
 * Enables open drain of the pin. Read Only Field The value of this field is fixed and cannot be
 * changed.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE__DISABLED (0x0) //!< Output is CMOS.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO, field PKE[12] (RW)
 *
 * Select one of next values for pad: JTAG_TDO.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_WR((HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO, field PUE[13] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE__KEEP (0x0) //!< Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO, field PUS[15:14] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO, field HYS[16] (RO)
 *
 * Read Only Field The value of this field is fixed and cannot be changed.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS)

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS__DISABLED (0x0) //!< CMOS input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_data7
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_data7_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_data7_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ADDR      (REGS_IOMUXC_BASE + 0x690)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data7_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_DAT7.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_DAT7.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_DAT7.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_DAT7.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_DAT7.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_DAT7.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_data6
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_data6_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_data6_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ADDR      (REGS_IOMUXC_BASE + 0x694)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data6_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_DAT6.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_DAT6.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_DAT6.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_DAT6.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_DAT6.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_DAT6.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_data5
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_data5_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_data5_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ADDR      (REGS_IOMUXC_BASE + 0x698)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data5_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_DAT5.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_DAT5.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_DAT5.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_DAT5.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_DAT5.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_DAT5.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_data4
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_data4_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_data4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ADDR      (REGS_IOMUXC_BASE + 0x69c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data4_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_DAT4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_DAT4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_DAT4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_DAT4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_DAT4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_DAT4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_cmd
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_cmd_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_cmd_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_CMD register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ADDR      (REGS_IOMUXC_BASE + 0x6a0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_cmd_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_CMD bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CMD, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CMD, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_CMD.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CMD, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_CMD.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CMD, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CMD, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_CMD.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CMD, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_CMD.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CMD, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_CMD.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CMD, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_CMD.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_clk_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_CLK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ADDR      (REGS_IOMUXC_BASE + 0x6a4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_clk_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_CLK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_CLK.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_CLK.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_CLK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_CLK.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_CLK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_CLK, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_CLK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_data0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x6a8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_DAT0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_DAT0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_DAT0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_DAT0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_DAT0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_DAT0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_data1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x6ac)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_DAT1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_DAT1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_DAT1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_DAT1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_DAT1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_DAT1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_data2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_data2_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_data2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ADDR      (REGS_IOMUXC_BASE + 0x6b0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_DAT2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_DAT2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_DAT2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_DAT2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_DAT2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_DAT2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_data3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_data3_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_data3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ADDR      (REGS_IOMUXC_BASE + 0x6b4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_DAT3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_DAT3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_DAT3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_DAT3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_DAT3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_DAT3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd3_reset
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd3_reset_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd3_reset_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD3_RESET register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ADDR      (REGS_IOMUXC_BASE + 0x6b8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd3_reset_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD3_RESET bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_RESET, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_RESET, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD3_RST.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_RESET, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD3_RST.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_RESET, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_RESET, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD3_RST.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_RESET, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD3_RST.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_RESET, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD3_RST.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD3_RESET, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD3_RST.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_cle
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_cle_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_cle_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_CLE register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ADDR      (REGS_IOMUXC_BASE + 0x6bc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_cle_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_CLE bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_CLE.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_CLE.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_CLE.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_CLE.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_CLE.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_CLE.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_ale
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_ale_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_ale_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_ALE register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ADDR      (REGS_IOMUXC_BASE + 0x6c0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_ale_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_ALE bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_ALE, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_ALE, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_ALE.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_ALE, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_ALE.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_ALE, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_ALE, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_ALE.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_ALE, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_ALE.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_ALE, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_ALE.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_ALE, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_ALE.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_wp_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_wp_b_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_wp_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ADDR      (REGS_IOMUXC_BASE + 0x6c4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_wp_b_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_WP_B.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_WP_B.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_WP_B.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_WP_B.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_WP_B.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_WP_B.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_ready
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_ready_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_ready_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_READY register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ADDR      (REGS_IOMUXC_BASE + 0x6c8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_ready_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_READY bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_READY, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_READY, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_RB0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_READY, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_RB0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_READY, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_READY, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_RB0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_READY, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_RB0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_READY, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_RB0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_READY, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_RB0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_cs0_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_cs0_b_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_cs0_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ADDR      (REGS_IOMUXC_BASE + 0x6cc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_cs0_b_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_CS0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_CS0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_CS0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_CS0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_CS0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_CS0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_cs1_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_cs1_b_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_cs1_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ADDR      (REGS_IOMUXC_BASE + 0x6d0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_cs1_b_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_CS1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_CS1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_CS1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_CS1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_CS1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_CS1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_cs2_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_cs2_b_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_cs2_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ADDR      (REGS_IOMUXC_BASE + 0x6d4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_cs2_b_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_CS2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_CS2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_CS2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_CS2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_CS2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_CS2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_cs3_b
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_cs3_b_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_cs3_b_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ADDR      (REGS_IOMUXC_BASE + 0x6d8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_cs3_b_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_CS3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_CS3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_CS3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_CS3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_CS3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_CS3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_cmd
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_cmd_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_cmd_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_CMD register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ADDR      (REGS_IOMUXC_BASE + 0x6dc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_cmd_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_CMD bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CMD, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CMD, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_CMD.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CMD, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_CMD.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CMD, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CMD, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_CMD.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CMD, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_CMD.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CMD, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_CMD.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CMD, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_CMD.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_clk_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_CLK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ADDR      (REGS_IOMUXC_BASE + 0x6e0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_clk_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_CLK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CLK, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CLK, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_CLK.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CLK, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_CLK.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CLK, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CLK, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_CLK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CLK, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_CLK.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CLK, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_CLK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_CLK, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_CLK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_data00
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_data00_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_data00_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ADDR      (REGS_IOMUXC_BASE + 0x6e4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_data00_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_D0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_D0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_D0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_D0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_D0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_D0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_data01
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_data01_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_data01_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ADDR      (REGS_IOMUXC_BASE + 0x6e8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_data01_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_D1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_D1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_D1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_D1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_D1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_D1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_data02
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_data02_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_data02_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ADDR      (REGS_IOMUXC_BASE + 0x6ec)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_data02_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_D2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_D2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_D2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_D2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_D2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_D2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_data03
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_data03_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_data03_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ADDR      (REGS_IOMUXC_BASE + 0x6f0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_data03_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_D3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_D3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_D3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_D3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_D3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_D3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_data04
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_data04_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_data04_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ADDR      (REGS_IOMUXC_BASE + 0x6f4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_data04_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_D4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_D4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_D4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_D4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_D4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_D4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_data05
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_data05_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_data05_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ADDR      (REGS_IOMUXC_BASE + 0x6f8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_data05_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_D5.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_D5.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_D5.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_D5.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_D5.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_D5.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_data06
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_data06_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_data06_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ADDR      (REGS_IOMUXC_BASE + 0x6fc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_data06_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_D6.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_D6.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_D6.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_D6.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_D6.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_D6.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_nand_data07
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_nand_data07_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_nand_data07_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ADDR      (REGS_IOMUXC_BASE + 0x700)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07           (*(volatile hw_iomuxc_sw_pad_ctl_pad_nand_data07_t *) HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR(HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: NANDF_D7.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: NANDF_D7.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07, field PKE[12] (RW)
 *
 * Select one of next values for pad: NANDF_D7.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07, field PUE[13] (RW)
 *
 * Select one of next values for pad: NANDF_D7.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: NANDF_D7.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07, field HYS[16] (RW)
 *
 * Select one of next values for pad: NANDF_D7.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR((HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_data0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x704)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_DAT0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_DAT0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_DAT0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_DAT0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_DAT0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_DAT0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_data1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x708)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_DAT1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_DAT1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_DAT1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_DAT1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_DAT1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_DAT1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_data2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_data2_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_data2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ADDR      (REGS_IOMUXC_BASE + 0x70c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_DAT2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_DAT2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_DAT2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_DAT2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_DAT2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_DAT2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_data3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_data3_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_data3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ADDR      (REGS_IOMUXC_BASE + 0x710)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_DAT3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_DAT3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_DAT3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_DAT3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_DAT3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_DAT3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_data4
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_data4_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_data4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ADDR      (REGS_IOMUXC_BASE + 0x714)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data4_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_DAT4.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_DAT4.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_DAT4.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_DAT4.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_DAT4.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_DAT4.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_data5
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_data5_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_data5_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ADDR      (REGS_IOMUXC_BASE + 0x718)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data5_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_DAT5.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_DAT5.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_DAT5.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_DAT5.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_DAT5.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_DAT5.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_data6
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_data6_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_data6_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ADDR      (REGS_IOMUXC_BASE + 0x71c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data6_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_DAT6.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_DAT6.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_DAT6.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_DAT6.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_DAT6.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_DAT6.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd4_data7
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd4_data7_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd4_data7_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ADDR      (REGS_IOMUXC_BASE + 0x720)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data7_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD4_DAT7.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD4_DAT7.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD4_DAT7.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD4_DAT7.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD4_DAT7.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD4_DAT7.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd1_data1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd1_data1_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd1_data1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ADDR      (REGS_IOMUXC_BASE + 0x724)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd1_data1_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD1_DAT1.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD1_DAT1.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD1_DAT1.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD1_DAT1.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD1_DAT1.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD1_DAT1.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd1_data0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd1_data0_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd1_data0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ADDR      (REGS_IOMUXC_BASE + 0x728)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd1_data0_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD1_DAT0.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD1_DAT0.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD1_DAT0.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD1_DAT0.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD1_DAT0.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD1_DAT0.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd1_data3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd1_data3_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd1_data3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ADDR      (REGS_IOMUXC_BASE + 0x72c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd1_data3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD1_DAT3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD1_DAT3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD1_DAT3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD1_DAT3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD1_DAT3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD1_DAT3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd1_cmd
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd1_cmd_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd1_cmd_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD1_CMD register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ADDR      (REGS_IOMUXC_BASE + 0x730)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd1_cmd_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD1_CMD bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CMD, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CMD, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD1_CMD.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CMD, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD1_CMD.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CMD, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CMD, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD1_CMD.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CMD, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD1_CMD.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CMD, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD1_CMD.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CMD, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD1_CMD.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd1_data2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd1_data2_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd1_data2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ADDR      (REGS_IOMUXC_BASE + 0x734)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd1_data2_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD1_DAT2.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD1_DAT2.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD1_DAT2.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD1_DAT2.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD1_DAT2.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD1_DAT2.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd1_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd1_clk_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd1_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD1_CLK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ADDR      (REGS_IOMUXC_BASE + 0x738)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd1_clk_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD1_CLK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CLK, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CLK, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD1_CLK.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CLK, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD1_CLK.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CLK, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CLK, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD1_CLK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CLK, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD1_CLK.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CLK, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD1_CLK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD1_CLK, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD1_CLK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd2_clk
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd2_clk_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd2_clk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD2_CLK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ADDR      (REGS_IOMUXC_BASE + 0x73c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd2_clk_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD2_CLK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CLK, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CLK, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD2_CLK.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CLK, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD2_CLK.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CLK, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CLK, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD2_CLK.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CLK, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD2_CLK.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CLK, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD2_CLK.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CLK, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD2_CLK.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd2_cmd
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd2_cmd_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd2_cmd_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD2_CMD register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ADDR      (REGS_IOMUXC_BASE + 0x740)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd2_cmd_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD2_CMD bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CMD, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CMD, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD2_CMD.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CMD, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD2_CMD.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CMD, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CMD, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD2_CMD.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CMD, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD2_CMD.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CMD, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD2_CMD.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_CMD, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD2_CMD.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 - Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 - Pad Control Register (RW)
 *
 * Reset value: 0x0001b0b0
 */
typedef union _hw_iomuxc_sw_pad_ctl_pad_sd2_data3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_pad_sd2_data3_bitfields
    {
        unsigned SRE : 1; //!< [0] Slew Rate Field
        unsigned RESERVED0 : 2; //!< [2:1] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned SPEED : 2; //!< [7:6] Speed Field
        unsigned RESERVED1 : 3; //!< [10:8] Reserved
        unsigned ODE : 1; //!< [11] Open Drain Enable Field
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned PUS : 2; //!< [15:14] Pull Up / Down Config. Field
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED2 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_pad_sd2_data3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ADDR      (REGS_IOMUXC_BASE + 0x744)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3           (*(volatile hw_iomuxc_sw_pad_ctl_pad_sd2_data3_t *) HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD()      (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3.U)
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR(HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3, field SRE[0] (RW)
 *
 * Slew rate control.
 *
 * Values:
 * - SLOW = 0 - Slow Slew Rate
 * - FAST = 1 - Fast Slew Rate
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE      (0)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE      (0x00000001)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SRE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE__SLOW (0x0) //!< Slow Slew Rate
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE__FAST (0x1) //!< Fast Slew Rate
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3, field DSE[5:3] (RW)
 *
 * Select one of next values for pad: SD2_DAT3.
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3, field SPEED[7:6] (RW)
 *
 * Select one of next values for pad: SD2_DAT3.
 *
 * Values:
 * - TBD = 00 - TBD
 * - 50MHZ = 01 - Low (50 MHz)
 * - 100MHZ = 10 - Medium (100 MHz)
 * - 200MHZ = 11 - Maximum (200 MHz)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED      (6)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED      (0x000000c0)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPEED field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED__TBD (0x0) //!< TBD
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED__50MHZ (0x1) //!< Low (50 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED__100MHZ (0x2) //!< Medium (100 MHz)
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED__200MHZ (0x3) //!< Maximum (200 MHz)
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3, field ODE[11] (RW)
 *
 * Enables open drain of the pin.
 *
 * Values:
 * - DISABLED = 0 - Output is CMOS.
 * - ENABLED = 1 - Output is Open Drain.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE      (11)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE      (0x00000800)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE__DISABLED (0x0) //!< Output is CMOS.
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE__ENABLED (0x1) //!< Output is Open Drain.
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3, field PKE[12] (RW)
 *
 * Select one of next values for pad: SD2_DAT3.
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3, field PUE[13] (RW)
 *
 * Select one of next values for pad: SD2_DAT3.
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE__PULL (0x1) //!< Pull Enabled
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3, field PUS[15:14] (RW)
 *
 * Select one of next values for pad: SD2_DAT3.
 *
 * Values:
 * - 100K_OHM_PD = 00 - 100K Ohm Pull Down
 * - 47K_OHM_PU = 01 - 47K Ohm Pull Up
 * - 100K_OHM_PU = 10 - 100K Ohm Pull Up
 * - 22K_OHM_PU = 11 - 22K Ohm Pull Up
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS      (14)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS      (0x0000c000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS__100K_OHM_PD (0x0) //!< 100K Ohm Pull Down
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS__47K_OHM_PU (0x1) //!< 47K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS__100K_OHM_PU (0x2) //!< 100K Ohm Pull Up
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS__22K_OHM_PU (0x3) //!< 22K Ohm Pull Up
//@}

/*! @name Register IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3, field HYS[16] (RW)
 *
 * Select one of next values for pad: SD2_DAT3.
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS.
#define BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS) >> BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS) & BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR((HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_RD() & ~BM_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS) | BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS(BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_B7DS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_B7DS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_b7ds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_b7ds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_b7ds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_B7DS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_ADDR      (REGS_IOMUXC_BASE + 0x748)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_B7DS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_b7ds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_B7DS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_B7DS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_B7DS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_B7DS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA56, DRAM_DATA57, DRAM_DATA58,
 * DRAM_DATA59, DRAM_DATA60, DRAM_DATA61, DRAM_DATA62, DRAM_DATA63
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_addds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_addds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_addds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_ADDDS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_ADDR      (REGS_IOMUXC_BASE + 0x74c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_addds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_ADDDS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_ADDDS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_ADDR00, DRAM_ADDR01, DRAM_ADDR02,
 * DRAM_ADDR03, DRAM_ADDR04, DRAM_ADDR05, DRAM_ADDR06, DRAM_ADDR07, DRAM_ADDR08, DRAM_ADDR09,
 * DRAM_ADDR10, DRAM_ADDR11, DRAM_ADDR12, DRAM_ADDR13, DRAM_ADDR14, DRAM_ADDR15, DRAM_SDBA0,
 * DRAM_SDBA1
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_ddrmode_ctl
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_ddrmode_ctl_bitfields
    {
        unsigned RESERVED0 : 17; //!< [16:0] Reserved
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned RESERVED1 : 14; //!< [31:18] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_ddrmode_ctl_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_ADDR      (REGS_IOMUXC_BASE + 0x750)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL           (*(volatile hw_iomuxc_sw_pad_ctl_grp_ddrmode_ctl_t *) HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_SDQS0_P, DRAM_SDQS1_P, DRAM_SDQS2_P,
 * DRAM_SDQS3_P, DRAM_SDQS4_P, DRAM_SDQS5_P, DRAM_SDQS6_P, DRAM_SDQS7_P
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR((HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_term_ctl0
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_term_ctl0_bitfields
    {
        unsigned RESERVED0 : 8; //!< [7:0] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED1 : 21; //!< [31:11] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_term_ctl0_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ADDR      (REGS_IOMUXC_BASE + 0x754)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0           (*(volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl0_t *) HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, field ODT[10:8] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA00, DRAM_DATA01, DRAM_DATA02,
 * DRAM_DATA03, DRAM_DATA04, DRAM_DATA05, DRAM_DATA06, DRAM_DATA07
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT) >> BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_WR((HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT) | BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT(BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0_ODT__RESERVED1 (0x7) //!< Reserved
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE - Pad Group Control Register (RW)
 *
 * Reset value: 0x00001000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_ddrpke
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_ddrpke_bitfields
    {
        unsigned RESERVED0 : 12; //!< [11:0] Reserved
        unsigned PKE : 1; //!< [12] Pull / Keep Enable Field
        unsigned RESERVED1 : 19; //!< [31:13] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_ddrpke_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_DDRPKE register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_ADDR      (REGS_IOMUXC_BASE + 0x758)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE           (*(volatile hw_iomuxc_sw_pad_ctl_grp_ddrpke_t *) HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_DDRPKE bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_DDRPKE, field PKE[12] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_ADDR00, DRAM_ADDR01, DRAM_ADDR02,
 * DRAM_ADDR03, DRAM_ADDR04, DRAM_ADDR05, DRAM_ADDR06, DRAM_ADDR07, DRAM_ADDR08, DRAM_ADDR09,
 * DRAM_ADDR10, DRAM_ADDR11, DRAM_ADDR12, DRAM_ADDR13, DRAM_ADDR14, DRAM_ADDR15, DRAM_CAS, DRAM_CS0,
 * DRAM_CS1, DRAM_DATA00, DRAM_DATA01, DRAM_DATA02, DRAM_DATA03, DRAM_DATA04, DRAM_DATA05,
 * DRAM_DATA06, DRAM_DATA07, DRAM_DATA08, DRAM_DATA09, DRAM_DATA10, DRAM_DATA11, DRAM_DATA12,
 * DRAM_DATA13, DRAM_DATA14, DRAM_DATA15, DRAM_DATA16, DRAM_DATA17, DRAM_DATA18, DRAM_DATA19,
 * DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23, DRAM_DATA24, DRAM_DATA25, DRAM_DATA26,
 * DRAM_DATA27, DRAM_DATA28, DRAM_DATA29, DRAM_DATA30, DRAM_DATA31, DRAM_DATA32, DRAM_DATA33,
 * DRAM_DATA34, DRAM_DATA35, DRAM_DATA36, DRAM_DATA37, DRAM_DATA38, DRAM_DATA39, DRAM_DATA40,
 * DRAM_DATA41, DRAM_DATA42, DRAM_DATA43, DRAM_DATA44, DRAM_DATA45, DRAM_DATA46, DRAM_DATA47,
 * DRAM_DATA48, DRAM_DATA49, DRAM_DATA50, DRAM_DATA51, DRAM_DATA52, DRAM_DATA53, DRAM_DATA54,
 * DRAM_DATA55, DRAM_DATA56, DRAM_DATA57, DRAM_DATA58, DRAM_DATA59, DRAM_DATA60, DRAM_DATA61,
 * DRAM_DATA62, DRAM_DATA63, DRAM_DQM0, DRAM_DQM1, DRAM_DQM2, DRAM_DQM3, DRAM_DQM4, DRAM_DQM5,
 * DRAM_DQM6, DRAM_DQM7, DRAM_RAS, DRAM_SDBA0, DRAM_SDBA1, DRAM_SDCLK0_P, DRAM_SDCLK1_P, DRAM_SDWE
 *
 * Values:
 * - DISABLED = 0 - Pull/Keeper Disabled
 * - ENABLED = 1 - Pull/Keeper Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE      (12)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE      (0x00001000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE) >> BP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PKE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR((HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE) | BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE(BV_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE__DISABLED (0x0) //!< Pull/Keeper Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE__ENABLED (0x1) //!< Pull/Keeper Enabled
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_term_ctl1
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_term_ctl1_bitfields
    {
        unsigned RESERVED0 : 8; //!< [7:0] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED1 : 21; //!< [31:11] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_term_ctl1_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ADDR      (REGS_IOMUXC_BASE + 0x75c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1           (*(volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl1_t *) HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, field ODT[10:8] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA08, DRAM_DATA09, DRAM_DATA10,
 * DRAM_DATA11, DRAM_DATA12, DRAM_DATA13, DRAM_DATA14, DRAM_DATA15
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT) >> BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_WR((HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT) | BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT(BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1_ODT__RESERVED1 (0x7) //!< Reserved
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_term_ctl2
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_term_ctl2_bitfields
    {
        unsigned RESERVED0 : 8; //!< [7:0] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED1 : 21; //!< [31:11] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_term_ctl2_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ADDR      (REGS_IOMUXC_BASE + 0x760)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2           (*(volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl2_t *) HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, field ODT[10:8] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA16, DRAM_DATA17, DRAM_DATA18,
 * DRAM_DATA19, DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT) >> BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_WR((HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT) | BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT(BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2_ODT__RESERVED1 (0x7) //!< Reserved
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_term_ctl3
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_term_ctl3_bitfields
    {
        unsigned RESERVED0 : 8; //!< [7:0] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED1 : 21; //!< [31:11] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_term_ctl3_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ADDR      (REGS_IOMUXC_BASE + 0x764)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3           (*(volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl3_t *) HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, field ODT[10:8] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA24, DRAM_DATA25, DRAM_DATA26,
 * DRAM_DATA27, DRAM_DATA28, DRAM_DATA29, DRAM_DATA30, DRAM_DATA31
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT) >> BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_WR((HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT) | BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT(BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3_ODT__RESERVED1 (0x7) //!< Reserved
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK - Pad Group Control Register (RW)
 *
 * Reset value: 0x00002000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_ddrpk
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_ddrpk_bitfields
    {
        unsigned RESERVED0 : 13; //!< [12:0] Reserved
        unsigned PUE : 1; //!< [13] Pull / Keep Select Field
        unsigned RESERVED1 : 18; //!< [31:14] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_ddrpk_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_DDRPK register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_ADDR      (REGS_IOMUXC_BASE + 0x768)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK           (*(volatile hw_iomuxc_sw_pad_ctl_grp_ddrpk_t *) HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_DDRPK bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_DDRPK, field PUE[13] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_ADDR00, DRAM_ADDR01, DRAM_ADDR02,
 * DRAM_ADDR03, DRAM_ADDR04, DRAM_ADDR05, DRAM_ADDR06, DRAM_ADDR07, DRAM_ADDR08, DRAM_ADDR09,
 * DRAM_ADDR10, DRAM_ADDR11, DRAM_ADDR12, DRAM_ADDR13, DRAM_ADDR14, DRAM_ADDR15, DRAM_CAS, DRAM_CS0,
 * DRAM_CS1, DRAM_DATA00, DRAM_DATA01, DRAM_DATA02, DRAM_DATA03, DRAM_DATA04, DRAM_DATA05,
 * DRAM_DATA06, DRAM_DATA07, DRAM_DATA08, DRAM_DATA09, DRAM_DATA10, DRAM_DATA11, DRAM_DATA12,
 * DRAM_DATA13, DRAM_DATA14, DRAM_DATA15, DRAM_DATA16, DRAM_DATA17, DRAM_DATA18, DRAM_DATA19,
 * DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23, DRAM_DATA24, DRAM_DATA25, DRAM_DATA26,
 * DRAM_DATA27, DRAM_DATA28, DRAM_DATA29, DRAM_DATA30, DRAM_DATA31, DRAM_DATA32, DRAM_DATA33,
 * DRAM_DATA34, DRAM_DATA35, DRAM_DATA36, DRAM_DATA37, DRAM_DATA38, DRAM_DATA39, DRAM_DATA40,
 * DRAM_DATA41, DRAM_DATA42, DRAM_DATA43, DRAM_DATA44, DRAM_DATA45, DRAM_DATA46, DRAM_DATA47,
 * DRAM_DATA48, DRAM_DATA49, DRAM_DATA50, DRAM_DATA51, DRAM_DATA52, DRAM_DATA53, DRAM_DATA54,
 * DRAM_DATA55, DRAM_DATA56, DRAM_DATA57, DRAM_DATA58, DRAM_DATA59, DRAM_DATA60, DRAM_DATA61,
 * DRAM_DATA62, DRAM_DATA63, DRAM_DQM0, DRAM_DQM1, DRAM_DQM2, DRAM_DQM3, DRAM_DQM4, DRAM_DQM5,
 * DRAM_DQM6, DRAM_DQM7, DRAM_RAS, DRAM_SDBA0, DRAM_SDBA1, DRAM_SDCLK0_P, DRAM_SDCLK1_P, DRAM_SDWE
 *
 * Values:
 * - KEEP = 0 - Keeper Enabled
 * - PULL = 1 - Pull Enabled
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE      (13)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE      (0x00002000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE) >> BP_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR((HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE) | BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE(BV_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE__KEEP (0x0) //!< Keeper Enabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE__PULL (0x1) //!< Pull Enabled
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_term_ctl4
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_term_ctl4_bitfields
    {
        unsigned RESERVED0 : 8; //!< [7:0] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED1 : 21; //!< [31:11] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_term_ctl4_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ADDR      (REGS_IOMUXC_BASE + 0x76c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4           (*(volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl4_t *) HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, field ODT[10:8] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA32, DRAM_DATA33, DRAM_DATA34,
 * DRAM_DATA35, DRAM_DATA36, DRAM_DATA37, DRAM_DATA38, DRAM_DATA39
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT) >> BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_WR((HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT) | BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT(BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4_ODT__RESERVED1 (0x7) //!< Reserved
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_ddrhys
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_ddrhys_bitfields
    {
        unsigned RESERVED0 : 16; //!< [15:0] Reserved
        unsigned HYS : 1; //!< [16] Hysteresis Enable Field
        unsigned RESERVED1 : 15; //!< [31:17] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_ddrhys_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_DDRHYS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_ADDR      (REGS_IOMUXC_BASE + 0x770)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_ddrhys_t *) HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_DDRHYS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_DDRHYS, field HYS[16] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA00, DRAM_DATA01, DRAM_DATA02,
 * DRAM_DATA03, DRAM_DATA04, DRAM_DATA05, DRAM_DATA06, DRAM_DATA07, DRAM_DATA08, DRAM_DATA09,
 * DRAM_DATA10, DRAM_DATA11, DRAM_DATA12, DRAM_DATA13, DRAM_DATA14, DRAM_DATA15, DRAM_DATA16,
 * DRAM_DATA17, DRAM_DATA18, DRAM_DATA19, DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23,
 * DRAM_DATA24, DRAM_DATA25, DRAM_DATA26, DRAM_DATA27, DRAM_DATA28, DRAM_DATA29, DRAM_DATA30,
 * DRAM_DATA31, DRAM_DATA32, DRAM_DATA33, DRAM_DATA34, DRAM_DATA35, DRAM_DATA36, DRAM_DATA37,
 * DRAM_DATA38, DRAM_DATA39, DRAM_DATA40, DRAM_DATA41, DRAM_DATA42, DRAM_DATA43, DRAM_DATA44,
 * DRAM_DATA45, DRAM_DATA46, DRAM_DATA47, DRAM_DATA48, DRAM_DATA49, DRAM_DATA50, DRAM_DATA51,
 * DRAM_DATA52, DRAM_DATA53, DRAM_DATA54, DRAM_DATA55, DRAM_DATA56, DRAM_DATA57, DRAM_DATA58,
 * DRAM_DATA59, DRAM_DATA60, DRAM_DATA61, DRAM_DATA62, DRAM_DATA63, DRAM_SDQS0_P, DRAM_SDQS1_P,
 * DRAM_SDQS2_P, DRAM_SDQS3_P, DRAM_SDQS4_P, DRAM_SDQS5_P, DRAM_SDQS6_P, DRAM_SDQS7_P
 *
 * Values:
 * - DISABLED = 0 - CMOS input
 * - ENABLED = 1 - Schmitt trigger input
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS      (16)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS.
#define BM_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS      (0x00010000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS) >> BP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the HYS field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS) | BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS(BV_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS__DISABLED (0x0) //!< CMOS input
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS__ENABLED (0x1) //!< Schmitt trigger input
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_ddrmode
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_ddrmode_bitfields
    {
        unsigned RESERVED0 : 17; //!< [16:0] Reserved
        unsigned DDR_INPUT : 1; //!< [17] DDR / CMOS Input Mode Field
        unsigned RESERVED1 : 14; //!< [31:18] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_ddrmode_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_DDRMODE register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_ADDR      (REGS_IOMUXC_BASE + 0x774)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE           (*(volatile hw_iomuxc_sw_pad_ctl_grp_ddrmode_t *) HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_DDRMODE bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_DDRMODE, field DDR_INPUT[17] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA00, DRAM_DATA01, DRAM_DATA02,
 * DRAM_DATA03, DRAM_DATA04, DRAM_DATA05, DRAM_DATA06, DRAM_DATA07, DRAM_DATA08, DRAM_DATA09,
 * DRAM_DATA10, DRAM_DATA11, DRAM_DATA12, DRAM_DATA13, DRAM_DATA14, DRAM_DATA15, DRAM_DATA16,
 * DRAM_DATA17, DRAM_DATA18, DRAM_DATA19, DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23,
 * DRAM_DATA24, DRAM_DATA25, DRAM_DATA26, DRAM_DATA27, DRAM_DATA28, DRAM_DATA29, DRAM_DATA30,
 * DRAM_DATA31, DRAM_DATA32, DRAM_DATA33, DRAM_DATA34, DRAM_DATA35, DRAM_DATA36, DRAM_DATA37,
 * DRAM_DATA38, DRAM_DATA39, DRAM_DATA40, DRAM_DATA41, DRAM_DATA42, DRAM_DATA43, DRAM_DATA44,
 * DRAM_DATA45, DRAM_DATA46, DRAM_DATA47, DRAM_DATA48, DRAM_DATA49, DRAM_DATA50, DRAM_DATA51,
 * DRAM_DATA52, DRAM_DATA53, DRAM_DATA54, DRAM_DATA55, DRAM_DATA56, DRAM_DATA57, DRAM_DATA58,
 * DRAM_DATA59, DRAM_DATA60, DRAM_DATA61, DRAM_DATA62, DRAM_DATA63
 *
 * Values:
 * - CMOS = 0 - CMOS input mode.
 * - DIFFERENTIAL = 1 - Differential input mode.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT      (17)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT      (0x00020000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT) >> BP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT) & BM_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_INPUT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR((HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT) | BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT(BV_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT__CMOS (0x0) //!< CMOS input mode.
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT__DIFFERENTIAL (0x1) //!< Differential input mode.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_term_ctl5
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_term_ctl5_bitfields
    {
        unsigned RESERVED0 : 8; //!< [7:0] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED1 : 21; //!< [31:11] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_term_ctl5_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ADDR      (REGS_IOMUXC_BASE + 0x778)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5           (*(volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl5_t *) HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, field ODT[10:8] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA40, DRAM_DATA41, DRAM_DATA42,
 * DRAM_DATA43, DRAM_DATA44, DRAM_DATA45, DRAM_DATA46, DRAM_DATA47
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT) >> BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_WR((HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT) | BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT(BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5_ODT__RESERVED1 (0x7) //!< Reserved
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_term_ctl6
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_term_ctl6_bitfields
    {
        unsigned RESERVED0 : 8; //!< [7:0] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED1 : 21; //!< [31:11] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_term_ctl6_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ADDR      (REGS_IOMUXC_BASE + 0x77c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6           (*(volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl6_t *) HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, field ODT[10:8] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA48, DRAM_DATA49, DRAM_DATA50,
 * DRAM_DATA51, DRAM_DATA52, DRAM_DATA53, DRAM_DATA54, DRAM_DATA55
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT) >> BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_WR((HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT) | BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT(BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6_ODT__RESERVED1 (0x7) //!< Reserved
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_term_ctl7
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_term_ctl7_bitfields
    {
        unsigned RESERVED0 : 8; //!< [7:0] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED1 : 21; //!< [31:11] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_term_ctl7_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ADDR      (REGS_IOMUXC_BASE + 0x780)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7           (*(volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl7_t *) HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_WR(HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, field ODT[10:8] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA56, DRAM_DATA57, DRAM_DATA58,
 * DRAM_DATA59, DRAM_DATA60, DRAM_DATA61, DRAM_DATA62, DRAM_DATA63
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT) >> BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT) & BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_WR((HW_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT) | BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT(BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7_ODT__RESERVED1 (0x7) //!< Reserved
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_B0DS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_B0DS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_b0ds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_b0ds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_b0ds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_B0DS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_ADDR      (REGS_IOMUXC_BASE + 0x784)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_B0DS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_b0ds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_B0DS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_B0DS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_B0DS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_B0DS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA00, DRAM_DATA01, DRAM_DATA02,
 * DRAM_DATA03, DRAM_DATA04, DRAM_DATA05, DRAM_DATA06, DRAM_DATA07
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_B1DS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_B1DS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_b1ds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_b1ds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_b1ds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_B1DS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_ADDR      (REGS_IOMUXC_BASE + 0x788)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_B1DS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_b1ds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_B1DS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_B1DS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_B1DS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_B1DS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA08, DRAM_DATA09, DRAM_DATA10,
 * DRAM_DATA11, DRAM_DATA12, DRAM_DATA13, DRAM_DATA14, DRAM_DATA15
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_ctlds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_ctlds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_ctlds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_CTLDS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_ADDR      (REGS_IOMUXC_BASE + 0x78c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_ctlds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_CTLDS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_CTLDS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_CS0, DRAM_CS1, DRAM_SDBA2,
 * DRAM_SDCKE0, DRAM_SDCKE1, DRAM_SDWE
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - Pad Group Control Register (RW)
 *
 * Reset value: 0x00080000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_ddr_type_rgmii
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_ddr_type_rgmii_bitfields
    {
        unsigned RESERVED0 : 18; //!< [17:0] Reserved
        unsigned DDR_SEL_RGMII : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED1 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_ddr_type_rgmii_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_ADDR      (REGS_IOMUXC_BASE + 0x790)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII           (*(volatile hw_iomuxc_sw_pad_ctl_grp_ddr_type_rgmii_t *) HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII, field DDR_SEL_RGMII[19:18] (RW)
 *
 * Select one of next values for group: . Affected pads: RGMII_RD0, RGMII_RD1, RGMII_RD2, RGMII_RD3,
 * RGMII_RXC, RGMII_RX_CTL, RGMII_TD0, RGMII_TD1, RGMII_TD2, RGMII_TD3, RGMII_TXC, RGMII_TX_CTL
 *
 * Values:
 * - RESERVED0 = 00 - Reserved
 * - RESERVED1 = 01 - Reserved
 * - 1P2V_IO = 10 - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals
 *     ranging from 1.0V up to 1.3V.
 * - 1P5V_IO = 11 - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from
 *     1.3V to 2.5V.
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII.
#define BM_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII) >> BP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII) & BM_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_SEL_RGMII field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR((HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII) | BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII(BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII__RESERVED0 (0x0) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII__RESERVED1 (0x1) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII__1P2V_IO (0x2) //!< 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII__1P5V_IO (0x3) //!< 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_B2DS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_B2DS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_b2ds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_b2ds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_b2ds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_B2DS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_ADDR      (REGS_IOMUXC_BASE + 0x794)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_B2DS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_b2ds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_B2DS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_B2DS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_B2DS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_B2DS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA16, DRAM_DATA17, DRAM_DATA18,
 * DRAM_DATA19, DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - Pad Group Control Register (RW)
 *
 * Reset value: 0x00080000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_ddr_type
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_ddr_type_bitfields
    {
        unsigned RESERVED0 : 18; //!< [17:0] Reserved
        unsigned DDR_SEL : 2; //!< [19:18] DDR Select Field
        unsigned RESERVED1 : 12; //!< [31:20] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_ddr_type_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_ADDR      (REGS_IOMUXC_BASE + 0x798)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE           (*(volatile hw_iomuxc_sw_pad_ctl_grp_ddr_type_t *) HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, field DDR_SEL[19:18] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_ADDR00, DRAM_ADDR01, DRAM_ADDR02,
 * DRAM_ADDR03, DRAM_ADDR04, DRAM_ADDR05, DRAM_ADDR06, DRAM_ADDR07, DRAM_ADDR08, DRAM_ADDR09,
 * DRAM_ADDR10, DRAM_ADDR11, DRAM_ADDR12, DRAM_ADDR13, DRAM_ADDR14, DRAM_ADDR15, DRAM_CAS, DRAM_CS0,
 * DRAM_CS1, DRAM_DATA00, DRAM_DATA01, DRAM_DATA02, DRAM_DATA03, DRAM_DATA04, DRAM_DATA05,
 * DRAM_DATA06, DRAM_DATA07, DRAM_DATA08, DRAM_DATA09, DRAM_DATA10, DRAM_DATA11, DRAM_DATA12,
 * DRAM_DATA13, DRAM_DATA14, DRAM_DATA15, DRAM_DATA16, DRAM_DATA17, DRAM_DATA18, DRAM_DATA19,
 * DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23, DRAM_DATA24, DRAM_DATA25, DRAM_DATA26,
 * DRAM_DATA27, DRAM_DATA28, DRAM_DATA29, DRAM_DATA30, DRAM_DATA31, DRAM_DATA32, DRAM_DATA33,
 * DRAM_DATA34, DRAM_DATA35, DRAM_DATA36, DRAM_DATA37, DRAM_DATA38, DRAM_DATA39, DRAM_DATA40,
 * DRAM_DATA41, DRAM_DATA42, DRAM_DATA43, DRAM_DATA44, DRAM_DATA45, DRAM_DATA46, DRAM_DATA47,
 * DRAM_DATA48, DRAM_DATA49, DRAM_DATA50, DRAM_DATA51, DRAM_DATA52, DRAM_DATA53, DRAM_DATA54,
 * DRAM_DATA55, DRAM_DATA56, DRAM_DATA57, DRAM_DATA58, DRAM_DATA59, DRAM_DATA60, DRAM_DATA61,
 * DRAM_DATA62, DRAM_DATA63, DRAM_DQM0, DRAM_DQM1, DRAM_DQM2, DRAM_DQM3, DRAM_DQM4, DRAM_DQM5,
 * DRAM_DQM6, DRAM_DQM7, DRAM_ODT0, DRAM_ODT1, DRAM_RAS, DRAM_SDBA0, DRAM_SDBA1, DRAM_SDBA2,
 * DRAM_SDCKE0, DRAM_SDCKE1, DRAM_SDCLK0_P, DRAM_SDCLK1_P, DRAM_SDQS0_P, DRAM_SDQS1_P, DRAM_SDQS2_P,
 * DRAM_SDQS3_P, DRAM_SDQS4_P, DRAM_SDQS5_P, DRAM_SDQS6_P, DRAM_SDQS7_P, DRAM_SDWE
 *
 * Values:
 * - RESERVED0 = 00 - Reserved
 * - RESERVED1 = 01 - Reserved
 * - LPDDR2 = 10 - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at
 *     1.2V)
 * - DDR3 = 11 - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at
 *     1.5V)
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL      (18)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL.
#define BM_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL      (0x000c0000)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL) >> BP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL) & BM_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDR_SEL field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR((HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL) | BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL(BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL__RESERVED0 (0x0) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL__RESERVED1 (0x1) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL__LPDDR2 (0x2) //!< LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
#define BV_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL__DDR3 (0x3) //!< DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_B3DS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_B3DS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_b3ds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_b3ds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_b3ds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_B3DS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_ADDR      (REGS_IOMUXC_BASE + 0x79c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_B3DS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_b3ds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_B3DS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_B3DS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_B3DS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_B3DS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA24, DRAM_DATA25, DRAM_DATA26,
 * DRAM_DATA27, DRAM_DATA28, DRAM_DATA29, DRAM_DATA30, DRAM_DATA31
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_B4DS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_B4DS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_b4ds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_b4ds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_b4ds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_B4DS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_ADDR      (REGS_IOMUXC_BASE + 0x7a0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_B4DS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_b4ds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_B4DS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_B4DS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_B4DS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_B4DS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA32, DRAM_DATA33, DRAM_DATA34,
 * DRAM_DATA35, DRAM_DATA36, DRAM_DATA37, DRAM_DATA38, DRAM_DATA39
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_B5DS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_B5DS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_b5ds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_b5ds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_b5ds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_B5DS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_ADDR      (REGS_IOMUXC_BASE + 0x7a4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_B5DS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_b5ds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_B5DS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_B5DS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_B5DS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_B5DS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA40, DRAM_DATA41, DRAM_DATA42,
 * DRAM_DATA43, DRAM_DATA44, DRAM_DATA45, DRAM_DATA46, DRAM_DATA47
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_B6DS - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_B6DS - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000030
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_b6ds
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_b6ds_bitfields
    {
        unsigned RESERVED0 : 3; //!< [2:0] Reserved
        unsigned DSE : 3; //!< [5:3] Drive Strength Field
        unsigned RESERVED1 : 26; //!< [31:6] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_b6ds_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_B6DS register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_ADDR      (REGS_IOMUXC_BASE + 0x7a8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_B6DS           (*(volatile hw_iomuxc_sw_pad_ctl_grp_b6ds_t *) HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_B6DS.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_B6DS.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_B6DS bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_B6DS, field DSE[5:3] (RW)
 *
 * Select one of next values for group: . Affected pads: DRAM_DATA48, DRAM_DATA49, DRAM_DATA50,
 * DRAM_DATA51, DRAM_DATA52, DRAM_DATA53, DRAM_DATA54, DRAM_DATA55
 *
 * Values:
 * - HIZ = 000 - HI-Z
 * - 240_OHM = 001 - 240 Ohm
 * - 120_OHM = 010 - 120 Ohm
 * - 80_OHM = 011 - 80 Ohm
 * - 60_OHM = 100 - 60 Ohm
 * - 48_OHM = 101 - 48 Ohm
 * - 40_OHM = 110 - 40 Ohm
 * - 34_OHM = 111 - 34 Ohm
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE      (3)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE.
#define BM_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE      (0x00000038)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE) >> BP_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE) & BM_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DSE field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR((HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE) | BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE(BV_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE__HIZ (0x0) //!< HI-Z
#define BV_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE__240_OHM (0x1) //!< 240 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE__120_OHM (0x2) //!< 120 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE__80_OHM (0x3) //!< 80 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE__60_OHM (0x4) //!< 60 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE__48_OHM (0x5) //!< 48 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE__40_OHM (0x6) //!< 40 Ohm
#define BV_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE__34_OHM (0x7) //!< 34 Ohm
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM - Pad Group Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM - Pad Group Control Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sw_pad_ctl_grp_rgmii_term
{
    reg32_t U;
    struct _hw_iomuxc_sw_pad_ctl_grp_rgmii_term_bitfields
    {
        unsigned RESERVED0 : 8; //!< [7:0] Reserved
        unsigned ODT : 3; //!< [10:8] On Die Termination Field
        unsigned RESERVED1 : 21; //!< [31:11] Reserved
    } B;
} hw_iomuxc_sw_pad_ctl_grp_rgmii_term_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM register
 */
//@{
#define HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ADDR      (REGS_IOMUXC_BASE + 0x7ac)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM           (*(volatile hw_iomuxc_sw_pad_ctl_grp_rgmii_term_t *) HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ADDR)
#define HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_RD()      (HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM.U)
#define HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(v)     (HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM.U = (v))
#define HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_SET(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_RD() |  (v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_CLR(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_RD() & ~(v)))
#define HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_TOG(v)    (HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM bitfields
 */

/*! @name Register IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM, field ODT[10:8] (RW)
 *
 * Select one of next values for group: . Affected pads: RGMII_RD0, RGMII_RD1, RGMII_RD2, RGMII_RD3,
 * RGMII_RXC, RGMII_RX_CTL
 *
 * Values:
 * - DISABLED = 000 - Disabled
 * - 120_OHM = 001 - 120 Ohm ODT
 * - 60_OHM = 010 - 60 Ohm ODT
 * - 40_OHM = 011 - 40 Ohm ODT
 * - 30_OHM = 100 - 30 Ohm ODT
 * - RESERVED0 = 101 - Reserved
 * - 20_OHM = 110 - 20 Ohm ODT
 * - RESERVED1 = 111 - Reserved
 */
//@{
#define BP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT      (8)      //!< Bit position for IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT.
#define BM_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT      (0x00000700)  //!< Bit mask for IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT.

//! @brief Get value of IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT from a register value.
#define BG_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT) >> BP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT)

//! @brief Format value for bitfield IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT.
#define BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT) & BM_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODT field to a new value.
#define BW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT(v)   (HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR((HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_RD() & ~BM_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT) | BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT_V(v) BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT(BV_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT__##v)

#define BV_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT__DISABLED (0x0) //!< Disabled
#define BV_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT__120_OHM (0x1) //!< 120 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT__60_OHM (0x2) //!< 60 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT__40_OHM (0x3) //!< 40 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT__30_OHM (0x4) //!< 30 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT__RESERVED0 (0x5) //!< Reserved
#define BV_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT__20_OHM (0x6) //!< 20 Ohm ODT
#define BV_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT__RESERVED1 (0x7) //!< Reserved
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_asrc_asrck_clock_6_select_input
{
    reg32_t U;
    struct _hw_iomuxc_asrc_asrck_clock_6_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_asrc_asrck_clock_6_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7b0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT           (*(volatile hw_iomuxc_asrc_asrck_clock_6_select_input_t *) HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_RD()      (HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT.U)
#define HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_WR(v)     (HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_SET(v)    (HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_WR(HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_WR(HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_WR(HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: asrc, In Pin: asrck_clock_6
 *
 * Values:
 * - KEY_ROW3_ALT1 = 00 - Selecting ALT1 mode of pad KEY_ROW3 for ASRC_EXT_CLK.
 * - GPIO00_ALT3 = 01 - Selecting ALT3 mode of pad GPIO_0 for ASRC_EXT_CLK.
 * - GPIO18_ALT4 = 10 - Selecting ALT4 mode of pad GPIO_18 for ASRC_EXT_CLK.
 */
//@{
#define BP_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY) >> BP_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY) & BM_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_WR((HW_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_RD() & ~BM_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY) | BF_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY(BV_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY__KEY_ROW3_ALT1 (0x0) //!< Selecting ALT1 mode of pad KEY_ROW3 for ASRC_EXT_CLK.
#define BV_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY__GPIO00_ALT3 (0x1) //!< Selecting ALT3 mode of pad GPIO_0 for ASRC_EXT_CLK.
#define BV_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT_DAISY__GPIO18_ALT4 (0x2) //!< Selecting ALT4 mode of pad GPIO_18 for ASRC_EXT_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud4_input_da_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud4_input_da_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud4_input_da_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7b4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud4_input_da_amx_select_input_t *) HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p4_input_da_amx
 *
 * Values:
 * - SD2_DATA0_ALT3 = 0 - Selecting ALT3 mode of pad SD2_DAT0 for AUD4_RXD.
 * - DISP0_DATA23_ALT3 = 1 - Selecting ALT3 mode of pad DISP0_DAT23 for AUD4_RXD.
 */
//@{
#define BP_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY__SD2_DATA0_ALT3 (0x0) //!< Selecting ALT3 mode of pad SD2_DAT0 for AUD4_RXD.
#define BV_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT_DAISY__DISP0_DATA23_ALT3 (0x1) //!< Selecting ALT3 mode of pad DISP0_DAT23 for AUD4_RXD.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud4_input_db_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud4_input_db_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud4_input_db_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7b8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud4_input_db_amx_select_input_t *) HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p4_input_db_amx
 *
 * Values:
 * - SD2_DATA2_ALT3 = 0 - Selecting ALT3 mode of pad SD2_DAT2 for AUD4_TXD.
 * - DISP0_DATA21_ALT3 = 1 - Selecting ALT3 mode of pad DISP0_DAT21 for AUD4_TXD.
 */
//@{
#define BP_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY__SD2_DATA2_ALT3 (0x0) //!< Selecting ALT3 mode of pad SD2_DAT2 for AUD4_TXD.
#define BV_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT_DAISY__DISP0_DATA21_ALT3 (0x1) //!< Selecting ALT3 mode of pad DISP0_DAT21 for AUD4_TXD.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud4_input_rxclk_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud4_input_rxclk_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud4_input_rxclk_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7bc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud4_input_rxclk_amx_select_input_t *) HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p4_input_rxclk_amx
 *
 * Values:
 * - DISP0_DATA19_ALT4 = 0 - Selecting ALT4 mode of pad DISP0_DAT19 for AUD4_RXC.
 * - SD2_CMD_ALT3 = 1 - Selecting ALT3 mode of pad SD2_CMD for AUD4_RXC.
 */
//@{
#define BP_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY__DISP0_DATA19_ALT4 (0x0) //!< Selecting ALT4 mode of pad DISP0_DAT19 for AUD4_RXC.
#define BV_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY__SD2_CMD_ALT3 (0x1) //!< Selecting ALT3 mode of pad SD2_CMD for AUD4_RXC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud4_input_rxfs_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud4_input_rxfs_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud4_input_rxfs_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7c0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud4_input_rxfs_amx_select_input_t *) HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p4_input_rxfs_amx
 *
 * Values:
 * - DISP0_DATA18_ALT4 = 0 - Selecting ALT4 mode of pad DISP0_DAT18 for AUD4_RXFS.
 * - SD2_CLK_ALT3 = 1 - Selecting ALT3 mode of pad SD2_CLK for AUD4_RXFS.
 */
//@{
#define BP_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY__DISP0_DATA18_ALT4 (0x0) //!< Selecting ALT4 mode of pad DISP0_DAT18 for AUD4_RXFS.
#define BV_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY__SD2_CLK_ALT3 (0x1) //!< Selecting ALT3 mode of pad SD2_CLK for AUD4_RXFS.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud4_input_txclk_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud4_input_txclk_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud4_input_txclk_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7c4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud4_input_txclk_amx_select_input_t *) HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p4_input_txclk_amx
 *
 * Values:
 * - DISP0_DATA20_ALT3 = 0 - Selecting ALT3 mode of pad DISP0_DAT20 for AUD4_TXC.
 * - SD2_DATA3_ALT3 = 1 - Selecting ALT3 mode of pad SD2_DAT3 for AUD4_TXC.
 */
//@{
#define BP_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY__DISP0_DATA20_ALT3 (0x0) //!< Selecting ALT3 mode of pad DISP0_DAT20 for AUD4_TXC.
#define BV_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY__SD2_DATA3_ALT3 (0x1) //!< Selecting ALT3 mode of pad SD2_DAT3 for AUD4_TXC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud4_input_txfs_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud4_input_txfs_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud4_input_txfs_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7c8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud4_input_txfs_amx_select_input_t *) HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p4_input_txfs_amx
 *
 * Values:
 * - SD2_DATA1_ALT3 = 0 - Selecting ALT3 mode of pad SD2_DAT1 for AUD4_TXFS.
 * - DISP0_DATA22_ALT3 = 1 - Selecting ALT3 mode of pad DISP0_DAT22 for AUD4_TXFS.
 */
//@{
#define BP_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY__SD2_DATA1_ALT3 (0x0) //!< Selecting ALT3 mode of pad SD2_DAT1 for AUD4_TXFS.
#define BV_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY__DISP0_DATA22_ALT3 (0x1) //!< Selecting ALT3 mode of pad DISP0_DAT22 for AUD4_TXFS.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud5_input_da_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud5_input_da_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud5_input_da_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7cc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud5_input_da_amx_select_input_t *) HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p5_input_da_amx
 *
 * Values:
 * - DISP0_DATA19_ALT3 = 0 - Selecting ALT3 mode of pad DISP0_DAT19 for AUD5_RXD.
 * - KEY_ROW1_ALT2 = 1 - Selecting ALT2 mode of pad KEY_ROW1 for AUD5_RXD.
 */
//@{
#define BP_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY__DISP0_DATA19_ALT3 (0x0) //!< Selecting ALT3 mode of pad DISP0_DAT19 for AUD5_RXD.
#define BV_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY__KEY_ROW1_ALT2 (0x1) //!< Selecting ALT2 mode of pad KEY_ROW1 for AUD5_RXD.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud5_input_db_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud5_input_db_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud5_input_db_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7d0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud5_input_db_amx_select_input_t *) HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p5_input_db_amx
 *
 * Values:
 * - DISP0_DATA17_ALT3 = 0 - Selecting ALT3 mode of pad DISP0_DAT17 for AUD5_TXD.
 * - KEY_ROW0_ALT2 = 1 - Selecting ALT2 mode of pad KEY_ROW0 for AUD5_TXD.
 */
//@{
#define BP_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY__DISP0_DATA17_ALT3 (0x0) //!< Selecting ALT3 mode of pad DISP0_DAT17 for AUD5_TXD.
#define BV_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT_DAISY__KEY_ROW0_ALT2 (0x1) //!< Selecting ALT2 mode of pad KEY_ROW0 for AUD5_TXD.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud5_input_rxclk_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud5_input_rxclk_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud5_input_rxclk_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7d4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud5_input_rxclk_amx_select_input_t *) HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p5_input_rxclk_amx
 *
 * Values:
 * - EIM_DATA25_ALT6 = 0 - Selecting ALT6 mode of pad EIM_D25 for AUD5_RXC.
 * - DISP0_DATA14_ALT3 = 1 - Selecting ALT3 mode of pad DISP0_DAT14 for AUD5_RXC.
 */
//@{
#define BP_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY__EIM_DATA25_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_D25 for AUD5_RXC.
#define BV_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY__DISP0_DATA14_ALT3 (0x1) //!< Selecting ALT3 mode of pad DISP0_DAT14 for AUD5_RXC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud5_input_rxfs_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud5_input_rxfs_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud5_input_rxfs_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7d8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud5_input_rxfs_amx_select_input_t *) HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p5_input_rxfs_amx
 *
 * Values:
 * - EIM_DATA24_ALT6 = 0 - Selecting ALT6 mode of pad EIM_D24 for AUD5_RXFS.
 * - DISP0_DATA13_ALT3 = 1 - Selecting ALT3 mode of pad DISP0_DAT13 for AUD5_RXFS.
 */
//@{
#define BP_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY__EIM_DATA24_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_D24 for AUD5_RXFS.
#define BV_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY__DISP0_DATA13_ALT3 (0x1) //!< Selecting ALT3 mode of pad DISP0_DAT13 for AUD5_RXFS.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud5_input_txclk_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud5_input_txclk_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud5_input_txclk_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7dc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud5_input_txclk_amx_select_input_t *) HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p5_input_txclk_amx
 *
 * Values:
 * - DISP0_DATA16_ALT3 = 0 - Selecting ALT3 mode of pad DISP0_DAT16 for AUD5_TXC.
 * - KEY_COL0_ALT2 = 1 - Selecting ALT2 mode of pad KEY_COL0 for AUD5_TXC.
 */
//@{
#define BP_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY__DISP0_DATA16_ALT3 (0x0) //!< Selecting ALT3 mode of pad DISP0_DAT16 for AUD5_TXC.
#define BV_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY__KEY_COL0_ALT2 (0x1) //!< Selecting ALT2 mode of pad KEY_COL0 for AUD5_TXC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_aud5_input_txfs_amx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_aud5_input_txfs_amx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_aud5_input_txfs_amx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7e0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT           (*(volatile hw_iomuxc_aud5_input_txfs_amx_select_input_t *) HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_RD()      (HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT.U)
#define HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_WR(v)     (HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_SET(v)    (HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_WR(HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: audmux, In Pin: p5_input_txfs_amx
 *
 * Values:
 * - DISP0_DATA18_ALT3 = 0 - Selecting ALT3 mode of pad DISP0_DAT18 for AUD5_TXFS.
 * - KEY_COL1_ALT2 = 1 - Selecting ALT2 mode of pad KEY_COL1 for AUD5_TXFS.
 */
//@{
#define BP_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY) >> BP_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY) & BM_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_WR((HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_RD() & ~BM_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY) | BF_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(BV_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY__DISP0_DATA18_ALT3 (0x0) //!< Selecting ALT3 mode of pad DISP0_DAT18 for AUD5_TXFS.
#define BV_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY__KEY_COL1_ALT2 (0x1) //!< Selecting ALT2 mode of pad KEY_COL1 for AUD5_TXFS.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_flexcan1_rx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_flexcan1_rx_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_flexcan1_rx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_FLEXCAN1_RX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7e4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT           (*(volatile hw_iomuxc_flexcan1_rx_select_input_t *) HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_RD()      (HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT.U)
#define HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(v)     (HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_SET(v)    (HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_FLEXCAN1_RX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_FLEXCAN1_RX_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: flexcan1, In Pin: ipp_ind_canrx
 *
 * Values:
 * - KEY_ROW2_ALT2 = 00 - Selecting ALT2 mode of pad KEY_ROW2 for FLEXCAN1_RX.
 * - GPIO08_ALT3 = 01 - Selecting ALT3 mode of pad GPIO_8 for FLEXCAN1_RX.
 * - SD3_CLK_ALT2 = 10 - Selecting ALT2 mode of pad SD3_CLK for FLEXCAN1_RX.
 */
//@{
#define BP_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY) >> BP_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY) & BM_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR((HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_RD() & ~BM_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY) | BF_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY(BV_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY__KEY_ROW2_ALT2 (0x0) //!< Selecting ALT2 mode of pad KEY_ROW2 for FLEXCAN1_RX.
#define BV_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY__GPIO08_ALT3 (0x1) //!< Selecting ALT3 mode of pad GPIO_8 for FLEXCAN1_RX.
#define BV_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY__SD3_CLK_ALT2 (0x2) //!< Selecting ALT2 mode of pad SD3_CLK for FLEXCAN1_RX.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_flexcan2_rx_select_input
{
    reg32_t U;
    struct _hw_iomuxc_flexcan2_rx_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_flexcan2_rx_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_FLEXCAN2_RX_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7e8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT           (*(volatile hw_iomuxc_flexcan2_rx_select_input_t *) HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_ADDR)
#define HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_RD()      (HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT.U)
#define HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(v)     (HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT.U = (v))
#define HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_SET(v)    (HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_CLR(v)    (HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_TOG(v)    (HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_FLEXCAN2_RX_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_FLEXCAN2_RX_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: flexcan2, In Pin: ipp_ind_canrx
 *
 * Values:
 * - KEY_ROW4_ALT0 = 0 - Selecting ALT0 mode of pad KEY_ROW4 for FLEXCAN2_RX.
 * - SD3_DATA1_ALT2 = 1 - Selecting ALT2 mode of pad SD3_DAT1 for FLEXCAN2_RX.
 */
//@{
#define BP_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY.
#define BM_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY) >> BP_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY.
#define BF_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY) & BM_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR((HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_RD() & ~BM_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY) | BF_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY(BV_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY__KEY_ROW4_ALT0 (0x0) //!< Selecting ALT0 mode of pad KEY_ROW4 for FLEXCAN2_RX.
#define BV_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY__SD3_DATA1_ALT2 (0x1) //!< Selecting ALT2 mode of pad SD3_DAT1 for FLEXCAN2_RX.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ccm_pmic_ready_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ccm_pmic_ready_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ccm_pmic_ready_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_CCM_PMIC_READY_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7f0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT           (*(volatile hw_iomuxc_ccm_pmic_ready_select_input_t *) HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_ADDR)
#define HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_RD()      (HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT.U)
#define HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_WR(v)     (HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT.U = (v))
#define HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_SET(v)    (HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_WR(HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_CLR(v)    (HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_WR(HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_TOG(v)    (HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_WR(HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_CCM_PMIC_READY_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_CCM_PMIC_READY_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ccm, In Pin: pmic_vfuncional_ready
 *
 * Values:
 * - EIM_EB0_ALT4 = 0 - Selecting ALT4 mode of pad EIM_EB0 for CCM_PMIC_READY.
 * - GPIO17_ALT2 = 1 - Selecting ALT2 mode of pad GPIO_17 for CCM_PMIC_READY.
 */
//@{
#define BP_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY.
#define BM_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY) >> BP_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY.
#define BF_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY) & BM_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_WR((HW_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_RD() & ~BM_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY) | BF_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY(BV_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY__EIM_EB0_ALT4 (0x0) //!< Selecting ALT4 mode of pad EIM_EB0 for CCM_PMIC_READY.
#define BV_IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY__GPIO17_ALT2 (0x1) //!< Selecting ALT2 mode of pad GPIO_17 for CCM_PMIC_READY.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi1_cspi_clk_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi1_cspi_clk_in_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_ecspi1_cspi_clk_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7f4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi1_cspi_clk_in_select_input_t *) HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi1, In Pin: ipp_cspi_clk_in
 *
 * Values:
 * - EIM_DATA16_ALT1 = 00 - Selecting ALT1 mode of pad EIM_D16 for ECSPI1_SCLK.
 * - DISP0_DATA20_ALT2 = 01 - Selecting ALT2 mode of pad DISP0_DAT20 for ECSPI1_SCLK.
 * - KEY_COL0_ALT0 = 10 - Selecting ALT0 mode of pad KEY_COL0 for ECSPI1_SCLK.
 * - CSI0_DATA04_ALT2 = 11 - Selecting ALT2 mode of pad CSI0_DAT4 for ECSPI1_SCLK.
 */
//@{
#define BP_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_WR((HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY__EIM_DATA16_ALT1 (0x0) //!< Selecting ALT1 mode of pad EIM_D16 for ECSPI1_SCLK.
#define BV_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY__DISP0_DATA20_ALT2 (0x1) //!< Selecting ALT2 mode of pad DISP0_DAT20 for ECSPI1_SCLK.
#define BV_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY__KEY_COL0_ALT0 (0x2) //!< Selecting ALT0 mode of pad KEY_COL0 for ECSPI1_SCLK.
#define BV_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY__CSI0_DATA04_ALT2 (0x3) //!< Selecting ALT2 mode of pad CSI0_DAT4 for ECSPI1_SCLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi1_miso_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi1_miso_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_ecspi1_miso_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI1_MISO_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7f8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi1_miso_select_input_t *) HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI1_MISO_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI1_MISO_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi1, In Pin: ipp_ind_miso
 *
 * Values:
 * - EIM_DATA17_ALT1 = 00 - Selecting ALT1 mode of pad EIM_D17 for ECSPI1_MISO.
 * - DISP0_DATA22_ALT2 = 01 - Selecting ALT2 mode of pad DISP0_DAT22 for ECSPI1_MISO.
 * - KEY_COL1_ALT0 = 10 - Selecting ALT0 mode of pad KEY_COL1 for ECSPI1_MISO.
 * - CSI0_DATA06_ALT2 = 11 - Selecting ALT2 mode of pad CSI0_DAT6 for ECSPI1_MISO.
 */
//@{
#define BP_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_WR((HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY__EIM_DATA17_ALT1 (0x0) //!< Selecting ALT1 mode of pad EIM_D17 for ECSPI1_MISO.
#define BV_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY__DISP0_DATA22_ALT2 (0x1) //!< Selecting ALT2 mode of pad DISP0_DAT22 for ECSPI1_MISO.
#define BV_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY__KEY_COL1_ALT0 (0x2) //!< Selecting ALT0 mode of pad KEY_COL1 for ECSPI1_MISO.
#define BV_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY__CSI0_DATA06_ALT2 (0x3) //!< Selecting ALT2 mode of pad CSI0_DAT6 for ECSPI1_MISO.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi1_mosi_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi1_mosi_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_ecspi1_mosi_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI1_MOSI_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x7fc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi1_mosi_select_input_t *) HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI1_MOSI_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI1_MOSI_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi1, In Pin: ipp_ind_mosi
 *
 * Values:
 * - EIM_DATA18_ALT1 = 00 - Selecting ALT1 mode of pad EIM_D18 for ECSPI1_MOSI.
 * - DISP0_DATA21_ALT2 = 01 - Selecting ALT2 mode of pad DISP0_DAT21 for ECSPI1_MOSI.
 * - KEY_ROW0_ALT0 = 10 - Selecting ALT0 mode of pad KEY_ROW0 for ECSPI1_MOSI.
 * - CSI0_DATA05_ALT2 = 11 - Selecting ALT2 mode of pad CSI0_DAT5 for ECSPI1_MOSI.
 */
//@{
#define BP_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_WR((HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY__EIM_DATA18_ALT1 (0x0) //!< Selecting ALT1 mode of pad EIM_D18 for ECSPI1_MOSI.
#define BV_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY__DISP0_DATA21_ALT2 (0x1) //!< Selecting ALT2 mode of pad DISP0_DAT21 for ECSPI1_MOSI.
#define BV_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY__KEY_ROW0_ALT0 (0x2) //!< Selecting ALT0 mode of pad KEY_ROW0 for ECSPI1_MOSI.
#define BV_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY__CSI0_DATA05_ALT2 (0x3) //!< Selecting ALT2 mode of pad CSI0_DAT5 for ECSPI1_MOSI.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi1_ss0_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi1_ss0_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_ecspi1_ss0_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI1_SS0_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x800)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi1_ss0_select_input_t *) HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI1_SS0_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI1_SS0_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi1, In Pin: ipp_ind_ss_b[0]
 *
 * Values:
 * - EIM_EB2_ALT1 = 00 - Selecting ALT1 mode of pad EIM_EB2 for ECSPI1_SS0.
 * - DISP0_DATA23_ALT2 = 01 - Selecting ALT2 mode of pad DISP0_DAT23 for ECSPI1_SS0.
 * - KEY_ROW1_ALT0 = 10 - Selecting ALT0 mode of pad KEY_ROW1 for ECSPI1_SS0.
 * - CSI0_DATA07_ALT2 = 11 - Selecting ALT2 mode of pad CSI0_DAT7 for ECSPI1_SS0.
 */
//@{
#define BP_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_WR((HW_IOMUXC_ECSPI1_SS0_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY__EIM_EB2_ALT1 (0x0) //!< Selecting ALT1 mode of pad EIM_EB2 for ECSPI1_SS0.
#define BV_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY__DISP0_DATA23_ALT2 (0x1) //!< Selecting ALT2 mode of pad DISP0_DAT23 for ECSPI1_SS0.
#define BV_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY__KEY_ROW1_ALT0 (0x2) //!< Selecting ALT0 mode of pad KEY_ROW1 for ECSPI1_SS0.
#define BV_IOMUXC_ECSPI1_SS0_SELECT_INPUT_DAISY__CSI0_DATA07_ALT2 (0x3) //!< Selecting ALT2 mode of pad CSI0_DAT7 for ECSPI1_SS0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi1_ss1_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi1_ss1_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_ecspi1_ss1_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI1_SS1_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x804)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi1_ss1_select_input_t *) HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI1_SS1_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI1_SS1_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi1, In Pin: ipp_ind_ss_b[1]
 *
 * Values:
 * - EIM_DATA19_ALT1 = 00 - Selecting ALT1 mode of pad EIM_D19 for ECSPI1_SS1.
 * - DISP0_DATA15_ALT2 = 01 - Selecting ALT2 mode of pad DISP0_DAT15 for ECSPI1_SS1.
 * - KEY_COL2_ALT0 = 10 - Selecting ALT0 mode of pad KEY_COL2 for ECSPI1_SS1.
 */
//@{
#define BP_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_WR((HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY__EIM_DATA19_ALT1 (0x0) //!< Selecting ALT1 mode of pad EIM_D19 for ECSPI1_SS1.
#define BV_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY__DISP0_DATA15_ALT2 (0x1) //!< Selecting ALT2 mode of pad DISP0_DAT15 for ECSPI1_SS1.
#define BV_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY__KEY_COL2_ALT0 (0x2) //!< Selecting ALT0 mode of pad KEY_COL2 for ECSPI1_SS1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi1_ss2_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi1_ss2_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ecspi1_ss2_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI1_SS2_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x808)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi1_ss2_select_input_t *) HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI1_SS2_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI1_SS2_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi1, In Pin: ipp_ind_ss_b[2]
 *
 * Values:
 * - EIM_DATA24_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D24 for ECSPI1_SS2.
 * - KEY_ROW2_ALT0 = 1 - Selecting ALT0 mode of pad KEY_ROW2 for ECSPI1_SS2.
 */
//@{
#define BP_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_WR((HW_IOMUXC_ECSPI1_SS2_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY__EIM_DATA24_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D24 for ECSPI1_SS2.
#define BV_IOMUXC_ECSPI1_SS2_SELECT_INPUT_DAISY__KEY_ROW2_ALT0 (0x1) //!< Selecting ALT0 mode of pad KEY_ROW2 for ECSPI1_SS2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi1_ss3_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi1_ss3_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ecspi1_ss3_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI1_SS3_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x80c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi1_ss3_select_input_t *) HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_WR(HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI1_SS3_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI1_SS3_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi1, In Pin: ipp_ind_ss_b[3]
 *
 * Values:
 * - EIM_DATA25_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D25 for ECSPI1_SS3.
 * - KEY_COL3_ALT0 = 1 - Selecting ALT0 mode of pad KEY_COL3 for ECSPI1_SS3.
 */
//@{
#define BP_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_WR((HW_IOMUXC_ECSPI1_SS3_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY__EIM_DATA25_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D25 for ECSPI1_SS3.
#define BV_IOMUXC_ECSPI1_SS3_SELECT_INPUT_DAISY__KEY_COL3_ALT0 (0x1) //!< Selecting ALT0 mode of pad KEY_COL3 for ECSPI1_SS3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi2_cspi_clk_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi2_cspi_clk_in_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_ecspi2_cspi_clk_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x810)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi2_cspi_clk_in_select_input_t *) HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi2, In Pin: ipp_cspi_clk_in
 *
 * Values:
 * - EIM_CS0_ALT2 = 00 - Selecting ALT2 mode of pad EIM_CS0 for ECSPI2_SCLK.
 * - DISP0_DATA19_ALT2 = 01 - Selecting ALT2 mode of pad DISP0_DAT19 for ECSPI2_SCLK.
 * - CSI0_DATA08_ALT2 = 10 - Selecting ALT2 mode of pad CSI0_DAT8 for ECSPI2_SCLK.
 */
//@{
#define BP_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_WR((HW_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY__EIM_CS0_ALT2 (0x0) //!< Selecting ALT2 mode of pad EIM_CS0 for ECSPI2_SCLK.
#define BV_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY__DISP0_DATA19_ALT2 (0x1) //!< Selecting ALT2 mode of pad DISP0_DAT19 for ECSPI2_SCLK.
#define BV_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT_DAISY__CSI0_DATA08_ALT2 (0x2) //!< Selecting ALT2 mode of pad CSI0_DAT8 for ECSPI2_SCLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi2_miso_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi2_miso_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_ecspi2_miso_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI2_MISO_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x814)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi2_miso_select_input_t *) HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI2_MISO_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI2_MISO_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi2, In Pin: ipp_ind_miso
 *
 * Values:
 * - EIM_OE_ALT2 = 00 - Selecting ALT2 mode of pad EIM_OE for ECSPI2_MISO.
 * - DISP0_DATA17_ALT2 = 01 - Selecting ALT2 mode of pad DISP0_DAT17 for ECSPI2_MISO.
 * - CSI0_DATA10_ALT2 = 10 - Selecting ALT2 mode of pad CSI0_DAT10 for ECSPI2_MISO.
 */
//@{
#define BP_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_WR((HW_IOMUXC_ECSPI2_MISO_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY__EIM_OE_ALT2 (0x0) //!< Selecting ALT2 mode of pad EIM_OE for ECSPI2_MISO.
#define BV_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY__DISP0_DATA17_ALT2 (0x1) //!< Selecting ALT2 mode of pad DISP0_DAT17 for ECSPI2_MISO.
#define BV_IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY__CSI0_DATA10_ALT2 (0x2) //!< Selecting ALT2 mode of pad CSI0_DAT10 for ECSPI2_MISO.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi2_mosi_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi2_mosi_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_ecspi2_mosi_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI2_MOSI_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x818)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi2_mosi_select_input_t *) HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI2_MOSI_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI2_MOSI_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi2, In Pin: ipp_ind_mosi
 *
 * Values:
 * - EIM_CS1_ALT2 = 00 - Selecting ALT2 mode of pad EIM_CS1 for ECSPI2_MOSI.
 * - DISP0_DATA16_ALT2 = 01 - Selecting ALT2 mode of pad DISP0_DAT16 for ECSPI2_MOSI.
 * - CSI0_DATA09_ALT2 = 10 - Selecting ALT2 mode of pad CSI0_DAT9 for ECSPI2_MOSI.
 */
//@{
#define BP_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_WR((HW_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY__EIM_CS1_ALT2 (0x0) //!< Selecting ALT2 mode of pad EIM_CS1 for ECSPI2_MOSI.
#define BV_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY__DISP0_DATA16_ALT2 (0x1) //!< Selecting ALT2 mode of pad DISP0_DAT16 for ECSPI2_MOSI.
#define BV_IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY__CSI0_DATA09_ALT2 (0x2) //!< Selecting ALT2 mode of pad CSI0_DAT9 for ECSPI2_MOSI.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi2_ss0_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi2_ss0_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_ecspi2_ss0_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI2_SS0_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x81c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi2_ss0_select_input_t *) HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI2_SS0_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI2_SS0_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi2, In Pin: ipp_ind_ss_b[0]
 *
 * Values:
 * - EIM_RW_ALT2 = 00 - Selecting ALT2 mode of pad EIM_RW for ECSPI2_SS0.
 * - DISP0_DATA18_ALT2 = 01 - Selecting ALT2 mode of pad DISP0_DAT18 for ECSPI2_SS0.
 * - CSI0_DATA11_ALT2 = 10 - Selecting ALT2 mode of pad CSI0_DAT11 for ECSPI2_SS0.
 */
//@{
#define BP_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_WR((HW_IOMUXC_ECSPI2_SS0_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY__EIM_RW_ALT2 (0x0) //!< Selecting ALT2 mode of pad EIM_RW for ECSPI2_SS0.
#define BV_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY__DISP0_DATA18_ALT2 (0x1) //!< Selecting ALT2 mode of pad DISP0_DAT18 for ECSPI2_SS0.
#define BV_IOMUXC_ECSPI2_SS0_SELECT_INPUT_DAISY__CSI0_DATA11_ALT2 (0x2) //!< Selecting ALT2 mode of pad CSI0_DAT11 for ECSPI2_SS0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi2_ss1_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi2_ss1_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ecspi2_ss1_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI2_SS1_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x820)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi2_ss1_select_input_t *) HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_WR(HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI2_SS1_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI2_SS1_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi2, In Pin: ipp_ind_ss_b[1]
 *
 * Values:
 * - EIM_LBA_ALT2 = 0 - Selecting ALT2 mode of pad EIM_LBA for ECSPI2_SS1.
 * - DISP0_DATA15_ALT3 = 1 - Selecting ALT3 mode of pad DISP0_DAT15 for ECSPI2_SS1.
 */
//@{
#define BP_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_WR((HW_IOMUXC_ECSPI2_SS1_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY__EIM_LBA_ALT2 (0x0) //!< Selecting ALT2 mode of pad EIM_LBA for ECSPI2_SS1.
#define BV_IOMUXC_ECSPI2_SS1_SELECT_INPUT_DAISY__DISP0_DATA15_ALT3 (0x1) //!< Selecting ALT3 mode of pad DISP0_DAT15 for ECSPI2_SS1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi4_ss0_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi4_ss0_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ecspi4_ss0_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI4_SS0_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x824)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi4_ss0_select_input_t *) HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI4_SS0_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI4_SS0_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi4, In Pin: ipp_ind_ss_b[0]
 *
 * Values:
 * - EIM_DATA20_ALT1 = 0 - Selecting ALT1 mode of pad EIM_D20 for ECSPI4_SS0.
 * - EIM_DATA29_ALT2 = 1 - Selecting ALT2 mode of pad EIM_D29 for ECSPI4_SS0.
 */
//@{
#define BP_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_WR((HW_IOMUXC_ECSPI4_SS0_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY__EIM_DATA20_ALT1 (0x0) //!< Selecting ALT1 mode of pad EIM_D20 for ECSPI4_SS0.
#define BV_IOMUXC_ECSPI4_SS0_SELECT_INPUT_DAISY__EIM_DATA29_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_D29 for ECSPI4_SS0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi5_cspi_clk_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi5_cspi_clk_in_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ecspi5_cspi_clk_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x828)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi5_cspi_clk_in_select_input_t *) HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi5, In Pin: ipp_cspi_clk_in
 *
 * Values:
 * - SD1_CLK_ALT1 = 0 - Selecting ALT1 mode of pad SD1_CLK for ECSPI5_SCLK.
 * - SD2_CLK_ALT1 = 1 - Selecting ALT1 mode of pad SD2_CLK for ECSPI5_SCLK.
 */
//@{
#define BP_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_WR((HW_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY__SD1_CLK_ALT1 (0x0) //!< Selecting ALT1 mode of pad SD1_CLK for ECSPI5_SCLK.
#define BV_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT_DAISY__SD2_CLK_ALT1 (0x1) //!< Selecting ALT1 mode of pad SD2_CLK for ECSPI5_SCLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi5_miso_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi5_miso_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ecspi5_miso_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI5_MISO_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x82c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi5_miso_select_input_t *) HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI5_MISO_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI5_MISO_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi5, In Pin: ipp_ind_miso
 *
 * Values:
 * - SD2_DATA0_ALT1 = 0 - Selecting ALT1 mode of pad SD2_DAT0 for ECSPI5_MISO.
 * - SD1_DATA0_ALT1 = 1 - Selecting ALT1 mode of pad SD1_DAT0 for ECSPI5_MISO.
 */
//@{
#define BP_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_WR((HW_IOMUXC_ECSPI5_MISO_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY__SD2_DATA0_ALT1 (0x0) //!< Selecting ALT1 mode of pad SD2_DAT0 for ECSPI5_MISO.
#define BV_IOMUXC_ECSPI5_MISO_SELECT_INPUT_DAISY__SD1_DATA0_ALT1 (0x1) //!< Selecting ALT1 mode of pad SD1_DAT0 for ECSPI5_MISO.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi5_mosi_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi5_mosi_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ecspi5_mosi_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI5_MOSI_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x830)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi5_mosi_select_input_t *) HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI5_MOSI_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI5_MOSI_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi5, In Pin: ipp_ind_mosi
 *
 * Values:
 * - SD1_CMD_ALT1 = 0 - Selecting ALT1 mode of pad SD1_CMD for ECSPI5_MOSI.
 * - SD2_CMD_ALT1 = 1 - Selecting ALT1 mode of pad SD2_CMD for ECSPI5_MOSI.
 */
//@{
#define BP_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_WR((HW_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY__SD1_CMD_ALT1 (0x0) //!< Selecting ALT1 mode of pad SD1_CMD for ECSPI5_MOSI.
#define BV_IOMUXC_ECSPI5_MOSI_SELECT_INPUT_DAISY__SD2_CMD_ALT1 (0x1) //!< Selecting ALT1 mode of pad SD2_CMD for ECSPI5_MOSI.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi5_ss0_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi5_ss0_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ecspi5_ss0_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI5_SS0_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x834)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi5_ss0_select_input_t *) HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI5_SS0_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI5_SS0_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi5, In Pin: ipp_ind_ss_b[0]
 *
 * Values:
 * - SD2_DATA1_ALT1 = 0 - Selecting ALT1 mode of pad SD2_DAT1 for ECSPI5_SS0.
 * - SD1_DATA1_ALT1 = 1 - Selecting ALT1 mode of pad SD1_DAT1 for ECSPI5_SS0.
 */
//@{
#define BP_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_WR((HW_IOMUXC_ECSPI5_SS0_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY__SD2_DATA1_ALT1 (0x0) //!< Selecting ALT1 mode of pad SD2_DAT1 for ECSPI5_SS0.
#define BV_IOMUXC_ECSPI5_SS0_SELECT_INPUT_DAISY__SD1_DATA1_ALT1 (0x1) //!< Selecting ALT1 mode of pad SD1_DAT1 for ECSPI5_SS0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ecspi5_ss1_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ecspi5_ss1_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ecspi5_ss1_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ECSPI5_SS1_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x838)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT           (*(volatile hw_iomuxc_ecspi5_ss1_select_input_t *) HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_RD()      (HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT.U)
#define HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_WR(v)     (HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_SET(v)    (HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_WR(HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ECSPI5_SS1_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ECSPI5_SS1_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ecspi5, In Pin: ipp_ind_ss_b[1]
 *
 * Values:
 * - SD2_DATA2_ALT1 = 0 - Selecting ALT1 mode of pad SD2_DAT2 for ECSPI5_SS1.
 * - SD1_DATA2_ALT1 = 1 - Selecting ALT1 mode of pad SD1_DAT2 for ECSPI5_SS1.
 */
//@{
#define BP_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY) >> BP_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY) & BM_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_WR((HW_IOMUXC_ECSPI5_SS1_SELECT_INPUT_RD() & ~BM_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY) | BF_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY(BV_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY__SD2_DATA2_ALT1 (0x0) //!< Selecting ALT1 mode of pad SD2_DAT2 for ECSPI5_SS1.
#define BV_IOMUXC_ECSPI5_SS1_SELECT_INPUT_DAISY__SD1_DATA2_ALT1 (0x1) //!< Selecting ALT1 mode of pad SD1_DAT2 for ECSPI5_SS1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_enet_ref_clk_select_input
{
    reg32_t U;
    struct _hw_iomuxc_enet_ref_clk_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_enet_ref_clk_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ENET_REF_CLK_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x83c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT           (*(volatile hw_iomuxc_enet_ref_clk_select_input_t *) HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_RD()      (HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT.U)
#define HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_WR(v)     (HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_SET(v)    (HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_WR(HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_WR(HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_WR(HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ENET_REF_CLK_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ENET_REF_CLK_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: enet, In Pin: ipg_clk_rmii
 *
 * Values:
 * - RGMII_TX_CTL_ALT7 = 0 - Selecting ALT7 mode of pad RGMII_TX_CTL for ENET_REF_CLK.
 * - GPIO16_ALT2 = 1 - Selecting ALT2 mode of pad GPIO_16 for ENET_REF_CLK.
 */
//@{
#define BP_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY) >> BP_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY) & BM_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_WR((HW_IOMUXC_ENET_REF_CLK_SELECT_INPUT_RD() & ~BM_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY) | BF_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY(BV_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY__RGMII_TX_CTL_ALT7 (0x0) //!< Selecting ALT7 mode of pad RGMII_TX_CTL for ENET_REF_CLK.
#define BV_IOMUXC_ENET_REF_CLK_SELECT_INPUT_DAISY__GPIO16_ALT2 (0x1) //!< Selecting ALT2 mode of pad GPIO_16 for ENET_REF_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_enet_mac0_mdio_select_input
{
    reg32_t U;
    struct _hw_iomuxc_enet_mac0_mdio_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_enet_mac0_mdio_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x840)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT           (*(volatile hw_iomuxc_enet_mac0_mdio_select_input_t *) HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_RD()      (HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT.U)
#define HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_WR(v)     (HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_SET(v)    (HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: enet, In Pin: ipp_ind_mac0_mdio
 *
 * Values:
 * - ENET_MDIO_ALT1 = 0 - Selecting ALT1 mode of pad ENET_MDIO for ENET_MDIO.
 * - KEY_COL1_ALT1 = 1 - Selecting ALT1 mode of pad KEY_COL1 for ENET_MDIO.
 */
//@{
#define BP_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY) >> BP_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY) & BM_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_WR((HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_RD() & ~BM_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY) | BF_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY(BV_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY__ENET_MDIO_ALT1 (0x0) //!< Selecting ALT1 mode of pad ENET_MDIO for ENET_MDIO.
#define BV_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY__KEY_COL1_ALT1 (0x1) //!< Selecting ALT1 mode of pad KEY_COL1 for ENET_MDIO.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_enet_mac0_rx_clk_select_input
{
    reg32_t U;
    struct _hw_iomuxc_enet_mac0_rx_clk_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_enet_mac0_rx_clk_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x844)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT           (*(volatile hw_iomuxc_enet_mac0_rx_clk_select_input_t *) HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_RD()      (HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT.U)
#define HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_WR(v)     (HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_SET(v)    (HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: enet, In Pin: ipp_ind_mac0_rxclk
 *
 * Values:
 * - RGMII_RXC_ALT1 = 0 - Selecting ALT1 mode of pad RGMII_RXC for RGMII_RXC.
 * - GPIO18_ALT1 = 1 - Selecting ALT1 mode of pad GPIO_18 for ENET_RX_CLK.
 */
//@{
#define BP_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY) >> BP_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY) & BM_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_WR((HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_RD() & ~BM_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY) | BF_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY(BV_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY__RGMII_RXC_ALT1 (0x0) //!< Selecting ALT1 mode of pad RGMII_RXC for RGMII_RXC.
#define BV_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY__GPIO18_ALT1 (0x1) //!< Selecting ALT1 mode of pad GPIO_18 for ENET_RX_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_enet_mac0_rx_data0_select_input
{
    reg32_t U;
    struct _hw_iomuxc_enet_mac0_rx_data0_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_enet_mac0_rx_data0_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x848)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT           (*(volatile hw_iomuxc_enet_mac0_rx_data0_select_input_t *) HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_RD()      (HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT.U)
#define HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_WR(v)     (HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_SET(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: enet, In Pin: ipp_ind_mac0_rxdata[0]
 *
 * Values:
 * - RGMII_RD0_ALT1 = 0 - Selecting ALT1 mode of pad RGMII_RD0 for RGMII_RD0.
 * - ENET_RX_DATA0_ALT1 = 1 - Selecting ALT1 mode of pad ENET_RXD0 for ENET_RX_DATA0.
 */
//@{
#define BP_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY) >> BP_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY) & BM_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_WR((HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_RD() & ~BM_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY) | BF_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY(BV_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY__RGMII_RD0_ALT1 (0x0) //!< Selecting ALT1 mode of pad RGMII_RD0 for RGMII_RD0.
#define BV_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY__ENET_RX_DATA0_ALT1 (0x1) //!< Selecting ALT1 mode of pad ENET_RXD0 for ENET_RX_DATA0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_enet_mac0_rx_data1_select_input
{
    reg32_t U;
    struct _hw_iomuxc_enet_mac0_rx_data1_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_enet_mac0_rx_data1_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x84c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT           (*(volatile hw_iomuxc_enet_mac0_rx_data1_select_input_t *) HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_RD()      (HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT.U)
#define HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_WR(v)     (HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_SET(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: enet, In Pin: ipp_ind_mac0_rxdata[1]
 *
 * Values:
 * - RGMII_RD1_ALT1 = 0 - Selecting ALT1 mode of pad RGMII_RD1 for RGMII_RD1.
 * - ENET_RX_DATA1_ALT1 = 1 - Selecting ALT1 mode of pad ENET_RXD1 for ENET_RX_DATA1.
 */
//@{
#define BP_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY) >> BP_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY) & BM_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_WR((HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_RD() & ~BM_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY) | BF_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY(BV_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY__RGMII_RD1_ALT1 (0x0) //!< Selecting ALT1 mode of pad RGMII_RD1 for RGMII_RD1.
#define BV_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY__ENET_RX_DATA1_ALT1 (0x1) //!< Selecting ALT1 mode of pad ENET_RXD1 for ENET_RX_DATA1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_enet_mac0_rx_data2_select_input
{
    reg32_t U;
    struct _hw_iomuxc_enet_mac0_rx_data2_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_enet_mac0_rx_data2_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x850)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT           (*(volatile hw_iomuxc_enet_mac0_rx_data2_select_input_t *) HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_RD()      (HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT.U)
#define HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_WR(v)     (HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_SET(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: enet, In Pin: ipp_ind_mac0_rxdata[2]
 *
 * Values:
 * - RGMII_RD2_ALT1 = 0 - Selecting ALT1 mode of pad RGMII_RD2 for RGMII_RD2.
 * - KEY_COL2_ALT1 = 1 - Selecting ALT1 mode of pad KEY_COL2 for ENET_RX_DATA2.
 */
//@{
#define BP_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY) >> BP_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY) & BM_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_WR((HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_RD() & ~BM_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY) | BF_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY(BV_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY__RGMII_RD2_ALT1 (0x0) //!< Selecting ALT1 mode of pad RGMII_RD2 for RGMII_RD2.
#define BV_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY__KEY_COL2_ALT1 (0x1) //!< Selecting ALT1 mode of pad KEY_COL2 for ENET_RX_DATA2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_enet_mac0_rx_data3_select_input
{
    reg32_t U;
    struct _hw_iomuxc_enet_mac0_rx_data3_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_enet_mac0_rx_data3_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x854)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT           (*(volatile hw_iomuxc_enet_mac0_rx_data3_select_input_t *) HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_RD()      (HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT.U)
#define HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_WR(v)     (HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_SET(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: enet, In Pin: ipp_ind_mac0_rxdata[3]
 *
 * Values:
 * - RGMII_RD3_ALT1 = 0 - Selecting ALT1 mode of pad RGMII_RD3 for RGMII_RD3.
 * - KEY_COL0_ALT1 = 1 - Selecting ALT1 mode of pad KEY_COL0 for ENET_RX_DATA3.
 */
//@{
#define BP_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY) >> BP_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY) & BM_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_WR((HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_RD() & ~BM_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY) | BF_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY(BV_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY__RGMII_RD3_ALT1 (0x0) //!< Selecting ALT1 mode of pad RGMII_RD3 for RGMII_RD3.
#define BV_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY__KEY_COL0_ALT1 (0x1) //!< Selecting ALT1 mode of pad KEY_COL0 for ENET_RX_DATA3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_enet_mac0_rx_en_select_input
{
    reg32_t U;
    struct _hw_iomuxc_enet_mac0_rx_en_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_enet_mac0_rx_en_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x858)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT           (*(volatile hw_iomuxc_enet_mac0_rx_en_select_input_t *) HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_RD()      (HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT.U)
#define HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_WR(v)     (HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_SET(v)    (HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_WR(HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: enet, In Pin: ipp_ind_mac0_rxen
 *
 * Values:
 * - RGMII_RX_CTL_ALT1 = 0 - Selecting ALT1 mode of pad RGMII_RX_CTL for RGMII_RX_CTL.
 * - ENET_CRS_DV_ALT1 = 1 - Selecting ALT1 mode of pad ENET_CRS_DV for ENET_RX_EN.
 */
//@{
#define BP_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY) >> BP_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY) & BM_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_WR((HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_RD() & ~BM_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY) | BF_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY(BV_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY__RGMII_RX_CTL_ALT1 (0x0) //!< Selecting ALT1 mode of pad RGMII_RX_CTL for RGMII_RX_CTL.
#define BV_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY__ENET_CRS_DV_ALT1 (0x1) //!< Selecting ALT1 mode of pad ENET_CRS_DV for ENET_RX_EN.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_rx_fs_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_rx_fs_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_rx_fs_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_RX_FS_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x85c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT           (*(volatile hw_iomuxc_esai_rx_fs_select_input_t *) HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_WR(HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_WR(HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_WR(HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_RX_FS_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_RX_FS_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_fsr
 *
 * Values:
 * - ENET_REF_CLK_ALT2 = 0 - Selecting ALT2 mode of pad ENET_REF_CLK for ESAI_RX_FS.
 * - GPIO09_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_9 for ESAI_RX_FS.
 */
//@{
#define BP_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_WR((HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY__ENET_REF_CLK_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_REF_CLK for ESAI_RX_FS.
#define BV_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY__GPIO09_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_9 for ESAI_RX_FS.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_tx_fs_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_tx_fs_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_tx_fs_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_TX_FS_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x860)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT           (*(volatile hw_iomuxc_esai_tx_fs_select_input_t *) HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_WR(HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_WR(HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_WR(HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_TX_FS_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_TX_FS_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_fst
 *
 * Values:
 * - ENET_RX_DATA1_ALT2 = 0 - Selecting ALT2 mode of pad ENET_RXD1 for ESAI_TX_FS.
 * - GPIO02_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_2 for ESAI_TX_FS.
 */
//@{
#define BP_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_WR((HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY__ENET_RX_DATA1_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_RXD1 for ESAI_TX_FS.
#define BV_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY__GPIO02_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_2 for ESAI_TX_FS.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_rx_hf_clk_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_rx_hf_clk_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_rx_hf_clk_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x864)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT           (*(volatile hw_iomuxc_esai_rx_hf_clk_select_input_t *) HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_hckr
 *
 * Values:
 * - ENET_RX_ER_ALT2 = 0 - Selecting ALT2 mode of pad ENET_RX_ER for ESAI_RX_HF_CLK.
 * - GPIO03_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_3 for ESAI_RX_HF_CLK.
 */
//@{
#define BP_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_WR((HW_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY__ENET_RX_ER_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_RX_ER for ESAI_RX_HF_CLK.
#define BV_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT_DAISY__GPIO03_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_3 for ESAI_RX_HF_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_tx_hf_clk_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_tx_hf_clk_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_tx_hf_clk_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x868)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT           (*(volatile hw_iomuxc_esai_tx_hf_clk_select_input_t *) HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_hckt
 *
 * Values:
 * - ENET_RX_DATA0_ALT2 = 0 - Selecting ALT2 mode of pad ENET_RXD0 for ESAI_TX_HF_CLK.
 * - GPIO04_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_4 for ESAI_TX_HF_CLK.
 */
//@{
#define BP_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_WR((HW_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY__ENET_RX_DATA0_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_RXD0 for ESAI_TX_HF_CLK.
#define BV_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT_DAISY__GPIO04_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_4 for ESAI_TX_HF_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_rx_clk_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_rx_clk_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_rx_clk_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_RX_CLK_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x86c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT           (*(volatile hw_iomuxc_esai_rx_clk_select_input_t *) HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_RX_CLK_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_RX_CLK_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_sckr
 *
 * Values:
 * - ENET_MDIO_ALT2 = 0 - Selecting ALT2 mode of pad ENET_MDIO for ESAI_RX_CLK.
 * - GPIO01_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_1 for ESAI_RX_CLK.
 */
//@{
#define BP_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_WR((HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY__ENET_MDIO_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_MDIO for ESAI_RX_CLK.
#define BV_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY__GPIO01_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_1 for ESAI_RX_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_tx_clk_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_tx_clk_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_tx_clk_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_TX_CLK_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x870)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT           (*(volatile hw_iomuxc_esai_tx_clk_select_input_t *) HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_WR(HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_TX_CLK_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_TX_CLK_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_sckt
 *
 * Values:
 * - ENET_CRS_DV_ALT2 = 0 - Selecting ALT2 mode of pad ENET_CRS_DV for ESAI_TX_CLK.
 * - GPIO06_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_6 for ESAI_TX_CLK.
 */
//@{
#define BP_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_WR((HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY__ENET_CRS_DV_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_CRS_DV for ESAI_TX_CLK.
#define BV_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY__GPIO06_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_6 for ESAI_TX_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_SDO0_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_SDO0_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_sdo0_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_sdo0_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_sdo0_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_SDO0_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x874)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_SDO0_SELECT_INPUT           (*(volatile hw_iomuxc_esai_sdo0_select_input_t *) HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_SDO0_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_SDO0_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_SDO0_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_SDO0_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_sdo0
 *
 * Values:
 * - GPIO17_ALT0 = 0 - Selecting ALT0 mode of pad GPIO_17 for ESAI_TX0.
 * - NAND_CS2_B_ALT2 = 1 - Selecting ALT2 mode of pad NANDF_CS2 for ESAI_TX0.
 */
//@{
#define BP_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_WR((HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY__GPIO17_ALT0 (0x0) //!< Selecting ALT0 mode of pad GPIO_17 for ESAI_TX0.
#define BV_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY__NAND_CS2_B_ALT2 (0x1) //!< Selecting ALT2 mode of pad NANDF_CS2 for ESAI_TX0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_SDO1_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_SDO1_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_sdo1_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_sdo1_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_sdo1_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_SDO1_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x878)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_SDO1_SELECT_INPUT           (*(volatile hw_iomuxc_esai_sdo1_select_input_t *) HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_SDO1_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_SDO1_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_SDO1_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_SDO1_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_sdo1
 *
 * Values:
 * - GPIO18_ALT0 = 0 - Selecting ALT0 mode of pad GPIO_18 for ESAI_TX1.
 * - NAND_CS3_B_ALT2 = 1 - Selecting ALT2 mode of pad NANDF_CS3 for ESAI_TX1.
 */
//@{
#define BP_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_WR((HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY__GPIO18_ALT0 (0x0) //!< Selecting ALT0 mode of pad GPIO_18 for ESAI_TX1.
#define BV_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY__NAND_CS3_B_ALT2 (0x1) //!< Selecting ALT2 mode of pad NANDF_CS3 for ESAI_TX1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_sdo2_sdi3_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_sdo2_sdi3_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_sdo2_sdi3_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x87c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT           (*(volatile hw_iomuxc_esai_sdo2_sdi3_select_input_t *) HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_sdo2_sdi3
 *
 * Values:
 * - ENET_TX_DATA1_ALT2 = 0 - Selecting ALT2 mode of pad ENET_TXD1 for ESAI_TX2_RX3.
 * - GPIO05_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_5 for ESAI_TX2_RX3.
 */
//@{
#define BP_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_WR((HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY__ENET_TX_DATA1_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_TXD1 for ESAI_TX2_RX3.
#define BV_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY__GPIO05_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_5 for ESAI_TX2_RX3.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_sdo3_sdi2_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_sdo3_sdi2_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_sdo3_sdi2_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x880)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT           (*(volatile hw_iomuxc_esai_sdo3_sdi2_select_input_t *) HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_sdo3_sdi2
 *
 * Values:
 * - ENET_TX_EN_ALT2 = 0 - Selecting ALT2 mode of pad ENET_TX_EN for ESAI_TX3_RX2.
 * - GPIO16_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_16 for ESAI_TX3_RX2.
 */
//@{
#define BP_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_WR((HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY__ENET_TX_EN_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_TX_EN for ESAI_TX3_RX2.
#define BV_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY__GPIO16_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_16 for ESAI_TX3_RX2.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_sdo4_sdi1_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_sdo4_sdi1_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_sdo4_sdi1_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x884)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT           (*(volatile hw_iomuxc_esai_sdo4_sdi1_select_input_t *) HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_sdo4_sdi1
 *
 * Values:
 * - ENET_TX_DATA0_ALT2 = 0 - Selecting ALT2 mode of pad ENET_TXD0 for ESAI_TX4_RX1.
 * - GPIO07_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_7 for ESAI_TX4_RX1.
 */
//@{
#define BP_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_WR((HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY__ENET_TX_DATA0_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_TXD0 for ESAI_TX4_RX1.
#define BV_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY__GPIO07_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_7 for ESAI_TX4_RX1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_esai_sdo5_sdi0_select_input
{
    reg32_t U;
    struct _hw_iomuxc_esai_sdo5_sdi0_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_esai_sdo5_sdi0_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x888)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT           (*(volatile hw_iomuxc_esai_sdo5_sdi0_select_input_t *) HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_ADDR)
#define HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_RD()      (HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT.U)
#define HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_WR(v)     (HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT.U = (v))
#define HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_SET(v)    (HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_CLR(v)    (HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_TOG(v)    (HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_WR(HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: esai, In Pin: ipp_ind_sdo5_sdi0
 *
 * Values:
 * - ENET_MDC_ALT2 = 0 - Selecting ALT2 mode of pad ENET_MDC for ESAI_TX5_RX0.
 * - GPIO08_ALT0 = 1 - Selecting ALT0 mode of pad GPIO_8 for ESAI_TX5_RX0.
 */
//@{
#define BP_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY.
#define BM_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY) >> BP_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY.
#define BF_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY) & BM_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_WR((HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_RD() & ~BM_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY) | BF_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY(BV_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY__ENET_MDC_ALT2 (0x0) //!< Selecting ALT2 mode of pad ENET_MDC for ESAI_TX5_RX0.
#define BV_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY__GPIO08_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_8 for ESAI_TX5_RX0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_hdmi_icecin_select_input
{
    reg32_t U;
    struct _hw_iomuxc_hdmi_icecin_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_hdmi_icecin_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_HDMI_ICECIN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x88c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT           (*(volatile hw_iomuxc_hdmi_icecin_select_input_t *) HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_RD()      (HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT.U)
#define HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_WR(v)     (HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_SET(v)    (HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_WR(HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_WR(HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_WR(HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_HDMI_ICECIN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_HDMI_ICECIN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: hdmi, In Pin: icecin
 *
 * Values:
 * - EIM_ADDR25_ALT6 = 0 - Selecting ALT6 mode of pad EIM_A25 for HDMI_TX_CEC_LINE.
 * - KEY_ROW2_ALT6 = 1 - Selecting ALT6 mode of pad KEY_ROW2 for HDMI_TX_CEC_LINE.
 */
//@{
#define BP_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY) >> BP_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY) & BM_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_WR((HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_RD() & ~BM_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY) | BF_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY(BV_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY__EIM_ADDR25_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_A25 for HDMI_TX_CEC_LINE.
#define BV_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY__KEY_ROW2_ALT6 (0x1) //!< Selecting ALT6 mode of pad KEY_ROW2 for HDMI_TX_CEC_LINE.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_hdmi_ii2c_clkin_select_input
{
    reg32_t U;
    struct _hw_iomuxc_hdmi_ii2c_clkin_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_hdmi_ii2c_clkin_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x890)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT           (*(volatile hw_iomuxc_hdmi_ii2c_clkin_select_input_t *) HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_RD()      (HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT.U)
#define HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_WR(v)     (HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_SET(v)    (HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_WR(HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_WR(HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_WR(HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: hdmi, In Pin: ii2c_msth13tddc_sclin
 *
 * Values:
 * - EIM_EB2_ALT4 = 0 - Selecting ALT4 mode of pad EIM_EB2 for HDMI_TX_DDC_SCL.
 * - KEY_COL3_ALT2 = 1 - Selecting ALT2 mode of pad KEY_COL3 for HDMI_TX_DDC_SCL.
 */
//@{
#define BP_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY) >> BP_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY) & BM_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_WR((HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_RD() & ~BM_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY) | BF_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY(BV_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY__EIM_EB2_ALT4 (0x0) //!< Selecting ALT4 mode of pad EIM_EB2 for HDMI_TX_DDC_SCL.
#define BV_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY__KEY_COL3_ALT2 (0x1) //!< Selecting ALT2 mode of pad KEY_COL3 for HDMI_TX_DDC_SCL.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_hdmi_ii2c_datain_select_input
{
    reg32_t U;
    struct _hw_iomuxc_hdmi_ii2c_datain_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_hdmi_ii2c_datain_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x894)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT           (*(volatile hw_iomuxc_hdmi_ii2c_datain_select_input_t *) HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_RD()      (HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT.U)
#define HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_WR(v)     (HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_SET(v)    (HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_WR(HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_WR(HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_WR(HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: hdmi, In Pin: ii2c_msth13tddc_sdain
 *
 * Values:
 * - EIM_DATA16_ALT4 = 0 - Selecting ALT4 mode of pad EIM_D16 for HDMI_TX_DDC_SDA.
 * - KEY_ROW3_ALT2 = 1 - Selecting ALT2 mode of pad KEY_ROW3 for HDMI_TX_DDC_SDA.
 */
//@{
#define BP_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY) >> BP_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY) & BM_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_WR((HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_RD() & ~BM_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY) | BF_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY(BV_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY__EIM_DATA16_ALT4 (0x0) //!< Selecting ALT4 mode of pad EIM_D16 for HDMI_TX_DDC_SDA.
#define BV_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY__KEY_ROW3_ALT2 (0x1) //!< Selecting ALT2 mode of pad KEY_ROW3 for HDMI_TX_DDC_SDA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_i2c1_scl_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_i2c1_scl_in_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_i2c1_scl_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_I2C1_SCL_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x898)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT           (*(volatile hw_iomuxc_i2c1_scl_in_select_input_t *) HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_RD()      (HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT.U)
#define HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_I2C1_SCL_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_I2C1_SCL_IN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: i2c1, In Pin: ipp_scl_in
 *
 * Values:
 * - EIM_DATA21_ALT6 = 0 - Selecting ALT6 mode of pad EIM_D21 for I2C1_SCL.
 * - CSI0_DATA09_ALT4 = 1 - Selecting ALT4 mode of pad CSI0_DAT9 for I2C1_SCL.
 */
//@{
#define BP_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_WR((HW_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY__EIM_DATA21_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_D21 for I2C1_SCL.
#define BV_IOMUXC_I2C1_SCL_IN_SELECT_INPUT_DAISY__CSI0_DATA09_ALT4 (0x1) //!< Selecting ALT4 mode of pad CSI0_DAT9 for I2C1_SCL.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_i2c1_sda_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_i2c1_sda_in_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_i2c1_sda_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_I2C1_SDA_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x89c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT           (*(volatile hw_iomuxc_i2c1_sda_in_select_input_t *) HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_RD()      (HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT.U)
#define HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_I2C1_SDA_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_I2C1_SDA_IN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: i2c1, In Pin: ipp_sda_in
 *
 * Values:
 * - EIM_DATA28_ALT1 = 0 - Selecting ALT1 mode of pad EIM_D28 for I2C1_SDA.
 * - CSI0_DATA08_ALT4 = 1 - Selecting ALT4 mode of pad CSI0_DAT8 for I2C1_SDA.
 */
//@{
#define BP_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_WR((HW_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY__EIM_DATA28_ALT1 (0x0) //!< Selecting ALT1 mode of pad EIM_D28 for I2C1_SDA.
#define BV_IOMUXC_I2C1_SDA_IN_SELECT_INPUT_DAISY__CSI0_DATA08_ALT4 (0x1) //!< Selecting ALT4 mode of pad CSI0_DAT8 for I2C1_SDA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_i2c2_scl_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_i2c2_scl_in_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_i2c2_scl_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_I2C2_SCL_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8a0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT           (*(volatile hw_iomuxc_i2c2_scl_in_select_input_t *) HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_RD()      (HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT.U)
#define HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_I2C2_SCL_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_I2C2_SCL_IN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: i2c2, In Pin: ipp_scl_in
 *
 * Values:
 * - EIM_EB2_ALT6 = 0 - Selecting ALT6 mode of pad EIM_EB2 for I2C2_SCL.
 * - KEY_COL3_ALT4 = 1 - Selecting ALT4 mode of pad KEY_COL3 for I2C2_SCL.
 */
//@{
#define BP_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_WR((HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY__EIM_EB2_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_EB2 for I2C2_SCL.
#define BV_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY__KEY_COL3_ALT4 (0x1) //!< Selecting ALT4 mode of pad KEY_COL3 for I2C2_SCL.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_i2c2_sda_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_i2c2_sda_in_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_i2c2_sda_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_I2C2_SDA_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8a4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT           (*(volatile hw_iomuxc_i2c2_sda_in_select_input_t *) HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_RD()      (HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT.U)
#define HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_I2C2_SDA_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_I2C2_SDA_IN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: i2c2, In Pin: ipp_sda_in
 *
 * Values:
 * - EIM_DATA16_ALT6 = 0 - Selecting ALT6 mode of pad EIM_D16 for I2C2_SDA.
 * - KEY_ROW3_ALT4 = 1 - Selecting ALT4 mode of pad KEY_ROW3 for I2C2_SDA.
 */
//@{
#define BP_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_WR((HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY__EIM_DATA16_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_D16 for I2C2_SDA.
#define BV_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY__KEY_ROW3_ALT4 (0x1) //!< Selecting ALT4 mode of pad KEY_ROW3 for I2C2_SDA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_i2c3_scl_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_i2c3_scl_in_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_i2c3_scl_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_I2C3_SCL_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8a8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT           (*(volatile hw_iomuxc_i2c3_scl_in_select_input_t *) HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_RD()      (HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT.U)
#define HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_I2C3_SCL_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_I2C3_SCL_IN_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: i2c3, In Pin: ipp_scl_in
 *
 * Values:
 * - EIM_DATA17_ALT6 = 00 - Selecting ALT6 mode of pad EIM_D17 for I2C3_SCL.
 * - GPIO03_ALT2 = 01 - Selecting ALT2 mode of pad GPIO_3 for I2C3_SCL.
 * - GPIO05_ALT6 = 10 - Selecting ALT6 mode of pad GPIO_5 for I2C3_SCL.
 */
//@{
#define BP_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_WR((HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY__EIM_DATA17_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_D17 for I2C3_SCL.
#define BV_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY__GPIO03_ALT2 (0x1) //!< Selecting ALT2 mode of pad GPIO_3 for I2C3_SCL.
#define BV_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY__GPIO05_ALT6 (0x2) //!< Selecting ALT6 mode of pad GPIO_5 for I2C3_SCL.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_i2c3_sda_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_i2c3_sda_in_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_i2c3_sda_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_I2C3_SDA_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8ac)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT           (*(volatile hw_iomuxc_i2c3_sda_in_select_input_t *) HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_RD()      (HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT.U)
#define HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_WR(HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_I2C3_SDA_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_I2C3_SDA_IN_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: i2c3, In Pin: ipp_sda_in
 *
 * Values:
 * - EIM_DATA18_ALT6 = 00 - Selecting ALT6 mode of pad EIM_D18 for I2C3_SDA.
 * - GPIO06_ALT2 = 01 - Selecting ALT2 mode of pad GPIO_6 for I2C3_SDA.
 * - GPIO16_ALT6 = 10 - Selecting ALT6 mode of pad GPIO_16 for I2C3_SDA.
 */
//@{
#define BP_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_WR((HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY__EIM_DATA18_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_D18 for I2C3_SDA.
#define BV_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY__GPIO06_ALT2 (0x1) //!< Selecting ALT2 mode of pad GPIO_6 for I2C3_SDA.
#define BV_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY__GPIO16_ALT6 (0x2) //!< Selecting ALT6 mode of pad GPIO_16 for I2C3_SDA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data10_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data10_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data10_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8b0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data10_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[10]
 *
 * Values:
 * - EIM_DATA22_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D22 for IPU2_CSI1_DATA10.
 * - EIM_EB1_ALT2 = 1 - Selecting ALT2 mode of pad EIM_EB1 for IPU2_CSI1_DATA10.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY__EIM_DATA22_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D22 for IPU2_CSI1_DATA10.
#define BV_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT_DAISY__EIM_EB1_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_EB1 for IPU2_CSI1_DATA10.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data11_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data11_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data11_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8b4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data11_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[11]
 *
 * Values:
 * - EIM_DATA21_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D21 for IPU2_CSI1_DATA11.
 * - EIM_EB0_ALT2 = 1 - Selecting ALT2 mode of pad EIM_EB0 for IPU2_CSI1_DATA11.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY__EIM_DATA21_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D21 for IPU2_CSI1_DATA11.
#define BV_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT_DAISY__EIM_EB0_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_EB0 for IPU2_CSI1_DATA11.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data12_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data12_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data12_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8b8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data12_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[12]
 *
 * Values:
 * - EIM_DATA28_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D28 for IPU2_CSI1_DATA12.
 * - EIM_ADDR17_ALT2 = 1 - Selecting ALT2 mode of pad EIM_A17 for IPU2_CSI1_DATA12.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY__EIM_DATA28_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D28 for IPU2_CSI1_DATA12.
#define BV_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT_DAISY__EIM_ADDR17_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_A17 for IPU2_CSI1_DATA12.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data13_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data13_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data13_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8bc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data13_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[13]
 *
 * Values:
 * - EIM_DATA27_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D27 for IPU2_CSI1_DATA13.
 * - EIM_ADDR18_ALT2 = 1 - Selecting ALT2 mode of pad EIM_A18 for IPU2_CSI1_DATA13.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY__EIM_DATA27_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D27 for IPU2_CSI1_DATA13.
#define BV_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT_DAISY__EIM_ADDR18_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_A18 for IPU2_CSI1_DATA13.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data14_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data14_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data14_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8c0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data14_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[14]
 *
 * Values:
 * - EIM_DATA26_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D26 for IPU2_CSI1_DATA14.
 * - EIM_ADDR19_ALT2 = 1 - Selecting ALT2 mode of pad EIM_A19 for IPU2_CSI1_DATA14.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY__EIM_DATA26_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D26 for IPU2_CSI1_DATA14.
#define BV_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT_DAISY__EIM_ADDR19_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_A19 for IPU2_CSI1_DATA14.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data15_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data15_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data15_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8c4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data15_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[15]
 *
 * Values:
 * - EIM_DATA20_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D20 for IPU2_CSI1_DATA15.
 * - EIM_ADDR20_ALT2 = 1 - Selecting ALT2 mode of pad EIM_A20 for IPU2_CSI1_DATA15.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY__EIM_DATA20_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D20 for IPU2_CSI1_DATA15.
#define BV_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT_DAISY__EIM_ADDR20_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_A20 for IPU2_CSI1_DATA15.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data16_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data16_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data16_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8c8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data16_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[16]
 *
 * Values:
 * - EIM_DATA19_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D19 for IPU2_CSI1_DATA16.
 * - EIM_ADDR21_ALT2 = 1 - Selecting ALT2 mode of pad EIM_A21 for IPU2_CSI1_DATA16.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY__EIM_DATA19_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D19 for IPU2_CSI1_DATA16.
#define BV_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT_DAISY__EIM_ADDR21_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_A21 for IPU2_CSI1_DATA16.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data17_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data17_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data17_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8cc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data17_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[17]
 *
 * Values:
 * - EIM_DATA18_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D18 for IPU2_CSI1_DATA17.
 * - EIM_ADDR22_ALT2 = 1 - Selecting ALT2 mode of pad EIM_A22 for IPU2_CSI1_DATA17.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY__EIM_DATA18_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D18 for IPU2_CSI1_DATA17.
#define BV_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT_DAISY__EIM_ADDR22_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_A22 for IPU2_CSI1_DATA17.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data18_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data18_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data18_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8d0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data18_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[18]
 *
 * Values:
 * - EIM_DATA16_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D16 for IPU2_CSI1_DATA18.
 * - EIM_ADDR23_ALT2 = 1 - Selecting ALT2 mode of pad EIM_A23 for IPU2_CSI1_DATA18.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY__EIM_DATA16_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D16 for IPU2_CSI1_DATA18.
#define BV_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT_DAISY__EIM_ADDR23_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_A23 for IPU2_CSI1_DATA18.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data19_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data19_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data19_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8d4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data19_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data[19]
 *
 * Values:
 * - EIM_EB2_ALT3 = 0 - Selecting ALT3 mode of pad EIM_EB2 for IPU2_CSI1_DATA19.
 * - EIM_ADDR24_ALT2 = 1 - Selecting ALT2 mode of pad EIM_A24 for IPU2_CSI1_DATA19.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY__EIM_EB2_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_EB2 for IPU2_CSI1_DATA19.
#define BV_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT_DAISY__EIM_ADDR24_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_A24 for IPU2_CSI1_DATA19.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_data_en_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_data_en_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_data_en_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8d8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_data_en_select_input_t *) HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_data_en
 *
 * Values:
 * - EIM_DATA23_ALT4 = 0 - Selecting ALT4 mode of pad EIM_D23 for IPU2_CSI1_DATA_EN.
 * - EIM_AD10_ALT2 = 1 - Selecting ALT2 mode of pad EIM_DA10 for IPU2_CSI1_DATA_EN.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY__EIM_DATA23_ALT4 (0x0) //!< Selecting ALT4 mode of pad EIM_D23 for IPU2_CSI1_DATA_EN.
#define BV_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT_DAISY__EIM_AD10_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_DA10 for IPU2_CSI1_DATA_EN.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_hsync_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_hsync_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_hsync_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8dc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_hsync_select_input_t *) HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_hsync
 *
 * Values:
 * - EIM_EB3_ALT4 = 0 - Selecting ALT4 mode of pad EIM_EB3 for IPU2_CSI1_HSYNC.
 * - EIM_AD11_ALT2 = 1 - Selecting ALT2 mode of pad EIM_DA11 for IPU2_CSI1_HSYNC.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY__EIM_EB3_ALT4 (0x0) //!< Selecting ALT4 mode of pad EIM_EB3 for IPU2_CSI1_HSYNC.
#define BV_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT_DAISY__EIM_AD11_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_DA11 for IPU2_CSI1_HSYNC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_pix_clk_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_pix_clk_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_pix_clk_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8e0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_pix_clk_select_input_t *) HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_pix_clk
 *
 * Values:
 * - EIM_DATA17_ALT3 = 0 - Selecting ALT3 mode of pad EIM_D17 for IPU2_CSI1_PIXCLK.
 * - EIM_ADDR16_ALT2 = 1 - Selecting ALT2 mode of pad EIM_A16 for IPU2_CSI1_PIXCLK.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY__EIM_DATA17_ALT3 (0x0) //!< Selecting ALT3 mode of pad EIM_D17 for IPU2_CSI1_PIXCLK.
#define BV_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT_DAISY__EIM_ADDR16_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_A16 for IPU2_CSI1_PIXCLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_ipu2_sens1_vsync_select_input
{
    reg32_t U;
    struct _hw_iomuxc_ipu2_sens1_vsync_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_ipu2_sens1_vsync_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8e4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT           (*(volatile hw_iomuxc_ipu2_sens1_vsync_select_input_t *) HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_ADDR)
#define HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_RD()      (HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT.U)
#define HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_WR(v)     (HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT.U = (v))
#define HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_SET(v)    (HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_CLR(v)    (HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_TOG(v)    (HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_WR(HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: ipu2, In Pin: ipp_ind_sens1_vsync
 *
 * Values:
 * - EIM_DATA29_ALT6 = 0 - Selecting ALT6 mode of pad EIM_D29 for IPU2_CSI1_VSYNC.
 * - EIM_AD12_ALT2 = 1 - Selecting ALT2 mode of pad EIM_DA12 for IPU2_CSI1_VSYNC.
 */
//@{
#define BP_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY.
#define BM_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY) >> BP_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY.
#define BF_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY) & BM_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_WR((HW_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_RD() & ~BM_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY) | BF_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY(BV_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY__EIM_DATA29_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_D29 for IPU2_CSI1_VSYNC.
#define BV_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT_DAISY__EIM_AD12_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_DA12 for IPU2_CSI1_VSYNC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_KEY_COL5_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_KEY_COL5_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_key_col5_select_input
{
    reg32_t U;
    struct _hw_iomuxc_key_col5_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_key_col5_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_KEY_COL5_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_KEY_COL5_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8e8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_KEY_COL5_SELECT_INPUT           (*(volatile hw_iomuxc_key_col5_select_input_t *) HW_IOMUXC_KEY_COL5_SELECT_INPUT_ADDR)
#define HW_IOMUXC_KEY_COL5_SELECT_INPUT_RD()      (HW_IOMUXC_KEY_COL5_SELECT_INPUT.U)
#define HW_IOMUXC_KEY_COL5_SELECT_INPUT_WR(v)     (HW_IOMUXC_KEY_COL5_SELECT_INPUT.U = (v))
#define HW_IOMUXC_KEY_COL5_SELECT_INPUT_SET(v)    (HW_IOMUXC_KEY_COL5_SELECT_INPUT_WR(HW_IOMUXC_KEY_COL5_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_KEY_COL5_SELECT_INPUT_CLR(v)    (HW_IOMUXC_KEY_COL5_SELECT_INPUT_WR(HW_IOMUXC_KEY_COL5_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_KEY_COL5_SELECT_INPUT_TOG(v)    (HW_IOMUXC_KEY_COL5_SELECT_INPUT_WR(HW_IOMUXC_KEY_COL5_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_KEY_COL5_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_KEY_COL5_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: kpp, In Pin: ipp_ind_col[5]
 *
 * Values:
 * - GPIO00_ALT2 = 00 - Selecting ALT2 mode of pad GPIO_0 for KEY_COL5.
 * - GPIO19_ALT0 = 01 - Selecting ALT0 mode of pad GPIO_19 for KEY_COL5.
 * - CSI0_DATA04_ALT3 = 10 - Selecting ALT3 mode of pad CSI0_DAT4 for KEY_COL5.
 * - SD2_CLK_ALT2 = 11 - Selecting ALT2 mode of pad SD2_CLK for KEY_COL5.
 */
//@{
#define BP_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_KEY_COL5_SELECT_INPUT_DAISY.
#define BM_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_KEY_COL5_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_KEY_COL5_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY) >> BP_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_KEY_COL5_SELECT_INPUT_DAISY.
#define BF_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY) & BM_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_KEY_COL5_SELECT_INPUT_WR((HW_IOMUXC_KEY_COL5_SELECT_INPUT_RD() & ~BM_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY) | BF_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY(BV_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY__GPIO00_ALT2 (0x0) //!< Selecting ALT2 mode of pad GPIO_0 for KEY_COL5.
#define BV_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY__GPIO19_ALT0 (0x1) //!< Selecting ALT0 mode of pad GPIO_19 for KEY_COL5.
#define BV_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY__CSI0_DATA04_ALT3 (0x2) //!< Selecting ALT3 mode of pad CSI0_DAT4 for KEY_COL5.
#define BV_IOMUXC_KEY_COL5_SELECT_INPUT_DAISY__SD2_CLK_ALT2 (0x3) //!< Selecting ALT2 mode of pad SD2_CLK for KEY_COL5.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_KEY_COL6_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_KEY_COL6_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_key_col6_select_input
{
    reg32_t U;
    struct _hw_iomuxc_key_col6_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_key_col6_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_KEY_COL6_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_KEY_COL6_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8ec)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_KEY_COL6_SELECT_INPUT           (*(volatile hw_iomuxc_key_col6_select_input_t *) HW_IOMUXC_KEY_COL6_SELECT_INPUT_ADDR)
#define HW_IOMUXC_KEY_COL6_SELECT_INPUT_RD()      (HW_IOMUXC_KEY_COL6_SELECT_INPUT.U)
#define HW_IOMUXC_KEY_COL6_SELECT_INPUT_WR(v)     (HW_IOMUXC_KEY_COL6_SELECT_INPUT.U = (v))
#define HW_IOMUXC_KEY_COL6_SELECT_INPUT_SET(v)    (HW_IOMUXC_KEY_COL6_SELECT_INPUT_WR(HW_IOMUXC_KEY_COL6_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_KEY_COL6_SELECT_INPUT_CLR(v)    (HW_IOMUXC_KEY_COL6_SELECT_INPUT_WR(HW_IOMUXC_KEY_COL6_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_KEY_COL6_SELECT_INPUT_TOG(v)    (HW_IOMUXC_KEY_COL6_SELECT_INPUT_WR(HW_IOMUXC_KEY_COL6_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_KEY_COL6_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_KEY_COL6_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: kpp, In Pin: ipp_ind_col[6]
 *
 * Values:
 * - GPIO09_ALT2 = 00 - Selecting ALT2 mode of pad GPIO_9 for KEY_COL6.
 * - CSI0_DATA06_ALT3 = 01 - Selecting ALT3 mode of pad CSI0_DAT6 for KEY_COL6.
 * - SD2_DATA3_ALT2 = 10 - Selecting ALT2 mode of pad SD2_DAT3 for KEY_COL6.
 */
//@{
#define BP_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_KEY_COL6_SELECT_INPUT_DAISY.
#define BM_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_KEY_COL6_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_KEY_COL6_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY) >> BP_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_KEY_COL6_SELECT_INPUT_DAISY.
#define BF_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY) & BM_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_KEY_COL6_SELECT_INPUT_WR((HW_IOMUXC_KEY_COL6_SELECT_INPUT_RD() & ~BM_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY) | BF_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY(BV_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY__GPIO09_ALT2 (0x0) //!< Selecting ALT2 mode of pad GPIO_9 for KEY_COL6.
#define BV_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY__CSI0_DATA06_ALT3 (0x1) //!< Selecting ALT3 mode of pad CSI0_DAT6 for KEY_COL6.
#define BV_IOMUXC_KEY_COL6_SELECT_INPUT_DAISY__SD2_DATA3_ALT2 (0x2) //!< Selecting ALT2 mode of pad SD2_DAT3 for KEY_COL6.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_KEY_COL7_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_KEY_COL7_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_key_col7_select_input
{
    reg32_t U;
    struct _hw_iomuxc_key_col7_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_key_col7_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_KEY_COL7_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_KEY_COL7_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8f0)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_KEY_COL7_SELECT_INPUT           (*(volatile hw_iomuxc_key_col7_select_input_t *) HW_IOMUXC_KEY_COL7_SELECT_INPUT_ADDR)
#define HW_IOMUXC_KEY_COL7_SELECT_INPUT_RD()      (HW_IOMUXC_KEY_COL7_SELECT_INPUT.U)
#define HW_IOMUXC_KEY_COL7_SELECT_INPUT_WR(v)     (HW_IOMUXC_KEY_COL7_SELECT_INPUT.U = (v))
#define HW_IOMUXC_KEY_COL7_SELECT_INPUT_SET(v)    (HW_IOMUXC_KEY_COL7_SELECT_INPUT_WR(HW_IOMUXC_KEY_COL7_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_KEY_COL7_SELECT_INPUT_CLR(v)    (HW_IOMUXC_KEY_COL7_SELECT_INPUT_WR(HW_IOMUXC_KEY_COL7_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_KEY_COL7_SELECT_INPUT_TOG(v)    (HW_IOMUXC_KEY_COL7_SELECT_INPUT_WR(HW_IOMUXC_KEY_COL7_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_KEY_COL7_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_KEY_COL7_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: kpp, In Pin: ipp_ind_col[7]
 *
 * Values:
 * - SD2_DATA1_ALT4 = 00 - Selecting ALT4 mode of pad SD2_DAT1 for KEY_COL7.
 * - GPIO04_ALT2 = 01 - Selecting ALT2 mode of pad GPIO_4 for KEY_COL7.
 * - CSI0_DATA08_ALT3 = 10 - Selecting ALT3 mode of pad CSI0_DAT8 for KEY_COL7.
 */
//@{
#define BP_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_KEY_COL7_SELECT_INPUT_DAISY.
#define BM_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_KEY_COL7_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_KEY_COL7_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY) >> BP_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_KEY_COL7_SELECT_INPUT_DAISY.
#define BF_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY) & BM_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_KEY_COL7_SELECT_INPUT_WR((HW_IOMUXC_KEY_COL7_SELECT_INPUT_RD() & ~BM_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY) | BF_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY(BV_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY__SD2_DATA1_ALT4 (0x0) //!< Selecting ALT4 mode of pad SD2_DAT1 for KEY_COL7.
#define BV_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY__GPIO04_ALT2 (0x1) //!< Selecting ALT2 mode of pad GPIO_4 for KEY_COL7.
#define BV_IOMUXC_KEY_COL7_SELECT_INPUT_DAISY__CSI0_DATA08_ALT3 (0x2) //!< Selecting ALT3 mode of pad CSI0_DAT8 for KEY_COL7.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_KEY_ROW5_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_KEY_ROW5_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_key_row5_select_input
{
    reg32_t U;
    struct _hw_iomuxc_key_row5_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_key_row5_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_KEY_ROW5_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_KEY_ROW5_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8f4)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_KEY_ROW5_SELECT_INPUT           (*(volatile hw_iomuxc_key_row5_select_input_t *) HW_IOMUXC_KEY_ROW5_SELECT_INPUT_ADDR)
#define HW_IOMUXC_KEY_ROW5_SELECT_INPUT_RD()      (HW_IOMUXC_KEY_ROW5_SELECT_INPUT.U)
#define HW_IOMUXC_KEY_ROW5_SELECT_INPUT_WR(v)     (HW_IOMUXC_KEY_ROW5_SELECT_INPUT.U = (v))
#define HW_IOMUXC_KEY_ROW5_SELECT_INPUT_SET(v)    (HW_IOMUXC_KEY_ROW5_SELECT_INPUT_WR(HW_IOMUXC_KEY_ROW5_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_KEY_ROW5_SELECT_INPUT_CLR(v)    (HW_IOMUXC_KEY_ROW5_SELECT_INPUT_WR(HW_IOMUXC_KEY_ROW5_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_KEY_ROW5_SELECT_INPUT_TOG(v)    (HW_IOMUXC_KEY_ROW5_SELECT_INPUT_WR(HW_IOMUXC_KEY_ROW5_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_KEY_ROW5_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_KEY_ROW5_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: kpp, In Pin: ipp_ind_row[5]
 *
 * Values:
 * - GPIO01_ALT2 = 00 - Selecting ALT2 mode of pad GPIO_1 for KEY_ROW5.
 * - CSI0_DATA05_ALT3 = 01 - Selecting ALT3 mode of pad CSI0_DAT5 for KEY_ROW5.
 * - SD2_CMD_ALT2 = 10 - Selecting ALT2 mode of pad SD2_CMD for KEY_ROW5.
 */
//@{
#define BP_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY.
#define BM_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY) >> BP_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY.
#define BF_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY) & BM_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_KEY_ROW5_SELECT_INPUT_WR((HW_IOMUXC_KEY_ROW5_SELECT_INPUT_RD() & ~BM_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY) | BF_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY(BV_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY__GPIO01_ALT2 (0x0) //!< Selecting ALT2 mode of pad GPIO_1 for KEY_ROW5.
#define BV_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY__CSI0_DATA05_ALT3 (0x1) //!< Selecting ALT3 mode of pad CSI0_DAT5 for KEY_ROW5.
#define BV_IOMUXC_KEY_ROW5_SELECT_INPUT_DAISY__SD2_CMD_ALT2 (0x2) //!< Selecting ALT2 mode of pad SD2_CMD for KEY_ROW5.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_KEY_ROW6_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_KEY_ROW6_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_key_row6_select_input
{
    reg32_t U;
    struct _hw_iomuxc_key_row6_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_key_row6_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_KEY_ROW6_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_KEY_ROW6_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8f8)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_KEY_ROW6_SELECT_INPUT           (*(volatile hw_iomuxc_key_row6_select_input_t *) HW_IOMUXC_KEY_ROW6_SELECT_INPUT_ADDR)
#define HW_IOMUXC_KEY_ROW6_SELECT_INPUT_RD()      (HW_IOMUXC_KEY_ROW6_SELECT_INPUT.U)
#define HW_IOMUXC_KEY_ROW6_SELECT_INPUT_WR(v)     (HW_IOMUXC_KEY_ROW6_SELECT_INPUT.U = (v))
#define HW_IOMUXC_KEY_ROW6_SELECT_INPUT_SET(v)    (HW_IOMUXC_KEY_ROW6_SELECT_INPUT_WR(HW_IOMUXC_KEY_ROW6_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_KEY_ROW6_SELECT_INPUT_CLR(v)    (HW_IOMUXC_KEY_ROW6_SELECT_INPUT_WR(HW_IOMUXC_KEY_ROW6_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_KEY_ROW6_SELECT_INPUT_TOG(v)    (HW_IOMUXC_KEY_ROW6_SELECT_INPUT_WR(HW_IOMUXC_KEY_ROW6_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_KEY_ROW6_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_KEY_ROW6_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: kpp, In Pin: ipp_ind_row[6]
 *
 * Values:
 * - SD2_DATA2_ALT4 = 00 - Selecting ALT4 mode of pad SD2_DAT2 for KEY_ROW6.
 * - GPIO02_ALT2 = 01 - Selecting ALT2 mode of pad GPIO_2 for KEY_ROW6.
 * - CSI0_DATA07_ALT3 = 10 - Selecting ALT3 mode of pad CSI0_DAT7 for KEY_ROW6.
 */
//@{
#define BP_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY.
#define BM_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY) >> BP_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY.
#define BF_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY) & BM_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_KEY_ROW6_SELECT_INPUT_WR((HW_IOMUXC_KEY_ROW6_SELECT_INPUT_RD() & ~BM_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY) | BF_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY(BV_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY__SD2_DATA2_ALT4 (0x0) //!< Selecting ALT4 mode of pad SD2_DAT2 for KEY_ROW6.
#define BV_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY__GPIO02_ALT2 (0x1) //!< Selecting ALT2 mode of pad GPIO_2 for KEY_ROW6.
#define BV_IOMUXC_KEY_ROW6_SELECT_INPUT_DAISY__CSI0_DATA07_ALT3 (0x2) //!< Selecting ALT3 mode of pad CSI0_DAT7 for KEY_ROW6.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_KEY_ROW7_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_KEY_ROW7_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_key_row7_select_input
{
    reg32_t U;
    struct _hw_iomuxc_key_row7_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_key_row7_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_KEY_ROW7_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_KEY_ROW7_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x8fc)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_KEY_ROW7_SELECT_INPUT           (*(volatile hw_iomuxc_key_row7_select_input_t *) HW_IOMUXC_KEY_ROW7_SELECT_INPUT_ADDR)
#define HW_IOMUXC_KEY_ROW7_SELECT_INPUT_RD()      (HW_IOMUXC_KEY_ROW7_SELECT_INPUT.U)
#define HW_IOMUXC_KEY_ROW7_SELECT_INPUT_WR(v)     (HW_IOMUXC_KEY_ROW7_SELECT_INPUT.U = (v))
#define HW_IOMUXC_KEY_ROW7_SELECT_INPUT_SET(v)    (HW_IOMUXC_KEY_ROW7_SELECT_INPUT_WR(HW_IOMUXC_KEY_ROW7_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_KEY_ROW7_SELECT_INPUT_CLR(v)    (HW_IOMUXC_KEY_ROW7_SELECT_INPUT_WR(HW_IOMUXC_KEY_ROW7_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_KEY_ROW7_SELECT_INPUT_TOG(v)    (HW_IOMUXC_KEY_ROW7_SELECT_INPUT_WR(HW_IOMUXC_KEY_ROW7_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_KEY_ROW7_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_KEY_ROW7_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: kpp, In Pin: ipp_ind_row[7]
 *
 * Values:
 * - SD2_DATA0_ALT4 = 00 - Selecting ALT4 mode of pad SD2_DAT0 for KEY_ROW7.
 * - GPIO05_ALT2 = 01 - Selecting ALT2 mode of pad GPIO_5 for KEY_ROW7.
 * - CSI0_DATA09_ALT3 = 10 - Selecting ALT3 mode of pad CSI0_DAT9 for KEY_ROW7.
 */
//@{
#define BP_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY.
#define BM_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY) >> BP_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY.
#define BF_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY) & BM_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_KEY_ROW7_SELECT_INPUT_WR((HW_IOMUXC_KEY_ROW7_SELECT_INPUT_RD() & ~BM_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY) | BF_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY(BV_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY__SD2_DATA0_ALT4 (0x0) //!< Selecting ALT4 mode of pad SD2_DAT0 for KEY_ROW7.
#define BV_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY__GPIO05_ALT2 (0x1) //!< Selecting ALT2 mode of pad GPIO_5 for KEY_ROW7.
#define BV_IOMUXC_KEY_ROW7_SELECT_INPUT_DAISY__CSI0_DATA09_ALT3 (0x2) //!< Selecting ALT3 mode of pad CSI0_DAT9 for KEY_ROW7.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_mlb_mlb_clk_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_mlb_mlb_clk_in_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_mlb_mlb_clk_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x900)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT           (*(volatile hw_iomuxc_mlb_mlb_clk_in_select_input_t *) HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_RD()      (HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT.U)
#define HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_WR(HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: mlb, In Pin: mlb_clk_in
 *
 * Values:
 * - ENET_TX_DATA1_ALT0 = 0 - Selecting ALT0 mode of pad ENET_TXD1 for MLB_CLK.
 * - GPIO03_ALT7 = 1 - Selecting ALT7 mode of pad GPIO_3 for MLB_CLK.
 */
//@{
#define BP_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_WR((HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY(BV_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY__ENET_TX_DATA1_ALT0 (0x0) //!< Selecting ALT0 mode of pad ENET_TXD1 for MLB_CLK.
#define BV_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY__GPIO03_ALT7 (0x1) //!< Selecting ALT7 mode of pad GPIO_3 for MLB_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_mlb_mlb_data_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_mlb_mlb_data_in_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_mlb_mlb_data_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x904)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT           (*(volatile hw_iomuxc_mlb_mlb_data_in_select_input_t *) HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_RD()      (HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT.U)
#define HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_WR(HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_WR(HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_WR(HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: mlb, In Pin: mlb_data_in
 *
 * Values:
 * - ENET_MDC_ALT0 = 0 - Selecting ALT0 mode of pad ENET_MDC for MLB_DATA.
 * - GPIO02_ALT7 = 1 - Selecting ALT7 mode of pad GPIO_2 for MLB_DATA.
 */
//@{
#define BP_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_WR((HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY(BV_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY__ENET_MDC_ALT0 (0x0) //!< Selecting ALT0 mode of pad ENET_MDC for MLB_DATA.
#define BV_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY__GPIO02_ALT7 (0x1) //!< Selecting ALT7 mode of pad GPIO_2 for MLB_DATA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_mlb_mlb_sig_in_select_input
{
    reg32_t U;
    struct _hw_iomuxc_mlb_mlb_sig_in_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_mlb_mlb_sig_in_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x908)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT           (*(volatile hw_iomuxc_mlb_mlb_sig_in_select_input_t *) HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_ADDR)
#define HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_RD()      (HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT.U)
#define HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_WR(v)     (HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT.U = (v))
#define HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_SET(v)    (HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_WR(HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_CLR(v)    (HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_WR(HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_TOG(v)    (HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_WR(HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: mlb, In Pin: mlb_sig_in
 *
 * Values:
 * - ENET_RX_DATA1_ALT0 = 0 - Selecting ALT0 mode of pad ENET_RXD1 for MLB_SIG.
 * - GPIO06_ALT7 = 1 - Selecting ALT7 mode of pad GPIO_6 for MLB_SIG.
 */
//@{
#define BP_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY.
#define BM_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY) >> BP_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY.
#define BF_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY) & BM_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_WR((HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_RD() & ~BM_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY) | BF_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY(BV_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY__ENET_RX_DATA1_ALT0 (0x0) //!< Selecting ALT0 mode of pad ENET_RXD1 for MLB_SIG.
#define BV_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY__GPIO06_ALT7 (0x1) //!< Selecting ALT7 mode of pad GPIO_6 for MLB_SIG.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sdma_events14_select_input
{
    reg32_t U;
    struct _hw_iomuxc_sdma_events14_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_sdma_events14_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SDMA_EVENTS14_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x90c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT           (*(volatile hw_iomuxc_sdma_events14_select_input_t *) HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_ADDR)
#define HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_RD()      (HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT.U)
#define HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_WR(v)     (HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT.U = (v))
#define HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_SET(v)    (HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_WR(HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_CLR(v)    (HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_WR(HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_TOG(v)    (HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_WR(HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SDMA_EVENTS14_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_SDMA_EVENTS14_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: sdma, In Pin: events[14]
 *
 * Values:
 * - DISP0_DATA16_ALT4 = 0 - Selecting ALT4 mode of pad DISP0_DAT16 for SDMA_EXT_EVENT0.
 * - GPIO17_ALT3 = 1 - Selecting ALT3 mode of pad GPIO_17 for SDMA_EXT_EVENT0.
 */
//@{
#define BP_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY.
#define BM_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY) >> BP_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY.
#define BF_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY) & BM_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_WR((HW_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_RD() & ~BM_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY) | BF_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY(BV_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY__DISP0_DATA16_ALT4 (0x0) //!< Selecting ALT4 mode of pad DISP0_DAT16 for SDMA_EXT_EVENT0.
#define BV_IOMUXC_SDMA_EVENTS14_SELECT_INPUT_DAISY__GPIO17_ALT3 (0x1) //!< Selecting ALT3 mode of pad GPIO_17 for SDMA_EXT_EVENT0.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_sdma_events15_select_input
{
    reg32_t U;
    struct _hw_iomuxc_sdma_events15_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_sdma_events15_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SDMA_EVENTS15_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x910)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT           (*(volatile hw_iomuxc_sdma_events15_select_input_t *) HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_ADDR)
#define HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_RD()      (HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT.U)
#define HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_WR(v)     (HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT.U = (v))
#define HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_SET(v)    (HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_WR(HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_CLR(v)    (HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_WR(HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_TOG(v)    (HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_WR(HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SDMA_EVENTS15_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_SDMA_EVENTS15_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: sdma, In Pin: events[15]
 *
 * Values:
 * - DISP0_DATA17_ALT4 = 0 - Selecting ALT4 mode of pad DISP0_DAT17 for SDMA_EXT_EVENT1.
 * - GPIO18_ALT3 = 1 - Selecting ALT3 mode of pad GPIO_18 for SDMA_EXT_EVENT1.
 */
//@{
#define BP_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY.
#define BM_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY) >> BP_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY.
#define BF_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY) & BM_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_WR((HW_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_RD() & ~BM_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY) | BF_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY(BV_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY__DISP0_DATA17_ALT4 (0x0) //!< Selecting ALT4 mode of pad DISP0_DAT17 for SDMA_EXT_EVENT1.
#define BV_IOMUXC_SDMA_EVENTS15_SELECT_INPUT_DAISY__GPIO18_ALT3 (0x1) //!< Selecting ALT3 mode of pad GPIO_18 for SDMA_EXT_EVENT1.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_spdif_spdif_in1_select_input
{
    reg32_t U;
    struct _hw_iomuxc_spdif_spdif_in1_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_spdif_spdif_in1_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x914)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT           (*(volatile hw_iomuxc_spdif_spdif_in1_select_input_t *) HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_ADDR)
#define HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_RD()      (HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT.U)
#define HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(v)     (HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT.U = (v))
#define HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_SET(v)    (HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_CLR(v)    (HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_TOG(v)    (HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: spdif, In Pin: spdif_in1
 *
 * Values:
 * - EIM_DATA21_ALT7 = 00 - Selecting ALT7 mode of pad EIM_D21 for SPDIF_IN.
 * - ENET_RX_ER_ALT3 = 01 - Selecting ALT3 mode of pad ENET_RX_ER for SPDIF_IN.
 * - KEY_COL3_ALT6 = 10 - Selecting ALT6 mode of pad KEY_COL3 for SPDIF_IN.
 * - GPIO16_ALT4 = 11 - Selecting ALT4 mode of pad GPIO_16 for SPDIF_IN.
 */
//@{
#define BP_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY.
#define BM_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY) >> BP_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY.
#define BF_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY) & BM_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR((HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_RD() & ~BM_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY) | BF_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY(BV_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY__EIM_DATA21_ALT7 (0x0) //!< Selecting ALT7 mode of pad EIM_D21 for SPDIF_IN.
#define BV_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY__ENET_RX_ER_ALT3 (0x1) //!< Selecting ALT3 mode of pad ENET_RX_ER for SPDIF_IN.
#define BV_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY__KEY_COL3_ALT6 (0x2) //!< Selecting ALT6 mode of pad KEY_COL3 for SPDIF_IN.
#define BV_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY__GPIO16_ALT4 (0x3) //!< Selecting ALT4 mode of pad GPIO_16 for SPDIF_IN.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_spdif_tx_clk2_select_input
{
    reg32_t U;
    struct _hw_iomuxc_spdif_tx_clk2_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_spdif_tx_clk2_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x918)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT           (*(volatile hw_iomuxc_spdif_tx_clk2_select_input_t *) HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_ADDR)
#define HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_RD()      (HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT.U)
#define HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_WR(v)     (HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT.U = (v))
#define HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_SET(v)    (HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_WR(HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_CLR(v)    (HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_WR(HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_TOG(v)    (HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_WR(HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: spdif, In Pin: tx_clk2
 *
 * Values:
 * - RGMII_TXC_ALT2 = 0 - Selecting ALT2 mode of pad RGMII_TXC for SPDIF_EXT_CLK.
 * - ENET_CRS_DV_ALT3 = 1 - Selecting ALT3 mode of pad ENET_CRS_DV for SPDIF_EXT_CLK.
 */
//@{
#define BP_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY.
#define BM_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY) >> BP_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY.
#define BF_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY) & BM_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_WR((HW_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_RD() & ~BM_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY) | BF_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY(BV_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY__RGMII_TXC_ALT2 (0x0) //!< Selecting ALT2 mode of pad RGMII_TXC for SPDIF_EXT_CLK.
#define BV_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY__ENET_CRS_DV_ALT3 (0x1) //!< Selecting ALT3 mode of pad ENET_CRS_DV for SPDIF_EXT_CLK.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart1_uart_rts_b_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart1_uart_rts_b_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_uart1_uart_rts_b_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART1_UART_RTS_B_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x91c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT           (*(volatile hw_iomuxc_uart1_uart_rts_b_select_input_t *) HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_RD()      (HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT.U)
#define HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART1_UART_RTS_B_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart1, In Pin: ipp_uart_rts_b Connect RTS_B pad
 * to ipp_uart_rts_b when UART is in DCE mode. Connect CTS_B pad to ipp_uart_rts_b when UART is in
 * DTE mode.
 *
 * Values:
 * - EIM_DATA19_ALT4 = 00 - Selecting ALT4 mode of pad EIM_D19 for UART1_CTS_B.
 * - EIM_DATA20_ALT4 = 01 - Selecting ALT4 mode of pad EIM_D20 for UART1_RTS_B.
 * - SD3_DATA0_ALT1 = 10 - Selecting ALT1 mode of pad SD3_DAT0 for UART1_CTS_B.
 * - SD3_DATA1_ALT1 = 11 - Selecting ALT1 mode of pad SD3_DAT1 for UART1_RTS_B.
 */
//@{
#define BP_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY) & BM_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_WR((HW_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_RD() & ~BM_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY) | BF_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY(BV_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY__EIM_DATA19_ALT4 (0x0) //!< Selecting ALT4 mode of pad EIM_D19 for UART1_CTS_B.
#define BV_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY__EIM_DATA20_ALT4 (0x1) //!< Selecting ALT4 mode of pad EIM_D20 for UART1_RTS_B.
#define BV_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY__SD3_DATA0_ALT1 (0x2) //!< Selecting ALT1 mode of pad SD3_DAT0 for UART1_CTS_B.
#define BV_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT_DAISY__SD3_DATA1_ALT1 (0x3) //!< Selecting ALT1 mode of pad SD3_DAT1 for UART1_RTS_B.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart1_uart_rx_data_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart1_uart_rx_data_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_uart1_uart_rx_data_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x920)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT           (*(volatile hw_iomuxc_uart1_uart_rx_data_select_input_t *) HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_RD()      (HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT.U)
#define HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart1, In Pin: ipp_uart_rxd_mux Connect RX_DATA
 * pad to ipp_uart_rxd_mux when UART is in DCE mode. Connect TX_DATA pad to ipp_uart_rxd_mux when
 * UART is in DTE mode.
 *
 * Values:
 * - CSI0_DATA10_ALT3 = 00 - Selecting ALT3 mode of pad CSI0_DAT10 for UART1_TX_DATA.
 * - CSI0_DATA11_ALT3 = 01 - Selecting ALT3 mode of pad CSI0_DAT11 for UART1_RX_DATA.
 * - SD3_DATA7_ALT1 = 10 - Selecting ALT1 mode of pad SD3_DAT7 for UART1_TX_DATA.
 * - SD3_DATA6_ALT1 = 11 - Selecting ALT1 mode of pad SD3_DAT6 for UART1_RX_DATA.
 */
//@{
#define BP_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY) & BM_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_WR((HW_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_RD() & ~BM_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY) | BF_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY(BV_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY__CSI0_DATA10_ALT3 (0x0) //!< Selecting ALT3 mode of pad CSI0_DAT10 for UART1_TX_DATA.
#define BV_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY__CSI0_DATA11_ALT3 (0x1) //!< Selecting ALT3 mode of pad CSI0_DAT11 for UART1_RX_DATA.
#define BV_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY__SD3_DATA7_ALT1 (0x2) //!< Selecting ALT1 mode of pad SD3_DAT7 for UART1_TX_DATA.
#define BV_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT_DAISY__SD3_DATA6_ALT1 (0x3) //!< Selecting ALT1 mode of pad SD3_DAT6 for UART1_RX_DATA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart2_uart_rts_b_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart2_uart_rts_b_select_input_bitfields
    {
        unsigned DAISY : 3; //!< [2:0] MUX Mode Select Field
        unsigned RESERVED0 : 29; //!< [31:3] Reserved
    } B;
} hw_iomuxc_uart2_uart_rts_b_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART2_UART_RTS_B_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x924)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT           (*(volatile hw_iomuxc_uart2_uart_rts_b_select_input_t *) HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_RD()      (HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT.U)
#define HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART2_UART_RTS_B_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART2_UART_RTS_B_SELECT_INPUT, field DAISY[2:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart2, In Pin: ipp_uart_rts_b Connect RTS_B pad
 * to ipp_uart_rts_b when UART is in DCE mode. Connect CTS_B pad to ipp_uart_rts_b when UART is in
 * DTE mode.
 *
 * Values:
 * - EIM_DATA28_ALT4 = 000 - Selecting ALT4 mode of pad EIM_D28 for UART2_CTS_B.
 * - EIM_DATA29_ALT4 = 001 - Selecting ALT4 mode of pad EIM_D29 for UART2_RTS_B.
 * - SD3_CMD_ALT1 = 010 - Selecting ALT1 mode of pad SD3_CMD for UART2_CTS_B.
 * - SD3_CLK_ALT1 = 011 - Selecting ALT1 mode of pad SD3_CLK for UART2_RTS_B.
 * - SD4_DATA5_ALT2 = 100 - Selecting ALT2 mode of pad SD4_DAT5 for UART2_RTS_B.
 * - SD4_DATA6_ALT2 = 101 - Selecting ALT2 mode of pad SD4_DAT6 for UART2_CTS_B.
 */
//@{
#define BP_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY      (0x00000007)  //!< Bit mask for IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY) & BM_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_WR((HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_RD() & ~BM_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY) | BF_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY(BV_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY__EIM_DATA28_ALT4 (0x0) //!< Selecting ALT4 mode of pad EIM_D28 for UART2_CTS_B.
#define BV_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY__EIM_DATA29_ALT4 (0x1) //!< Selecting ALT4 mode of pad EIM_D29 for UART2_RTS_B.
#define BV_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY__SD3_CMD_ALT1 (0x2) //!< Selecting ALT1 mode of pad SD3_CMD for UART2_CTS_B.
#define BV_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY__SD3_CLK_ALT1 (0x3) //!< Selecting ALT1 mode of pad SD3_CLK for UART2_RTS_B.
#define BV_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY__SD4_DATA5_ALT2 (0x4) //!< Selecting ALT2 mode of pad SD4_DAT5 for UART2_RTS_B.
#define BV_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY__SD4_DATA6_ALT2 (0x5) //!< Selecting ALT2 mode of pad SD4_DAT6 for UART2_CTS_B.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart2_uart_rx_data_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart2_uart_rx_data_select_input_bitfields
    {
        unsigned DAISY : 3; //!< [2:0] MUX Mode Select Field
        unsigned RESERVED0 : 29; //!< [31:3] Reserved
    } B;
} hw_iomuxc_uart2_uart_rx_data_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x928)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT           (*(volatile hw_iomuxc_uart2_uart_rx_data_select_input_t *) HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_RD()      (HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT.U)
#define HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT, field DAISY[2:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart2, In Pin: ipp_uart_rxd_mux Connect RX_DATA
 * pad to ipp_uart_rxd_mux when UART is in DCE mode. Connect TX_DATA pad to ipp_uart_rxd_mux when
 * UART is in DTE mode.
 *
 * Values:
 * - EIM_DATA26_ALT4 = 000 - Selecting ALT4 mode of pad EIM_D26 for UART2_TX_DATA.
 * - EIM_DATA27_ALT4 = 001 - Selecting ALT4 mode of pad EIM_D27 for UART2_RX_DATA.
 * - GPIO07_ALT4 = 010 - Selecting ALT4 mode of pad GPIO_7 for UART2_TX_DATA.
 * - GPIO08_ALT4 = 011 - Selecting ALT4 mode of pad GPIO_8 for UART2_RX_DATA.
 * - SD3_DATA5_ALT1 = 100 - Selecting ALT1 mode of pad SD3_DAT5 for UART2_TX_DATA.
 * - SD3_DATA4_ALT1 = 101 - Selecting ALT1 mode of pad SD3_DAT4 for UART2_RX_DATA.
 * - SD4_DATA4_ALT2 = 110 - Selecting ALT2 mode of pad SD4_DAT4 for UART2_RX_DATA.
 * - SD4_DATA7_ALT2 = 111 - Selecting ALT2 mode of pad SD4_DAT7 for UART2_TX_DATA.
 */
//@{
#define BP_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY      (0x00000007)  //!< Bit mask for IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY) & BM_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_WR((HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_RD() & ~BM_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY) | BF_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY(BV_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY__EIM_DATA26_ALT4 (0x0) //!< Selecting ALT4 mode of pad EIM_D26 for UART2_TX_DATA.
#define BV_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY__EIM_DATA27_ALT4 (0x1) //!< Selecting ALT4 mode of pad EIM_D27 for UART2_RX_DATA.
#define BV_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY__GPIO07_ALT4 (0x2) //!< Selecting ALT4 mode of pad GPIO_7 for UART2_TX_DATA.
#define BV_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY__GPIO08_ALT4 (0x3) //!< Selecting ALT4 mode of pad GPIO_8 for UART2_RX_DATA.
#define BV_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY__SD3_DATA5_ALT1 (0x4) //!< Selecting ALT1 mode of pad SD3_DAT5 for UART2_TX_DATA.
#define BV_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY__SD3_DATA4_ALT1 (0x5) //!< Selecting ALT1 mode of pad SD3_DAT4 for UART2_RX_DATA.
#define BV_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY__SD4_DATA4_ALT2 (0x6) //!< Selecting ALT2 mode of pad SD4_DAT4 for UART2_RX_DATA.
#define BV_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY__SD4_DATA7_ALT2 (0x7) //!< Selecting ALT2 mode of pad SD4_DAT7 for UART2_TX_DATA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart3_uart_rts_b_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart3_uart_rts_b_select_input_bitfields
    {
        unsigned DAISY : 3; //!< [2:0] MUX Mode Select Field
        unsigned RESERVED0 : 29; //!< [31:3] Reserved
    } B;
} hw_iomuxc_uart3_uart_rts_b_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART3_UART_RTS_B_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x92c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT           (*(volatile hw_iomuxc_uart3_uart_rts_b_select_input_t *) HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_RD()      (HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT.U)
#define HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART3_UART_RTS_B_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART3_UART_RTS_B_SELECT_INPUT, field DAISY[2:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart3, In Pin: ipp_uart_rts_b Connect RTS_B pad
 * to ipp_uart_rts_b when UART is in DCE mode. Connect CTS_B pad to ipp_uart_rts_b when UART is in
 * DTE mode.
 *
 * Values:
 * - EIM_DATA23_ALT2 = 000 - Selecting ALT2 mode of pad EIM_D23 for UART3_CTS_B.
 * - EIM_EB3_ALT2 = 001 - Selecting ALT2 mode of pad EIM_EB3 for UART3_RTS_B.
 * - EIM_DATA30_ALT4 = 010 - Selecting ALT4 mode of pad EIM_D30 for UART3_CTS_B.
 * - EIM_DATA31_ALT4 = 011 - Selecting ALT4 mode of pad EIM_D31 for UART3_RTS_B.
 * - SD3_DATA3_ALT1 = 100 - Selecting ALT1 mode of pad SD3_DAT3 for UART3_CTS_B.
 * - SD3_RESET_ALT1 = 101 - Selecting ALT1 mode of pad SD3_RST for UART3_RTS_B.
 */
//@{
#define BP_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY      (0x00000007)  //!< Bit mask for IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY) & BM_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_WR((HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_RD() & ~BM_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY) | BF_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY(BV_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY__EIM_DATA23_ALT2 (0x0) //!< Selecting ALT2 mode of pad EIM_D23 for UART3_CTS_B.
#define BV_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY__EIM_EB3_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_EB3 for UART3_RTS_B.
#define BV_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY__EIM_DATA30_ALT4 (0x2) //!< Selecting ALT4 mode of pad EIM_D30 for UART3_CTS_B.
#define BV_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY__EIM_DATA31_ALT4 (0x3) //!< Selecting ALT4 mode of pad EIM_D31 for UART3_RTS_B.
#define BV_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY__SD3_DATA3_ALT1 (0x4) //!< Selecting ALT1 mode of pad SD3_DAT3 for UART3_CTS_B.
#define BV_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY__SD3_RESET_ALT1 (0x5) //!< Selecting ALT1 mode of pad SD3_RST for UART3_RTS_B.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart3_uart_rx_data_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart3_uart_rx_data_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_uart3_uart_rx_data_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x930)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT           (*(volatile hw_iomuxc_uart3_uart_rx_data_select_input_t *) HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_RD()      (HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT.U)
#define HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart3, In Pin: ipp_uart_rxd_mux Connect RX_DATA
 * pad to ipp_uart_rxd_mux when UART is in DCE mode. Connect TX_DATA pad to ipp_uart_rxd_mux when
 * UART is in DTE mode.
 *
 * Values:
 * - EIM_DATA24_ALT2 = 00 - Selecting ALT2 mode of pad EIM_D24 for UART3_TX_DATA.
 * - EIM_DATA25_ALT2 = 01 - Selecting ALT2 mode of pad EIM_D25 for UART3_RX_DATA.
 * - SD4_CMD_ALT2 = 10 - Selecting ALT2 mode of pad SD4_CMD for UART3_TX_DATA.
 * - SD4_CLK_ALT2 = 11 - Selecting ALT2 mode of pad SD4_CLK for UART3_RX_DATA.
 */
//@{
#define BP_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY) & BM_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_WR((HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_RD() & ~BM_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY) | BF_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY(BV_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY__EIM_DATA24_ALT2 (0x0) //!< Selecting ALT2 mode of pad EIM_D24 for UART3_TX_DATA.
#define BV_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY__EIM_DATA25_ALT2 (0x1) //!< Selecting ALT2 mode of pad EIM_D25 for UART3_RX_DATA.
#define BV_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY__SD4_CMD_ALT2 (0x2) //!< Selecting ALT2 mode of pad SD4_CMD for UART3_TX_DATA.
#define BV_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY__SD4_CLK_ALT2 (0x3) //!< Selecting ALT2 mode of pad SD4_CLK for UART3_RX_DATA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart4_uart_rts_b_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart4_uart_rts_b_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_uart4_uart_rts_b_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART4_UART_RTS_B_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x934)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT           (*(volatile hw_iomuxc_uart4_uart_rts_b_select_input_t *) HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_RD()      (HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT.U)
#define HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART4_UART_RTS_B_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART4_UART_RTS_B_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart4, In Pin: ipp_uart_rts_b Connect RTS_B pad
 * to ipp_uart_rts_b when UART is in DCE mode. Connect CTS_B pad to ipp_uart_rts_b when UART is in
 * DTE mode.
 *
 * Values:
 * - CSI0_DATA16_ALT3 = 0 - Selecting ALT3 mode of pad CSI0_DAT16 for UART4_RTS_B.
 * - CSI0_DATA17_ALT3 = 1 - Selecting ALT3 mode of pad CSI0_DAT17 for UART4_CTS_B.
 */
//@{
#define BP_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY) & BM_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_WR((HW_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_RD() & ~BM_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY) | BF_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY(BV_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY__CSI0_DATA16_ALT3 (0x0) //!< Selecting ALT3 mode of pad CSI0_DAT16 for UART4_RTS_B.
#define BV_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT_DAISY__CSI0_DATA17_ALT3 (0x1) //!< Selecting ALT3 mode of pad CSI0_DAT17 for UART4_CTS_B.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart4_uart_rx_data_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart4_uart_rx_data_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_uart4_uart_rx_data_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x938)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT           (*(volatile hw_iomuxc_uart4_uart_rx_data_select_input_t *) HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_RD()      (HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT.U)
#define HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart4, In Pin: ipp_uart_rxd_mux Connect RX_DATA
 * pad to ipp_uart_rxd_mux when UART is in DCE mode. Connect TX_DATA pad to ipp_uart_rxd_mux when
 * UART is in DTE mode.
 *
 * Values:
 * - KEY_COL0_ALT4 = 00 - Selecting ALT4 mode of pad KEY_COL0 for UART4_TX_DATA.
 * - KEY_ROW0_ALT4 = 01 - Selecting ALT4 mode of pad KEY_ROW0 for UART4_RX_DATA.
 * - CSI0_DATA12_ALT3 = 10 - Selecting ALT3 mode of pad CSI0_DAT12 for UART4_TX_DATA.
 * - CSI0_DATA13_ALT3 = 11 - Selecting ALT3 mode of pad CSI0_DAT13 for UART4_RX_DATA.
 */
//@{
#define BP_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY) & BM_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR((HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_RD() & ~BM_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY) | BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY(BV_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY__KEY_COL0_ALT4 (0x0) //!< Selecting ALT4 mode of pad KEY_COL0 for UART4_TX_DATA.
#define BV_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY__KEY_ROW0_ALT4 (0x1) //!< Selecting ALT4 mode of pad KEY_ROW0 for UART4_RX_DATA.
#define BV_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY__CSI0_DATA12_ALT3 (0x2) //!< Selecting ALT3 mode of pad CSI0_DAT12 for UART4_TX_DATA.
#define BV_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY__CSI0_DATA13_ALT3 (0x3) //!< Selecting ALT3 mode of pad CSI0_DAT13 for UART4_RX_DATA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart5_uart_rts_b_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart5_uart_rts_b_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_uart5_uart_rts_b_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART5_UART_RTS_B_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x93c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT           (*(volatile hw_iomuxc_uart5_uart_rts_b_select_input_t *) HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_RD()      (HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT.U)
#define HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_WR(HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART5_UART_RTS_B_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART5_UART_RTS_B_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart5, In Pin: ipp_uart_rts_b Connect RTS_B pad
 * to ipp_uart_rts_b when UART is in DCE mode. Connect CTS_B pad to ipp_uart_rts_b when UART is in
 * DTE mode.
 *
 * Values:
 * - KEY_COL4_ALT4 = 00 - Selecting ALT4 mode of pad KEY_COL4 for UART5_RTS_B.
 * - KEY_ROW4_ALT4 = 01 - Selecting ALT4 mode of pad KEY_ROW4 for UART5_CTS_B.
 * - CSI0_DATA18_ALT3 = 10 - Selecting ALT3 mode of pad CSI0_DAT18 for UART5_RTS_B.
 * - CSI0_DATA19_ALT3 = 11 - Selecting ALT3 mode of pad CSI0_DAT19 for UART5_CTS_B.
 */
//@{
#define BP_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY) & BM_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_WR((HW_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_RD() & ~BM_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY) | BF_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY(BV_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY__KEY_COL4_ALT4 (0x0) //!< Selecting ALT4 mode of pad KEY_COL4 for UART5_RTS_B.
#define BV_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY__KEY_ROW4_ALT4 (0x1) //!< Selecting ALT4 mode of pad KEY_ROW4 for UART5_CTS_B.
#define BV_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY__CSI0_DATA18_ALT3 (0x2) //!< Selecting ALT3 mode of pad CSI0_DAT18 for UART5_RTS_B.
#define BV_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT_DAISY__CSI0_DATA19_ALT3 (0x3) //!< Selecting ALT3 mode of pad CSI0_DAT19 for UART5_CTS_B.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_uart5_uart_rx_data_select_input
{
    reg32_t U;
    struct _hw_iomuxc_uart5_uart_rx_data_select_input_bitfields
    {
        unsigned DAISY : 2; //!< [1:0] MUX Mode Select Field
        unsigned RESERVED0 : 30; //!< [31:2] Reserved
    } B;
} hw_iomuxc_uart5_uart_rx_data_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x940)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT           (*(volatile hw_iomuxc_uart5_uart_rx_data_select_input_t *) HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_ADDR)
#define HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_RD()      (HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT.U)
#define HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_WR(v)     (HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT.U = (v))
#define HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_SET(v)    (HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_CLR(v)    (HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_TOG(v)    (HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_WR(HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT, field DAISY[1:0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: uart5, In Pin: ipp_uart_rxd_mux Connect RX_DATA
 * pad to ipp_uart_rxd_mux when UART is in DCE mode. Connect TX_DATA pad to ipp_uart_rxd_mux when
 * UART is in DTE mode.
 *
 * Values:
 * - KEY_COL1_ALT4 = 00 - Selecting ALT4 mode of pad KEY_COL1 for UART5_TX_DATA.
 * - KEY_ROW1_ALT4 = 01 - Selecting ALT4 mode of pad KEY_ROW1 for UART5_RX_DATA.
 * - CSI0_DATA14_ALT3 = 10 - Selecting ALT3 mode of pad CSI0_DAT14 for UART5_TX_DATA.
 * - CSI0_DATA15_ALT3 = 11 - Selecting ALT3 mode of pad CSI0_DAT15 for UART5_RX_DATA.
 */
//@{
#define BP_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BM_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY      (0x00000003)  //!< Bit mask for IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY) >> BP_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY.
#define BF_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY) & BM_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_WR((HW_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_RD() & ~BM_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY) | BF_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY(BV_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY__KEY_COL1_ALT4 (0x0) //!< Selecting ALT4 mode of pad KEY_COL1 for UART5_TX_DATA.
#define BV_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY__KEY_ROW1_ALT4 (0x1) //!< Selecting ALT4 mode of pad KEY_ROW1 for UART5_RX_DATA.
#define BV_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY__CSI0_DATA14_ALT3 (0x2) //!< Selecting ALT3 mode of pad CSI0_DAT14 for UART5_TX_DATA.
#define BV_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT_DAISY__CSI0_DATA15_ALT3 (0x3) //!< Selecting ALT3 mode of pad CSI0_DAT15 for UART5_RX_DATA.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_USB_OTG_OC_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_USB_OTG_OC_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_usb_otg_oc_select_input
{
    reg32_t U;
    struct _hw_iomuxc_usb_otg_oc_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_usb_otg_oc_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_USB_OTG_OC_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x944)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_USB_OTG_OC_SELECT_INPUT           (*(volatile hw_iomuxc_usb_otg_oc_select_input_t *) HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_ADDR)
#define HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_RD()      (HW_IOMUXC_USB_OTG_OC_SELECT_INPUT.U)
#define HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_WR(v)     (HW_IOMUXC_USB_OTG_OC_SELECT_INPUT.U = (v))
#define HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_SET(v)    (HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_WR(HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_CLR(v)    (HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_WR(HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_TOG(v)    (HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_WR(HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_USB_OTG_OC_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_USB_OTG_OC_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: usb, In Pin: ipp_ind_otg_oc
 *
 * Values:
 * - EIM_DATA21_ALT4 = 0 - Selecting ALT4 mode of pad EIM_D21 for USB_OTG_OC.
 * - KEY_COL4_ALT2 = 1 - Selecting ALT2 mode of pad KEY_COL4 for USB_OTG_OC.
 */
//@{
#define BP_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY.
#define BM_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY) >> BP_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY.
#define BF_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY) & BM_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_WR((HW_IOMUXC_USB_OTG_OC_SELECT_INPUT_RD() & ~BM_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY) | BF_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY(BV_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY__EIM_DATA21_ALT4 (0x0) //!< Selecting ALT4 mode of pad EIM_D21 for USB_OTG_OC.
#define BV_IOMUXC_USB_OTG_OC_SELECT_INPUT_DAISY__KEY_COL4_ALT2 (0x1) //!< Selecting ALT2 mode of pad KEY_COL4 for USB_OTG_OC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_USB_H1_OC_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_USB_H1_OC_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_usb_h1_oc_select_input
{
    reg32_t U;
    struct _hw_iomuxc_usb_h1_oc_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_usb_h1_oc_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_USB_H1_OC_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_USB_H1_OC_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x948)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_USB_H1_OC_SELECT_INPUT           (*(volatile hw_iomuxc_usb_h1_oc_select_input_t *) HW_IOMUXC_USB_H1_OC_SELECT_INPUT_ADDR)
#define HW_IOMUXC_USB_H1_OC_SELECT_INPUT_RD()      (HW_IOMUXC_USB_H1_OC_SELECT_INPUT.U)
#define HW_IOMUXC_USB_H1_OC_SELECT_INPUT_WR(v)     (HW_IOMUXC_USB_H1_OC_SELECT_INPUT.U = (v))
#define HW_IOMUXC_USB_H1_OC_SELECT_INPUT_SET(v)    (HW_IOMUXC_USB_H1_OC_SELECT_INPUT_WR(HW_IOMUXC_USB_H1_OC_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_USB_H1_OC_SELECT_INPUT_CLR(v)    (HW_IOMUXC_USB_H1_OC_SELECT_INPUT_WR(HW_IOMUXC_USB_H1_OC_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_USB_H1_OC_SELECT_INPUT_TOG(v)    (HW_IOMUXC_USB_H1_OC_SELECT_INPUT_WR(HW_IOMUXC_USB_H1_OC_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_USB_H1_OC_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_USB_H1_OC_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: usb, In Pin: ipp_ind_uh1_oc
 *
 * Values:
 * - EIM_DATA30_ALT6 = 0 - Selecting ALT6 mode of pad EIM_D30 for USB_H1_OC.
 * - GPIO03_ALT6 = 1 - Selecting ALT6 mode of pad GPIO_3 for USB_H1_OC.
 */
//@{
#define BP_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY.
#define BM_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY) >> BP_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY.
#define BF_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY) & BM_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_USB_H1_OC_SELECT_INPUT_WR((HW_IOMUXC_USB_H1_OC_SELECT_INPUT_RD() & ~BM_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY) | BF_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY(BV_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY__EIM_DATA30_ALT6 (0x0) //!< Selecting ALT6 mode of pad EIM_D30 for USB_H1_OC.
#define BV_IOMUXC_USB_H1_OC_SELECT_INPUT_DAISY__GPIO03_ALT6 (0x1) //!< Selecting ALT6 mode of pad GPIO_3 for USB_H1_OC.
//@}

//-------------------------------------------------------------------------------------------
// HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT - Select Input Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT - Select Input Register (RW)
 *
 * Reset value: 0x00000000
 */
typedef union _hw_iomuxc_usdhc1_wp_on_select_input
{
    reg32_t U;
    struct _hw_iomuxc_usdhc1_wp_on_select_input_bitfields
    {
        unsigned DAISY : 1; //!< [0] MUX Mode Select Field
        unsigned RESERVED0 : 31; //!< [31:1] Reserved
    } B;
} hw_iomuxc_usdhc1_wp_on_select_input_t;
#endif

/*!
 * @name Constants and macros for entire IOMUXC_USDHC1_WP_ON_SELECT_INPUT register
 */
//@{
#define HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_ADDR      (REGS_IOMUXC_BASE + 0x94c)

#ifndef __LANGUAGE_ASM__
#define HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT           (*(volatile hw_iomuxc_usdhc1_wp_on_select_input_t *) HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_ADDR)
#define HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_RD()      (HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT.U)
#define HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_WR(v)     (HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT.U = (v))
#define HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_SET(v)    (HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_WR(HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_RD() |  (v)))
#define HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_CLR(v)    (HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_WR(HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_RD() & ~(v)))
#define HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_TOG(v)    (HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_WR(HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_RD() ^  (v)))
#endif
//@}

/*
 * constants & macros for individual IOMUXC_USDHC1_WP_ON_SELECT_INPUT bitfields
 */

/*! @name Register IOMUXC_USDHC1_WP_ON_SELECT_INPUT, field DAISY[0] (RW)
 *
 * Selecting Pads Involved in Daisy Chain. Instance: usdhc1, In Pin: ipp_wp_on
 *
 * Values:
 * - DI0_PIN04_ALT3 = 0 - Selecting ALT3 mode of pad DI0_PIN4 for SD1_WP.
 * - GPIO09_ALT6 = 1 - Selecting ALT6 mode of pad GPIO_9 for SD1_WP.
 */
//@{
#define BP_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY      (0)      //!< Bit position for IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY.
#define BM_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY      (0x00000001)  //!< Bit mask for IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY.

//! @brief Get value of IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY from a register value.
#define BG_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY) >> BP_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY)

//! @brief Format value for bitfield IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY.
#define BF_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY) & BM_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DAISY field to a new value.
#define BW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY(v)   (HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_WR((HW_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_RD() & ~BM_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY) | BF_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY(v)))
#endif

//! @brief Macro to simplify usage of value macros.
#define BF_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY_V(v) BF_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY(BV_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY__##v)

#define BV_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY__DI0_PIN04_ALT3 (0x0) //!< Selecting ALT3 mode of pad DI0_PIN4 for SD1_WP.
#define BV_IOMUXC_USDHC1_WP_ON_SELECT_INPUT_DAISY__GPIO09_ALT6 (0x1) //!< Selecting ALT6 mode of pad GPIO_9 for SD1_WP.
//@}

//-------------------------------------------------------------------------------------------
// hw_iomuxc_t - module struct
//-------------------------------------------------------------------------------------------
/*!
 * @brief All IOMUXC module registers.
 */
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_iomuxc
{
    volatile hw_iomuxc_gpr0_t GPR0; //!< GPR
    volatile hw_iomuxc_gpr1_t GPR1; //!< GPR
    volatile hw_iomuxc_gpr2_t GPR2; //!< GPR
    volatile hw_iomuxc_gpr3_t GPR3; //!< GPR
    volatile hw_iomuxc_gpr4_t GPR4; //!< GPR
    volatile hw_iomuxc_gpr5_t GPR5; //!< GPR
    volatile hw_iomuxc_gpr6_t GPR6; //!< GPR
    volatile hw_iomuxc_gpr7_t GPR7; //!< GPR
    volatile hw_iomuxc_gpr8_t GPR8; //!< GPR
    volatile hw_iomuxc_gpr9_t GPR9; //!< GPR
    volatile hw_iomuxc_gpr10_t GPR10; //!< GPR
    volatile hw_iomuxc_gpr11_t GPR11; //!< GPR
    volatile hw_iomuxc_gpr12_t GPR12; //!< GPR
    volatile hw_iomuxc_gpr13_t GPR13; //!< GPR
    reg32_t _reserved0[5];
    volatile hw_iomuxc_sw_mux_ctl_pad_sd2_data1_t SW_MUX_CTL_PAD_SD2_DATA1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd2_data2_t SW_MUX_CTL_PAD_SD2_DATA2; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd2_data0_t SW_MUX_CTL_PAD_SD2_DATA0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_txc_t SW_MUX_CTL_PAD_RGMII_TXC; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_td0_t SW_MUX_CTL_PAD_RGMII_TD0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_td1_t SW_MUX_CTL_PAD_RGMII_TD1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_td2_t SW_MUX_CTL_PAD_RGMII_TD2; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_td3_t SW_MUX_CTL_PAD_RGMII_TD3; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rx_ctl_t SW_MUX_CTL_PAD_RGMII_RX_CTL; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rd0_t SW_MUX_CTL_PAD_RGMII_RD0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_tx_ctl_t SW_MUX_CTL_PAD_RGMII_TX_CTL; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rd1_t SW_MUX_CTL_PAD_RGMII_RD1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rd2_t SW_MUX_CTL_PAD_RGMII_RD2; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rd3_t SW_MUX_CTL_PAD_RGMII_RD3; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_rgmii_rxc_t SW_MUX_CTL_PAD_RGMII_RXC; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr25_t SW_MUX_CTL_PAD_EIM_ADDR25; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_eb2_t SW_MUX_CTL_PAD_EIM_EB2; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data16_t SW_MUX_CTL_PAD_EIM_DATA16; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data17_t SW_MUX_CTL_PAD_EIM_DATA17; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data18_t SW_MUX_CTL_PAD_EIM_DATA18; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data19_t SW_MUX_CTL_PAD_EIM_DATA19; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data20_t SW_MUX_CTL_PAD_EIM_DATA20; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data21_t SW_MUX_CTL_PAD_EIM_DATA21; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data22_t SW_MUX_CTL_PAD_EIM_DATA22; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data23_t SW_MUX_CTL_PAD_EIM_DATA23; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_eb3_t SW_MUX_CTL_PAD_EIM_EB3; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data24_t SW_MUX_CTL_PAD_EIM_DATA24; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data25_t SW_MUX_CTL_PAD_EIM_DATA25; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data26_t SW_MUX_CTL_PAD_EIM_DATA26; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data27_t SW_MUX_CTL_PAD_EIM_DATA27; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data28_t SW_MUX_CTL_PAD_EIM_DATA28; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data29_t SW_MUX_CTL_PAD_EIM_DATA29; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data30_t SW_MUX_CTL_PAD_EIM_DATA30; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_data31_t SW_MUX_CTL_PAD_EIM_DATA31; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr24_t SW_MUX_CTL_PAD_EIM_ADDR24; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr23_t SW_MUX_CTL_PAD_EIM_ADDR23; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr22_t SW_MUX_CTL_PAD_EIM_ADDR22; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr21_t SW_MUX_CTL_PAD_EIM_ADDR21; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr20_t SW_MUX_CTL_PAD_EIM_ADDR20; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr19_t SW_MUX_CTL_PAD_EIM_ADDR19; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr18_t SW_MUX_CTL_PAD_EIM_ADDR18; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr17_t SW_MUX_CTL_PAD_EIM_ADDR17; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_addr16_t SW_MUX_CTL_PAD_EIM_ADDR16; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_cs0_t SW_MUX_CTL_PAD_EIM_CS0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_cs1_t SW_MUX_CTL_PAD_EIM_CS1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_oe_t SW_MUX_CTL_PAD_EIM_OE; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_rw_t SW_MUX_CTL_PAD_EIM_RW; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_lba_t SW_MUX_CTL_PAD_EIM_LBA; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_eb0_t SW_MUX_CTL_PAD_EIM_EB0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_eb1_t SW_MUX_CTL_PAD_EIM_EB1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad00_t SW_MUX_CTL_PAD_EIM_AD00; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad01_t SW_MUX_CTL_PAD_EIM_AD01; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad02_t SW_MUX_CTL_PAD_EIM_AD02; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad03_t SW_MUX_CTL_PAD_EIM_AD03; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad04_t SW_MUX_CTL_PAD_EIM_AD04; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad05_t SW_MUX_CTL_PAD_EIM_AD05; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad06_t SW_MUX_CTL_PAD_EIM_AD06; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad07_t SW_MUX_CTL_PAD_EIM_AD07; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad08_t SW_MUX_CTL_PAD_EIM_AD08; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad09_t SW_MUX_CTL_PAD_EIM_AD09; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad10_t SW_MUX_CTL_PAD_EIM_AD10; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad11_t SW_MUX_CTL_PAD_EIM_AD11; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad12_t SW_MUX_CTL_PAD_EIM_AD12; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad13_t SW_MUX_CTL_PAD_EIM_AD13; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad14_t SW_MUX_CTL_PAD_EIM_AD14; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_ad15_t SW_MUX_CTL_PAD_EIM_AD15; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_wait_t SW_MUX_CTL_PAD_EIM_WAIT; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_eim_bclk_t SW_MUX_CTL_PAD_EIM_BCLK; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_di0_disp_clk_t SW_MUX_CTL_PAD_DI0_DISP_CLK; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_di0_pin15_t SW_MUX_CTL_PAD_DI0_PIN15; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_di0_pin02_t SW_MUX_CTL_PAD_DI0_PIN02; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_di0_pin03_t SW_MUX_CTL_PAD_DI0_PIN03; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_di0_pin04_t SW_MUX_CTL_PAD_DI0_PIN04; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data00_t SW_MUX_CTL_PAD_DISP0_DATA00; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data01_t SW_MUX_CTL_PAD_DISP0_DATA01; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data02_t SW_MUX_CTL_PAD_DISP0_DATA02; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data03_t SW_MUX_CTL_PAD_DISP0_DATA03; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data04_t SW_MUX_CTL_PAD_DISP0_DATA04; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data05_t SW_MUX_CTL_PAD_DISP0_DATA05; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data06_t SW_MUX_CTL_PAD_DISP0_DATA06; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data07_t SW_MUX_CTL_PAD_DISP0_DATA07; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data08_t SW_MUX_CTL_PAD_DISP0_DATA08; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data09_t SW_MUX_CTL_PAD_DISP0_DATA09; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data10_t SW_MUX_CTL_PAD_DISP0_DATA10; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data11_t SW_MUX_CTL_PAD_DISP0_DATA11; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data12_t SW_MUX_CTL_PAD_DISP0_DATA12; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data13_t SW_MUX_CTL_PAD_DISP0_DATA13; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data14_t SW_MUX_CTL_PAD_DISP0_DATA14; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data15_t SW_MUX_CTL_PAD_DISP0_DATA15; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data16_t SW_MUX_CTL_PAD_DISP0_DATA16; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data17_t SW_MUX_CTL_PAD_DISP0_DATA17; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data18_t SW_MUX_CTL_PAD_DISP0_DATA18; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data19_t SW_MUX_CTL_PAD_DISP0_DATA19; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data20_t SW_MUX_CTL_PAD_DISP0_DATA20; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data21_t SW_MUX_CTL_PAD_DISP0_DATA21; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data22_t SW_MUX_CTL_PAD_DISP0_DATA22; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_disp0_data23_t SW_MUX_CTL_PAD_DISP0_DATA23; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_mdio_t SW_MUX_CTL_PAD_ENET_MDIO; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_ref_clk_t SW_MUX_CTL_PAD_ENET_REF_CLK; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_rx_er_t SW_MUX_CTL_PAD_ENET_RX_ER; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_crs_dv_t SW_MUX_CTL_PAD_ENET_CRS_DV; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_rx_data1_t SW_MUX_CTL_PAD_ENET_RX_DATA1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_rx_data0_t SW_MUX_CTL_PAD_ENET_RX_DATA0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_tx_en_t SW_MUX_CTL_PAD_ENET_TX_EN; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_tx_data1_t SW_MUX_CTL_PAD_ENET_TX_DATA1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_tx_data0_t SW_MUX_CTL_PAD_ENET_TX_DATA0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_enet_mdc_t SW_MUX_CTL_PAD_ENET_MDC; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_col0_t SW_MUX_CTL_PAD_KEY_COL0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_row0_t SW_MUX_CTL_PAD_KEY_ROW0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_col1_t SW_MUX_CTL_PAD_KEY_COL1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_row1_t SW_MUX_CTL_PAD_KEY_ROW1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_col2_t SW_MUX_CTL_PAD_KEY_COL2; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_row2_t SW_MUX_CTL_PAD_KEY_ROW2; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_col3_t SW_MUX_CTL_PAD_KEY_COL3; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_row3_t SW_MUX_CTL_PAD_KEY_ROW3; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_col4_t SW_MUX_CTL_PAD_KEY_COL4; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_key_row4_t SW_MUX_CTL_PAD_KEY_ROW4; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio00_t SW_MUX_CTL_PAD_GPIO00; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio01_t SW_MUX_CTL_PAD_GPIO01; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio09_t SW_MUX_CTL_PAD_GPIO09; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio03_t SW_MUX_CTL_PAD_GPIO03; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio06_t SW_MUX_CTL_PAD_GPIO06; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio02_t SW_MUX_CTL_PAD_GPIO02; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio04_t SW_MUX_CTL_PAD_GPIO04; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio05_t SW_MUX_CTL_PAD_GPIO05; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio07_t SW_MUX_CTL_PAD_GPIO07; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio08_t SW_MUX_CTL_PAD_GPIO08; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio16_t SW_MUX_CTL_PAD_GPIO16; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio17_t SW_MUX_CTL_PAD_GPIO17; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio18_t SW_MUX_CTL_PAD_GPIO18; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_gpio19_t SW_MUX_CTL_PAD_GPIO19; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_pixclk_t SW_MUX_CTL_PAD_CSI0_PIXCLK; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_hsync_t SW_MUX_CTL_PAD_CSI0_HSYNC; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data_en_t SW_MUX_CTL_PAD_CSI0_DATA_EN; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_vsync_t SW_MUX_CTL_PAD_CSI0_VSYNC; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data04_t SW_MUX_CTL_PAD_CSI0_DATA04; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data05_t SW_MUX_CTL_PAD_CSI0_DATA05; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data06_t SW_MUX_CTL_PAD_CSI0_DATA06; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data07_t SW_MUX_CTL_PAD_CSI0_DATA07; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data08_t SW_MUX_CTL_PAD_CSI0_DATA08; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data09_t SW_MUX_CTL_PAD_CSI0_DATA09; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data10_t SW_MUX_CTL_PAD_CSI0_DATA10; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data11_t SW_MUX_CTL_PAD_CSI0_DATA11; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data12_t SW_MUX_CTL_PAD_CSI0_DATA12; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data13_t SW_MUX_CTL_PAD_CSI0_DATA13; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data14_t SW_MUX_CTL_PAD_CSI0_DATA14; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data15_t SW_MUX_CTL_PAD_CSI0_DATA15; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data16_t SW_MUX_CTL_PAD_CSI0_DATA16; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data17_t SW_MUX_CTL_PAD_CSI0_DATA17; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data18_t SW_MUX_CTL_PAD_CSI0_DATA18; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_csi0_data19_t SW_MUX_CTL_PAD_CSI0_DATA19; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data7_t SW_MUX_CTL_PAD_SD3_DATA7; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data6_t SW_MUX_CTL_PAD_SD3_DATA6; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data5_t SW_MUX_CTL_PAD_SD3_DATA5; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data4_t SW_MUX_CTL_PAD_SD3_DATA4; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_cmd_t SW_MUX_CTL_PAD_SD3_CMD; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_clk_t SW_MUX_CTL_PAD_SD3_CLK; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data0_t SW_MUX_CTL_PAD_SD3_DATA0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data1_t SW_MUX_CTL_PAD_SD3_DATA1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data2_t SW_MUX_CTL_PAD_SD3_DATA2; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_data3_t SW_MUX_CTL_PAD_SD3_DATA3; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd3_reset_t SW_MUX_CTL_PAD_SD3_RESET; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_cle_t SW_MUX_CTL_PAD_NAND_CLE; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_ale_t SW_MUX_CTL_PAD_NAND_ALE; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_wp_b_t SW_MUX_CTL_PAD_NAND_WP_B; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_ready_t SW_MUX_CTL_PAD_NAND_READY; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_cs0_b_t SW_MUX_CTL_PAD_NAND_CS0_B; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_cs1_b_t SW_MUX_CTL_PAD_NAND_CS1_B; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_cs2_b_t SW_MUX_CTL_PAD_NAND_CS2_B; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_cs3_b_t SW_MUX_CTL_PAD_NAND_CS3_B; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_cmd_t SW_MUX_CTL_PAD_SD4_CMD; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_clk_t SW_MUX_CTL_PAD_SD4_CLK; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_data00_t SW_MUX_CTL_PAD_NAND_DATA00; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_data01_t SW_MUX_CTL_PAD_NAND_DATA01; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_data02_t SW_MUX_CTL_PAD_NAND_DATA02; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_data03_t SW_MUX_CTL_PAD_NAND_DATA03; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_data04_t SW_MUX_CTL_PAD_NAND_DATA04; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_data05_t SW_MUX_CTL_PAD_NAND_DATA05; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_data06_t SW_MUX_CTL_PAD_NAND_DATA06; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_nand_data07_t SW_MUX_CTL_PAD_NAND_DATA07; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data0_t SW_MUX_CTL_PAD_SD4_DATA0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data1_t SW_MUX_CTL_PAD_SD4_DATA1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data2_t SW_MUX_CTL_PAD_SD4_DATA2; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data3_t SW_MUX_CTL_PAD_SD4_DATA3; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data4_t SW_MUX_CTL_PAD_SD4_DATA4; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data5_t SW_MUX_CTL_PAD_SD4_DATA5; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data6_t SW_MUX_CTL_PAD_SD4_DATA6; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd4_data7_t SW_MUX_CTL_PAD_SD4_DATA7; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd1_data1_t SW_MUX_CTL_PAD_SD1_DATA1; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd1_data0_t SW_MUX_CTL_PAD_SD1_DATA0; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd1_data3_t SW_MUX_CTL_PAD_SD1_DATA3; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd1_cmd_t SW_MUX_CTL_PAD_SD1_CMD; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd1_data2_t SW_MUX_CTL_PAD_SD1_DATA2; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd1_clk_t SW_MUX_CTL_PAD_SD1_CLK; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd2_clk_t SW_MUX_CTL_PAD_SD2_CLK; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd2_cmd_t SW_MUX_CTL_PAD_SD2_CMD; //!< Pad Mux Register
    volatile hw_iomuxc_sw_mux_ctl_pad_sd2_data3_t SW_MUX_CTL_PAD_SD2_DATA3; //!< Pad Mux Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd2_data1_t SW_PAD_CTL_PAD_SD2_DATA1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd2_data2_t SW_PAD_CTL_PAD_SD2_DATA2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd2_data0_t SW_PAD_CTL_PAD_SD2_DATA0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_txc_t SW_PAD_CTL_PAD_RGMII_TXC; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_td0_t SW_PAD_CTL_PAD_RGMII_TD0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_td1_t SW_PAD_CTL_PAD_RGMII_TD1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_td2_t SW_PAD_CTL_PAD_RGMII_TD2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_td3_t SW_PAD_CTL_PAD_RGMII_TD3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rx_ctl_t SW_PAD_CTL_PAD_RGMII_RX_CTL; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rd0_t SW_PAD_CTL_PAD_RGMII_RD0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_tx_ctl_t SW_PAD_CTL_PAD_RGMII_TX_CTL; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rd1_t SW_PAD_CTL_PAD_RGMII_RD1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rd2_t SW_PAD_CTL_PAD_RGMII_RD2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rd3_t SW_PAD_CTL_PAD_RGMII_RD3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_rgmii_rxc_t SW_PAD_CTL_PAD_RGMII_RXC; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr25_t SW_PAD_CTL_PAD_EIM_ADDR25; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_eb2_t SW_PAD_CTL_PAD_EIM_EB2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data16_t SW_PAD_CTL_PAD_EIM_DATA16; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data17_t SW_PAD_CTL_PAD_EIM_DATA17; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data18_t SW_PAD_CTL_PAD_EIM_DATA18; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data19_t SW_PAD_CTL_PAD_EIM_DATA19; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data20_t SW_PAD_CTL_PAD_EIM_DATA20; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data21_t SW_PAD_CTL_PAD_EIM_DATA21; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data22_t SW_PAD_CTL_PAD_EIM_DATA22; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data23_t SW_PAD_CTL_PAD_EIM_DATA23; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_eb3_t SW_PAD_CTL_PAD_EIM_EB3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data24_t SW_PAD_CTL_PAD_EIM_DATA24; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data25_t SW_PAD_CTL_PAD_EIM_DATA25; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data26_t SW_PAD_CTL_PAD_EIM_DATA26; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data27_t SW_PAD_CTL_PAD_EIM_DATA27; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data28_t SW_PAD_CTL_PAD_EIM_DATA28; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data29_t SW_PAD_CTL_PAD_EIM_DATA29; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data30_t SW_PAD_CTL_PAD_EIM_DATA30; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_data31_t SW_PAD_CTL_PAD_EIM_DATA31; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr24_t SW_PAD_CTL_PAD_EIM_ADDR24; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr23_t SW_PAD_CTL_PAD_EIM_ADDR23; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr22_t SW_PAD_CTL_PAD_EIM_ADDR22; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr21_t SW_PAD_CTL_PAD_EIM_ADDR21; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr20_t SW_PAD_CTL_PAD_EIM_ADDR20; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr19_t SW_PAD_CTL_PAD_EIM_ADDR19; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr18_t SW_PAD_CTL_PAD_EIM_ADDR18; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr17_t SW_PAD_CTL_PAD_EIM_ADDR17; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_addr16_t SW_PAD_CTL_PAD_EIM_ADDR16; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_cs0_t SW_PAD_CTL_PAD_EIM_CS0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_cs1_t SW_PAD_CTL_PAD_EIM_CS1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_oe_t SW_PAD_CTL_PAD_EIM_OE; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_rw_t SW_PAD_CTL_PAD_EIM_RW; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_lba_t SW_PAD_CTL_PAD_EIM_LBA; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_eb0_t SW_PAD_CTL_PAD_EIM_EB0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_eb1_t SW_PAD_CTL_PAD_EIM_EB1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad00_t SW_PAD_CTL_PAD_EIM_AD00; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad01_t SW_PAD_CTL_PAD_EIM_AD01; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad02_t SW_PAD_CTL_PAD_EIM_AD02; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad03_t SW_PAD_CTL_PAD_EIM_AD03; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad04_t SW_PAD_CTL_PAD_EIM_AD04; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad05_t SW_PAD_CTL_PAD_EIM_AD05; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad06_t SW_PAD_CTL_PAD_EIM_AD06; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad07_t SW_PAD_CTL_PAD_EIM_AD07; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad08_t SW_PAD_CTL_PAD_EIM_AD08; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad09_t SW_PAD_CTL_PAD_EIM_AD09; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad10_t SW_PAD_CTL_PAD_EIM_AD10; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad11_t SW_PAD_CTL_PAD_EIM_AD11; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad12_t SW_PAD_CTL_PAD_EIM_AD12; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad13_t SW_PAD_CTL_PAD_EIM_AD13; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad14_t SW_PAD_CTL_PAD_EIM_AD14; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_ad15_t SW_PAD_CTL_PAD_EIM_AD15; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_wait_t SW_PAD_CTL_PAD_EIM_WAIT; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_eim_bclk_t SW_PAD_CTL_PAD_EIM_BCLK; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_di0_disp_clk_t SW_PAD_CTL_PAD_DI0_DISP_CLK; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_di0_pin15_t SW_PAD_CTL_PAD_DI0_PIN15; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_di0_pin02_t SW_PAD_CTL_PAD_DI0_PIN02; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_di0_pin03_t SW_PAD_CTL_PAD_DI0_PIN03; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_di0_pin04_t SW_PAD_CTL_PAD_DI0_PIN04; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data00_t SW_PAD_CTL_PAD_DISP0_DATA00; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data01_t SW_PAD_CTL_PAD_DISP0_DATA01; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data02_t SW_PAD_CTL_PAD_DISP0_DATA02; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data03_t SW_PAD_CTL_PAD_DISP0_DATA03; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data04_t SW_PAD_CTL_PAD_DISP0_DATA04; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data05_t SW_PAD_CTL_PAD_DISP0_DATA05; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data06_t SW_PAD_CTL_PAD_DISP0_DATA06; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data07_t SW_PAD_CTL_PAD_DISP0_DATA07; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data08_t SW_PAD_CTL_PAD_DISP0_DATA08; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data09_t SW_PAD_CTL_PAD_DISP0_DATA09; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data10_t SW_PAD_CTL_PAD_DISP0_DATA10; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data11_t SW_PAD_CTL_PAD_DISP0_DATA11; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data12_t SW_PAD_CTL_PAD_DISP0_DATA12; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data13_t SW_PAD_CTL_PAD_DISP0_DATA13; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data14_t SW_PAD_CTL_PAD_DISP0_DATA14; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data15_t SW_PAD_CTL_PAD_DISP0_DATA15; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data16_t SW_PAD_CTL_PAD_DISP0_DATA16; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data17_t SW_PAD_CTL_PAD_DISP0_DATA17; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data18_t SW_PAD_CTL_PAD_DISP0_DATA18; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data19_t SW_PAD_CTL_PAD_DISP0_DATA19; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data20_t SW_PAD_CTL_PAD_DISP0_DATA20; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data21_t SW_PAD_CTL_PAD_DISP0_DATA21; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data22_t SW_PAD_CTL_PAD_DISP0_DATA22; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_disp0_data23_t SW_PAD_CTL_PAD_DISP0_DATA23; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_mdio_t SW_PAD_CTL_PAD_ENET_MDIO; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_ref_clk_t SW_PAD_CTL_PAD_ENET_REF_CLK; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_rx_er_t SW_PAD_CTL_PAD_ENET_RX_ER; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_crs_dv_t SW_PAD_CTL_PAD_ENET_CRS_DV; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_rx_data1_t SW_PAD_CTL_PAD_ENET_RX_DATA1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_rx_data0_t SW_PAD_CTL_PAD_ENET_RX_DATA0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_tx_en_t SW_PAD_CTL_PAD_ENET_TX_EN; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_tx_data1_t SW_PAD_CTL_PAD_ENET_TX_DATA1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_tx_data0_t SW_PAD_CTL_PAD_ENET_TX_DATA0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_enet_mdc_t SW_PAD_CTL_PAD_ENET_MDC; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs5_p_t SW_PAD_CTL_PAD_DRAM_SDQS5_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm5_t SW_PAD_CTL_PAD_DRAM_DQM5; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm4_t SW_PAD_CTL_PAD_DRAM_DQM4; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs4_p_t SW_PAD_CTL_PAD_DRAM_SDQS4_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs3_p_t SW_PAD_CTL_PAD_DRAM_SDQS3_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm3_t SW_PAD_CTL_PAD_DRAM_DQM3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs2_p_t SW_PAD_CTL_PAD_DRAM_SDQS2_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm2_t SW_PAD_CTL_PAD_DRAM_DQM2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr00_t SW_PAD_CTL_PAD_DRAM_ADDR00; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr01_t SW_PAD_CTL_PAD_DRAM_ADDR01; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr02_t SW_PAD_CTL_PAD_DRAM_ADDR02; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr03_t SW_PAD_CTL_PAD_DRAM_ADDR03; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr04_t SW_PAD_CTL_PAD_DRAM_ADDR04; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr05_t SW_PAD_CTL_PAD_DRAM_ADDR05; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr06_t SW_PAD_CTL_PAD_DRAM_ADDR06; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr07_t SW_PAD_CTL_PAD_DRAM_ADDR07; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr08_t SW_PAD_CTL_PAD_DRAM_ADDR08; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr09_t SW_PAD_CTL_PAD_DRAM_ADDR09; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr10_t SW_PAD_CTL_PAD_DRAM_ADDR10; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr11_t SW_PAD_CTL_PAD_DRAM_ADDR11; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr12_t SW_PAD_CTL_PAD_DRAM_ADDR12; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr13_t SW_PAD_CTL_PAD_DRAM_ADDR13; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr14_t SW_PAD_CTL_PAD_DRAM_ADDR14; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_addr15_t SW_PAD_CTL_PAD_DRAM_ADDR15; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_cas_t SW_PAD_CTL_PAD_DRAM_CAS; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_cs0_t SW_PAD_CTL_PAD_DRAM_CS0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_cs1_t SW_PAD_CTL_PAD_DRAM_CS1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_ras_t SW_PAD_CTL_PAD_DRAM_RAS; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_reset_t SW_PAD_CTL_PAD_DRAM_RESET; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdba0_t SW_PAD_CTL_PAD_DRAM_SDBA0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdba1_t SW_PAD_CTL_PAD_DRAM_SDBA1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdclk0_p_t SW_PAD_CTL_PAD_DRAM_SDCLK0_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdba2_t SW_PAD_CTL_PAD_DRAM_SDBA2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdcke0_t SW_PAD_CTL_PAD_DRAM_SDCKE0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdclk1_p_t SW_PAD_CTL_PAD_DRAM_SDCLK1_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdcke1_t SW_PAD_CTL_PAD_DRAM_SDCKE1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_odt0_t SW_PAD_CTL_PAD_DRAM_ODT0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_odt1_t SW_PAD_CTL_PAD_DRAM_ODT1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdwe_t SW_PAD_CTL_PAD_DRAM_SDWE; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs0_p_t SW_PAD_CTL_PAD_DRAM_SDQS0_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm0_t SW_PAD_CTL_PAD_DRAM_DQM0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs1_p_t SW_PAD_CTL_PAD_DRAM_SDQS1_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm1_t SW_PAD_CTL_PAD_DRAM_DQM1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs6_p_t SW_PAD_CTL_PAD_DRAM_SDQS6_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm6_t SW_PAD_CTL_PAD_DRAM_DQM6; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_sdqs7_p_t SW_PAD_CTL_PAD_DRAM_SDQS7_P; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_dram_dqm7_t SW_PAD_CTL_PAD_DRAM_DQM7; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_col0_t SW_PAD_CTL_PAD_KEY_COL0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_row0_t SW_PAD_CTL_PAD_KEY_ROW0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_col1_t SW_PAD_CTL_PAD_KEY_COL1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_row1_t SW_PAD_CTL_PAD_KEY_ROW1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_col2_t SW_PAD_CTL_PAD_KEY_COL2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_row2_t SW_PAD_CTL_PAD_KEY_ROW2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_col3_t SW_PAD_CTL_PAD_KEY_COL3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_row3_t SW_PAD_CTL_PAD_KEY_ROW3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_col4_t SW_PAD_CTL_PAD_KEY_COL4; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_key_row4_t SW_PAD_CTL_PAD_KEY_ROW4; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio00_t SW_PAD_CTL_PAD_GPIO00; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio01_t SW_PAD_CTL_PAD_GPIO01; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio09_t SW_PAD_CTL_PAD_GPIO09; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio03_t SW_PAD_CTL_PAD_GPIO03; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio06_t SW_PAD_CTL_PAD_GPIO06; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio02_t SW_PAD_CTL_PAD_GPIO02; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio04_t SW_PAD_CTL_PAD_GPIO04; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio05_t SW_PAD_CTL_PAD_GPIO05; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio07_t SW_PAD_CTL_PAD_GPIO07; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio08_t SW_PAD_CTL_PAD_GPIO08; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio16_t SW_PAD_CTL_PAD_GPIO16; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio17_t SW_PAD_CTL_PAD_GPIO17; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio18_t SW_PAD_CTL_PAD_GPIO18; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_gpio19_t SW_PAD_CTL_PAD_GPIO19; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_pixclk_t SW_PAD_CTL_PAD_CSI0_PIXCLK; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_hsync_t SW_PAD_CTL_PAD_CSI0_HSYNC; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data_en_t SW_PAD_CTL_PAD_CSI0_DATA_EN; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_vsync_t SW_PAD_CTL_PAD_CSI0_VSYNC; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data04_t SW_PAD_CTL_PAD_CSI0_DATA04; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data05_t SW_PAD_CTL_PAD_CSI0_DATA05; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data06_t SW_PAD_CTL_PAD_CSI0_DATA06; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data07_t SW_PAD_CTL_PAD_CSI0_DATA07; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data08_t SW_PAD_CTL_PAD_CSI0_DATA08; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data09_t SW_PAD_CTL_PAD_CSI0_DATA09; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data10_t SW_PAD_CTL_PAD_CSI0_DATA10; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data11_t SW_PAD_CTL_PAD_CSI0_DATA11; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data12_t SW_PAD_CTL_PAD_CSI0_DATA12; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data13_t SW_PAD_CTL_PAD_CSI0_DATA13; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data14_t SW_PAD_CTL_PAD_CSI0_DATA14; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data15_t SW_PAD_CTL_PAD_CSI0_DATA15; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data16_t SW_PAD_CTL_PAD_CSI0_DATA16; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data17_t SW_PAD_CTL_PAD_CSI0_DATA17; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data18_t SW_PAD_CTL_PAD_CSI0_DATA18; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_csi0_data19_t SW_PAD_CTL_PAD_CSI0_DATA19; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_jtag_tms_t SW_PAD_CTL_PAD_JTAG_TMS; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_jtag_mod_t SW_PAD_CTL_PAD_JTAG_MOD; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_jtag_trstb_t SW_PAD_CTL_PAD_JTAG_TRSTB; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_jtag_tdi_t SW_PAD_CTL_PAD_JTAG_TDI; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_jtag_tck_t SW_PAD_CTL_PAD_JTAG_TCK; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_jtag_tdo_t SW_PAD_CTL_PAD_JTAG_TDO; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data7_t SW_PAD_CTL_PAD_SD3_DATA7; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data6_t SW_PAD_CTL_PAD_SD3_DATA6; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data5_t SW_PAD_CTL_PAD_SD3_DATA5; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data4_t SW_PAD_CTL_PAD_SD3_DATA4; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_cmd_t SW_PAD_CTL_PAD_SD3_CMD; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_clk_t SW_PAD_CTL_PAD_SD3_CLK; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data0_t SW_PAD_CTL_PAD_SD3_DATA0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data1_t SW_PAD_CTL_PAD_SD3_DATA1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data2_t SW_PAD_CTL_PAD_SD3_DATA2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_data3_t SW_PAD_CTL_PAD_SD3_DATA3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd3_reset_t SW_PAD_CTL_PAD_SD3_RESET; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_cle_t SW_PAD_CTL_PAD_NAND_CLE; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_ale_t SW_PAD_CTL_PAD_NAND_ALE; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_wp_b_t SW_PAD_CTL_PAD_NAND_WP_B; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_ready_t SW_PAD_CTL_PAD_NAND_READY; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_cs0_b_t SW_PAD_CTL_PAD_NAND_CS0_B; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_cs1_b_t SW_PAD_CTL_PAD_NAND_CS1_B; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_cs2_b_t SW_PAD_CTL_PAD_NAND_CS2_B; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_cs3_b_t SW_PAD_CTL_PAD_NAND_CS3_B; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_cmd_t SW_PAD_CTL_PAD_SD4_CMD; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_clk_t SW_PAD_CTL_PAD_SD4_CLK; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_data00_t SW_PAD_CTL_PAD_NAND_DATA00; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_data01_t SW_PAD_CTL_PAD_NAND_DATA01; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_data02_t SW_PAD_CTL_PAD_NAND_DATA02; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_data03_t SW_PAD_CTL_PAD_NAND_DATA03; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_data04_t SW_PAD_CTL_PAD_NAND_DATA04; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_data05_t SW_PAD_CTL_PAD_NAND_DATA05; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_data06_t SW_PAD_CTL_PAD_NAND_DATA06; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_nand_data07_t SW_PAD_CTL_PAD_NAND_DATA07; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data0_t SW_PAD_CTL_PAD_SD4_DATA0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data1_t SW_PAD_CTL_PAD_SD4_DATA1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data2_t SW_PAD_CTL_PAD_SD4_DATA2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data3_t SW_PAD_CTL_PAD_SD4_DATA3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data4_t SW_PAD_CTL_PAD_SD4_DATA4; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data5_t SW_PAD_CTL_PAD_SD4_DATA5; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data6_t SW_PAD_CTL_PAD_SD4_DATA6; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd4_data7_t SW_PAD_CTL_PAD_SD4_DATA7; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd1_data1_t SW_PAD_CTL_PAD_SD1_DATA1; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd1_data0_t SW_PAD_CTL_PAD_SD1_DATA0; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd1_data3_t SW_PAD_CTL_PAD_SD1_DATA3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd1_cmd_t SW_PAD_CTL_PAD_SD1_CMD; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd1_data2_t SW_PAD_CTL_PAD_SD1_DATA2; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd1_clk_t SW_PAD_CTL_PAD_SD1_CLK; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd2_clk_t SW_PAD_CTL_PAD_SD2_CLK; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd2_cmd_t SW_PAD_CTL_PAD_SD2_CMD; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_pad_sd2_data3_t SW_PAD_CTL_PAD_SD2_DATA3; //!< Pad Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_b7ds_t SW_PAD_CTL_GRP_B7DS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_addds_t SW_PAD_CTL_GRP_ADDDS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_ddrmode_ctl_t SW_PAD_CTL_GRP_DDRMODE_CTL; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl0_t SW_PAD_CTL_GRP_TERM_CTL0; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_ddrpke_t SW_PAD_CTL_GRP_DDRPKE; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl1_t SW_PAD_CTL_GRP_TERM_CTL1; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl2_t SW_PAD_CTL_GRP_TERM_CTL2; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl3_t SW_PAD_CTL_GRP_TERM_CTL3; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_ddrpk_t SW_PAD_CTL_GRP_DDRPK; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl4_t SW_PAD_CTL_GRP_TERM_CTL4; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_ddrhys_t SW_PAD_CTL_GRP_DDRHYS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_ddrmode_t SW_PAD_CTL_GRP_DDRMODE; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl5_t SW_PAD_CTL_GRP_TERM_CTL5; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl6_t SW_PAD_CTL_GRP_TERM_CTL6; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_term_ctl7_t SW_PAD_CTL_GRP_TERM_CTL7; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_b0ds_t SW_PAD_CTL_GRP_B0DS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_b1ds_t SW_PAD_CTL_GRP_B1DS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_ctlds_t SW_PAD_CTL_GRP_CTLDS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_ddr_type_rgmii_t SW_PAD_CTL_GRP_DDR_TYPE_RGMII; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_b2ds_t SW_PAD_CTL_GRP_B2DS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_ddr_type_t SW_PAD_CTL_GRP_DDR_TYPE; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_b3ds_t SW_PAD_CTL_GRP_B3DS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_b4ds_t SW_PAD_CTL_GRP_B4DS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_b5ds_t SW_PAD_CTL_GRP_B5DS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_b6ds_t SW_PAD_CTL_GRP_B6DS; //!< Pad Group Control Register
    volatile hw_iomuxc_sw_pad_ctl_grp_rgmii_term_t SW_PAD_CTL_GRP_RGMII_TERM; //!< Pad Group Control Register
    volatile hw_iomuxc_asrc_asrck_clock_6_select_input_t ASRC_ASRCK_CLOCK_6_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud4_input_da_amx_select_input_t AUD4_INPUT_DA_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud4_input_db_amx_select_input_t AUD4_INPUT_DB_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud4_input_rxclk_amx_select_input_t AUD4_INPUT_RXCLK_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud4_input_rxfs_amx_select_input_t AUD4_INPUT_RXFS_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud4_input_txclk_amx_select_input_t AUD4_INPUT_TXCLK_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud4_input_txfs_amx_select_input_t AUD4_INPUT_TXFS_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud5_input_da_amx_select_input_t AUD5_INPUT_DA_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud5_input_db_amx_select_input_t AUD5_INPUT_DB_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud5_input_rxclk_amx_select_input_t AUD5_INPUT_RXCLK_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud5_input_rxfs_amx_select_input_t AUD5_INPUT_RXFS_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud5_input_txclk_amx_select_input_t AUD5_INPUT_TXCLK_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_aud5_input_txfs_amx_select_input_t AUD5_INPUT_TXFS_AMX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_flexcan1_rx_select_input_t FLEXCAN1_RX_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_flexcan2_rx_select_input_t FLEXCAN2_RX_SELECT_INPUT; //!< Select Input Register
    reg32_t _reserved1;
    volatile hw_iomuxc_ccm_pmic_ready_select_input_t CCM_PMIC_READY_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi1_cspi_clk_in_select_input_t ECSPI1_CSPI_CLK_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi1_miso_select_input_t ECSPI1_MISO_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi1_mosi_select_input_t ECSPI1_MOSI_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi1_ss0_select_input_t ECSPI1_SS0_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi1_ss1_select_input_t ECSPI1_SS1_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi1_ss2_select_input_t ECSPI1_SS2_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi1_ss3_select_input_t ECSPI1_SS3_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi2_cspi_clk_in_select_input_t ECSPI2_CSPI_CLK_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi2_miso_select_input_t ECSPI2_MISO_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi2_mosi_select_input_t ECSPI2_MOSI_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi2_ss0_select_input_t ECSPI2_SS0_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi2_ss1_select_input_t ECSPI2_SS1_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi4_ss0_select_input_t ECSPI4_SS0_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi5_cspi_clk_in_select_input_t ECSPI5_CSPI_CLK_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi5_miso_select_input_t ECSPI5_MISO_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi5_mosi_select_input_t ECSPI5_MOSI_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi5_ss0_select_input_t ECSPI5_SS0_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ecspi5_ss1_select_input_t ECSPI5_SS1_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_enet_ref_clk_select_input_t ENET_REF_CLK_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_enet_mac0_mdio_select_input_t ENET_MAC0_MDIO_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_enet_mac0_rx_clk_select_input_t ENET_MAC0_RX_CLK_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_enet_mac0_rx_data0_select_input_t ENET_MAC0_RX_DATA0_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_enet_mac0_rx_data1_select_input_t ENET_MAC0_RX_DATA1_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_enet_mac0_rx_data2_select_input_t ENET_MAC0_RX_DATA2_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_enet_mac0_rx_data3_select_input_t ENET_MAC0_RX_DATA3_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_enet_mac0_rx_en_select_input_t ENET_MAC0_RX_EN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_rx_fs_select_input_t ESAI_RX_FS_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_tx_fs_select_input_t ESAI_TX_FS_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_rx_hf_clk_select_input_t ESAI_RX_HF_CLK_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_tx_hf_clk_select_input_t ESAI_TX_HF_CLK_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_rx_clk_select_input_t ESAI_RX_CLK_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_tx_clk_select_input_t ESAI_TX_CLK_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_sdo0_select_input_t ESAI_SDO0_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_sdo1_select_input_t ESAI_SDO1_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_sdo2_sdi3_select_input_t ESAI_SDO2_SDI3_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_sdo3_sdi2_select_input_t ESAI_SDO3_SDI2_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_sdo4_sdi1_select_input_t ESAI_SDO4_SDI1_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_esai_sdo5_sdi0_select_input_t ESAI_SDO5_SDI0_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_hdmi_icecin_select_input_t HDMI_ICECIN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_hdmi_ii2c_clkin_select_input_t HDMI_II2C_CLKIN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_hdmi_ii2c_datain_select_input_t HDMI_II2C_DATAIN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_i2c1_scl_in_select_input_t I2C1_SCL_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_i2c1_sda_in_select_input_t I2C1_SDA_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_i2c2_scl_in_select_input_t I2C2_SCL_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_i2c2_sda_in_select_input_t I2C2_SDA_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_i2c3_scl_in_select_input_t I2C3_SCL_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_i2c3_sda_in_select_input_t I2C3_SDA_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data10_select_input_t IPU2_SENS1_DATA10_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data11_select_input_t IPU2_SENS1_DATA11_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data12_select_input_t IPU2_SENS1_DATA12_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data13_select_input_t IPU2_SENS1_DATA13_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data14_select_input_t IPU2_SENS1_DATA14_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data15_select_input_t IPU2_SENS1_DATA15_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data16_select_input_t IPU2_SENS1_DATA16_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data17_select_input_t IPU2_SENS1_DATA17_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data18_select_input_t IPU2_SENS1_DATA18_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data19_select_input_t IPU2_SENS1_DATA19_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_data_en_select_input_t IPU2_SENS1_DATA_EN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_hsync_select_input_t IPU2_SENS1_HSYNC_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_pix_clk_select_input_t IPU2_SENS1_PIX_CLK_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_ipu2_sens1_vsync_select_input_t IPU2_SENS1_VSYNC_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_key_col5_select_input_t KEY_COL5_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_key_col6_select_input_t KEY_COL6_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_key_col7_select_input_t KEY_COL7_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_key_row5_select_input_t KEY_ROW5_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_key_row6_select_input_t KEY_ROW6_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_key_row7_select_input_t KEY_ROW7_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_mlb_mlb_clk_in_select_input_t MLB_MLB_CLK_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_mlb_mlb_data_in_select_input_t MLB_MLB_DATA_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_mlb_mlb_sig_in_select_input_t MLB_MLB_SIG_IN_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_sdma_events14_select_input_t SDMA_EVENTS14_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_sdma_events15_select_input_t SDMA_EVENTS15_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_spdif_spdif_in1_select_input_t SPDIF_SPDIF_IN1_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_spdif_tx_clk2_select_input_t SPDIF_TX_CLK2_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart1_uart_rts_b_select_input_t UART1_UART_RTS_B_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart1_uart_rx_data_select_input_t UART1_UART_RX_DATA_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart2_uart_rts_b_select_input_t UART2_UART_RTS_B_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart2_uart_rx_data_select_input_t UART2_UART_RX_DATA_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart3_uart_rts_b_select_input_t UART3_UART_RTS_B_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart3_uart_rx_data_select_input_t UART3_UART_RX_DATA_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart4_uart_rts_b_select_input_t UART4_UART_RTS_B_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart4_uart_rx_data_select_input_t UART4_UART_RX_DATA_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart5_uart_rts_b_select_input_t UART5_UART_RTS_B_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_uart5_uart_rx_data_select_input_t UART5_UART_RX_DATA_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_usb_otg_oc_select_input_t USB_OTG_OC_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_usb_h1_oc_select_input_t USB_H1_OC_SELECT_INPUT; //!< Select Input Register
    volatile hw_iomuxc_usdhc1_wp_on_select_input_t USDHC1_WP_ON_SELECT_INPUT; //!< Select Input Register
} hw_iomuxc_t;
#pragma pack()

//! @brief Macro to access all IOMUXC registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//!     use the '&' operator, like <code>&HW_IOMUXC</code>.
#define HW_IOMUXC     (*(hw_iomuxc_t *) REGS_IOMUXC_BASE)
#endif

#endif // __HW_IOMUXC_REGISTERS_H__
// v18/121106/1.2.2
// EOF