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micro_kern
| Author | SHA1 | Date |
|---|---|---|
 TXuian
|
98bd60356a | |
|
TXuian
|
1bca808abf | |
|
TXuian
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5e87814024 | |
|
TXuian
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59c5ab7a02 | |
 Liu_Weichao
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553f4c457e |
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@ -1,18 +0,0 @@
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|||
#
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# Automatically generated file; DO NOT EDIT.
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# XiZi_AIoT Project Configuration
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#
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CONFIG_BOARD_IMX6Q_SABRELITE_EVB=y
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CONFIG_ARCH_ARM=y
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#
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# imx6q sabrelite feature
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#
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#
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# Lib
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#
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CONFIG_LIB=y
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CONFIG_LIB_POSIX=y
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CONFIG_LIB_NEWLIB=y
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# CONFIG_LIB_MUSLLIB is not set
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@ -9,7 +9,7 @@ emulator_support +=
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support := $(riscv_support) $(arm_support) $(emulator_support)
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SRC_DIR :=
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export BOARD ?=imx6q-sabrelite
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export BOARD ?= imx6q-sabrelite
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# This is the environment variable for kconfig-mconf
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export KCONFIG_CONFIG ?= .config
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@ -19,7 +19,6 @@ $(warning "This is what we support:")
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$(warning "RISCV EVB: $(riscv_support)")
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$(warning "ARM EVB: $(arm_support)")
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$(warning "EMULATORS: $(emulator_support)")
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# $(warning "$(support)")
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$(error "break" )
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endif
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@ -32,20 +31,18 @@ MAKEFILES =$(KERNEL_ROOT)/.config
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export BSP_ROOT ?= $(KERNEL_ROOT)/services/boards/$(BOARD)
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export UBIQUITOUS_ROOT ?= ..
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include services/boards/$(BOARD)/config.mk
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export BSP_BUILD_DIR := boards/$(BOARD)
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include $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/config.mk
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export BSP_BUILD_DIR := $(KERNEL_ROOT)
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export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/services/tools/hosttools
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export CONFIG2H_EXE ?= $(HOSTTOOLS_DIR)/xsconfig.sh
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export CPPPATHS
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export SRC_APP_DIR := ../../APP_Framework
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export SRC_KERNEL_DIR := hardkernel services softkernel support testing
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# export SRC_DIR:= $(SRC_APP_DIR) $(SRC_KERNEL_DIR)
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export SRC_DIR:= $(SRC_KERNEL_DIR)
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export SRC_KERNEL_DIR := hardkernel softkernel
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export SRC_DIR := $(SRC_KERNEL_DIR)
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export LIBCC
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export MUSL_DIR := $(KERNEL_ROOT)/services/lib/musllib
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PART:=
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PART :=
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all:
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ifeq ($(CONFIG_COMPILER_APP)_$(CONFIG_COMPILER_KERNEL),y_)
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@ -78,15 +75,6 @@ COMPILE_ALL:
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@$(MAKE) -C build TARGET=XiZi-$(BOARD).elf LINK_FLAGS=LFLAGS
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@rm build/Makefile build/make.obj
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COMPILE_MUSL:
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@for dir in $(MUSL_DIR);do \
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$(MAKE) -C $$dir COMPILE_TYPE=$@ CONFIG_RESOURCES_LWIP=n; \
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done
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@cp link_libc.mk build/Makefile
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@$(MAKE) -C build TARGET=libmusl.a LINK_FLAGS=LFLAGS
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@cp build/libmusl.a $(KERNEL_ROOT)/lib/musllib/libmusl.a
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@rm build/Makefile build/make.obj
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COMPILE_KERNEL:
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@for dir in $(SRC_KERNEL_DIR);do \
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$(MAKE) -C $$dir; \
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@ -0,0 +1,265 @@
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/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/imx6q_init.o: \
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/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/boot/src/imx6q_init.c \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/imx6q.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/iomux_v3.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/soc_memory_map.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/regs_anadig.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/regs_pins.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regsuart.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regs.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/crm_regs.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regs.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/arm_cp_registers.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/uart.h
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/boot.o: \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/boot/src/boot.c \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/mmu.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/bootdriver.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/serial.h
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/start_boot.o: \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/boot/src/start_boot.S
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/lowlevel_init.o: \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/boot/src/lowlevel_init.S \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/soc_memory_map.h
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/vector_table.o: \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/boot/src/vector_table.S
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/ivt.o: \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/boot/sdk/imx6/src/ivt.c \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/hab_defines.h
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/dcd.o: \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/boot/sdk/imx6/src/dcd.c \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/hab_defines.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/soc_memory_map.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/iomux_register.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regs.h
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/mmu.o: \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/src/mmu.c \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/mmu.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/vm.h
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/serial.o: \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/src/serial.c \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/serial.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/imx_uart.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/trap.h \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/irq_numbers.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/cortex_a9.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/cpu.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/uart.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/imx6q.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/iomux_v3.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/soc_memory_map.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/regs_anadig.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/regs_pins.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regsuart.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regs.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/crm_regs.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regs.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/arm_cp_registers.h
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/iomux_v3.o: \
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||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/sdk/imx6/src/iomux_v3.c \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/imx6q.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/iomux_v3.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/soc_memory_map.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/regs_anadig.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/regs_pins.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regsuart.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regs.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/crm_regs.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regs.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/arm_cp_registers.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/uart.h
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/uart.o: \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/sdk/imx6/src/uart.c \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/uart.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/imx6q.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/iomux_v3.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/soc_memory_map.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/regs_anadig.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/regs_pins.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regsuart.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regs.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/crm_regs.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/registers/regs.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/arm_cp_registers.h
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/imx_uart.o: \
|
||||
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|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/memory/multiple-address-spaces/pager.c \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/phymem.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/mmu.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/spinlock.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/vm.h
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/irq.o: \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/trap/irq.c \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/gic.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/cpu.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/clock.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/trap.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/irq_numbers.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/cortex_a9.h
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/trap.o: \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/trap/trap.c \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/trap.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/irq_numbers.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/cortex_a9.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/cpu.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/process.o: \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/proc/process.c \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/process.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/cpu.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/trap.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/irq_numbers.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/imx6q_platform_sdk/cortex_a9.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/vm.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/include/mmu.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/spinlock.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/phymem.h
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/build/initproc.o: \
|
||||
/home/tuxian/work/microkernel/xiuos/Ubiquitous/XiZi_AIoT/softkernel/proc/initproc.S
|
||||
|
|
@ -1,20 +1,8 @@
|
|||
ifeq ($(COMPILE_TYPE), COMPILE_MUSL)
|
||||
SRC_DIR_TEMP := $(MUSL_DIR)
|
||||
else ifeq ($(COMPILE_TYPE), COMPILE_LWIP)
|
||||
SRC_DIR_TEMP := $(LWIP_DIR)
|
||||
else
|
||||
SRC_DIR_TEMP := $(SRC_DIR)
|
||||
endif
|
||||
|
||||
SRC_DIR :=
|
||||
MUSL_DIR :=
|
||||
LWIP_DIR :=
|
||||
|
||||
ifeq ($(USE_APP_INCLUDEPATH), y)
|
||||
include $(KERNEL_ROOT)/path_app.mk
|
||||
else
|
||||
include $(KERNEL_ROOT)/path_kernel.mk
|
||||
endif
|
||||
include $(KERNEL_ROOT)/path_kernel.mk
|
||||
|
||||
export CPPPATHS := $(KERNELPATHS)
|
||||
|
||||
CUR_DIR :=$(shell pwd)
|
||||
|
|
@ -27,9 +15,8 @@ CFLAGS += $(DEFINES)
|
|||
AFLAGS += $(DEFINES)
|
||||
CXXFLAGS += $(DEFINES)
|
||||
BUILD_DIR := $(KERNEL_ROOT)/build
|
||||
APP_DIR := Ubiquitous/XiZi
|
||||
APP_DIR := Ubiquitous/XiZi_AIoT
|
||||
|
||||
|
||||
.PHONY:COMPILER
|
||||
COMPILER:
|
||||
@if [ "${SRC_DIR_TEMP}" != "" ]; then \
|
||||
|
|
@ -39,23 +26,22 @@ COMPILER:
|
|||
fi
|
||||
@/bin/echo -n $(OBJS) " " >> $(KERNEL_ROOT)/build/make.obj
|
||||
|
||||
|
||||
################################################
|
||||
define add_c_file
|
||||
$(eval COBJ := $(1:%.c=%.o)) \
|
||||
$(eval COBJ := $(notdir $(1:%.c=%.o))) \
|
||||
$(eval COBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(COBJ))) \
|
||||
$(eval LOCALC := $(addprefix $(BUILD_DIR)/,$(COBJ))) \
|
||||
$(eval OBJS += $(LOCALC)) \
|
||||
$(if $(strip $(LOCALC)),$(eval $(LOCALC): $(1)
|
||||
@if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi
|
||||
@echo cc $$<
|
||||
@echo cc $$<
|
||||
@/bin/echo -n $(dir $(LOCALC)) >>$(KERNEL_ROOT)/build/make.dep
|
||||
@($(CROSS_COMPILE)gcc -MM $$(CFLAGS) -c $$<) >>$(KERNEL_ROOT)/build/make.dep
|
||||
@$(CROSS_COMPILE)gcc $$(CFLAGS) -c $$< -o $$@))
|
||||
endef
|
||||
|
||||
define add_cpp_file
|
||||
$(eval COBJ := $(1:%.cpp=%.o)) \
|
||||
$(eval COBJ := $(notdir $(1:%.cpp=%.o))) \
|
||||
$(eval COBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(COBJ))) \
|
||||
$(eval LOCALCPP := $(addprefix $(BUILD_DIR)/,$(COBJ))) \
|
||||
$(eval OBJS += $(LOCALCPP)) \
|
||||
|
|
@ -68,7 +54,7 @@ $(if $(strip $(LOCALCPP)),$(eval $(LOCALCPP): $(1)
|
|||
endef
|
||||
|
||||
define add_cc_file
|
||||
$(eval COBJ := $(1:%.cc=%.o)) \
|
||||
$(eval COBJ := $(notdir $(1:%.cc=%.o))) \
|
||||
$(eval COBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(COBJ))) \
|
||||
$(eval LOCALCPP := $(addprefix $(BUILD_DIR)/,$(COBJ))) \
|
||||
$(eval OBJS += $(LOCALCPP)) \
|
||||
|
|
@ -81,7 +67,7 @@ $(if $(strip $(LOCALCPP)),$(eval $(LOCALCPP): $(1)
|
|||
endef
|
||||
|
||||
define add_S_file
|
||||
$(eval SOBJ := $(1:%.S=%.o)) \
|
||||
$(eval SOBJ := $(notdir $(1:%.S=%.o))) \
|
||||
$(eval SOBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(SOBJ))) \
|
||||
$(eval LOCALS := $(addprefix $(BUILD_DIR)/,$(SOBJ))) \
|
||||
$(eval OBJS += $(LOCALS)) \
|
||||
|
|
@ -94,7 +80,7 @@ $(if $(strip $(LOCALS)),$(eval $(LOCALS): $(1)
|
|||
endef
|
||||
|
||||
define add_a_file
|
||||
$(eval SOBJ := $(1:%.a=%.a)) \
|
||||
$(eval SOBJ := $(notdir $(1:%.a=%.a))) \
|
||||
$(eval SOBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(SOBJ))) \
|
||||
$(eval LOCALA := $(addprefix $(BUILD_DIR)/,$(SOBJ))) \
|
||||
$(eval OBJS += $(LOCALA)) \
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
SRC_DIR := arch abstraction
|
||||
SRC_DIR := boot mmu uart trap gpt cpu
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -1,3 +0,0 @@
|
|||
SRC_FILES := cache.c isr.c abstraction_mmu.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file: abstraction_mmu.c
|
||||
* @brief: the general management of system mmu
|
||||
* @version: 3.0
|
||||
* @author: AIIT XUOS Lab
|
||||
* @date: 2023/4/27
|
||||
*
|
||||
*/
|
||||
|
||||
#include <abstraction_mmu.h>
|
||||
|
||||
AbstractionMmu abstraction_mmu;
|
||||
|
||||
volatile uint32_t global_L1_pte_table[4096];
|
||||
|
||||
/**
|
||||
* @description: write cmd to CP15 register
|
||||
* @param reg_type - CP15 register type
|
||||
* @param val - ops val pointer
|
||||
* @return
|
||||
*/
|
||||
static void MmuCp15Write(uint8_t reg_type, uint32_t *val)
|
||||
{
|
||||
uint32_t write_val = *val;
|
||||
switch (reg_type) {
|
||||
case AM_MMU_CP15_TTBCR:
|
||||
TTBCR_W(write_val);
|
||||
AM_ISB;
|
||||
case AM_MMU_CP15_TTBR0:
|
||||
TTBR0_W(write_val);
|
||||
AM_ISB;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @description: read CP15 register from mmu
|
||||
* @param reg_type - CP15 register type
|
||||
* @param val - ops val pointer
|
||||
* @return
|
||||
*/
|
||||
static void MmuCp15Read(uint8_t reg_type, uint32_t *val)
|
||||
{
|
||||
uint32_t read_val = 0;
|
||||
switch (reg_type) {
|
||||
case AM_MMU_CP15_TTBCR:
|
||||
TTBCR_R(read_val);
|
||||
case AM_MMU_CP15_TTBR0:
|
||||
TTBR0_R(read_val);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
*val = read_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @description: write or read CP15 register to set mmu
|
||||
* @param ops_type - CP15 write or read
|
||||
* @param reg_type - CP15 register type
|
||||
* @param val - ops val pointer
|
||||
* @return
|
||||
*/
|
||||
static void MmuRegOps(uint8_t ops_type, uint8_t reg_type, uint32_t *val)
|
||||
{
|
||||
switch (ops_type) {
|
||||
case AM_MMU_CP15_WRITE:
|
||||
MmuCp15Write(reg_type, val);
|
||||
case AM_MMU_CP15_READ:
|
||||
MmuCp15Read(reg_type, val);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @description: Init abstraction_mmu function
|
||||
* @param mmu - abstraction mmu pointer
|
||||
* @param ttb_base - ttb base pointer
|
||||
* @return success : 0 error : -1
|
||||
*/
|
||||
static int _AbstractionMmuInit(AbstractionMmu *mmu, uint32_t *ttb_base)
|
||||
{
|
||||
mmu_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @description: map L1 or L2 page table section
|
||||
* @param mmu - abstraction mmu pointer
|
||||
* @param section_size - section size
|
||||
* @return success : 0 error : -1
|
||||
*/
|
||||
static int _AbstractionMmuSectionMap(AbstractionMmu *mmu, uint32_t section_size)
|
||||
{
|
||||
uint32_t vaddr_length = mmu->vaddr_end - mmu->vaddr_start + 1;
|
||||
|
||||
mmu_map_l1_range(mmu->paddr_start, mmu->vaddr_start, vaddr_length,
|
||||
mmu->mmu_memory_type, mmu->mmu_shareability, mmu->mmu_access);
|
||||
|
||||
mmu->mmu_status = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @description: unmap L1 or L2 page table section
|
||||
* @param mmu - abstraction mmu pointer
|
||||
* @param vaddr_start - virtual address start
|
||||
* @param vaddr_size - virtual address size
|
||||
* @return success : 0 error : -1
|
||||
*/
|
||||
static int _AbstractionMmuSectionUnmap(AbstractionMmu *mmu, uint32_t vaddr_start, uint32_t vaddr_size)
|
||||
{
|
||||
uint32_t *l1_umap_ventry = mmu->ttb_vbase + (vaddr_start >> AM_MMU_L1_SECTION_SHIFT);
|
||||
uint32_t vaddr_end = vaddr_start + vaddr_size - 1;
|
||||
uint32_t umap_count = (vaddr_end >> AM_MMU_L1_SECTION_SHIFT) - (vaddr_start >> AM_MMU_L1_SECTION_SHIFT) + 1;
|
||||
|
||||
while (umap_count) {
|
||||
AM_DMB;
|
||||
*l1_umap_ventry = 0;
|
||||
AM_DSB;
|
||||
|
||||
umap_count--;
|
||||
l1_umap_ventry += (1 << AM_MMU_L1_SECTION_SHIFT);//1MB section
|
||||
}
|
||||
|
||||
AM_DSB;
|
||||
CLEARTLB(0);//clear TLB data and configure
|
||||
AM_DSB;
|
||||
AM_ISB;
|
||||
mmu->mmu_status = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @description: switch ttb base by re-write ttbr register
|
||||
* @param mmu - abstraction mmu pointer
|
||||
* @return success : 0 error : -1
|
||||
*/
|
||||
static int _AbstractionMmuTtbSwitch(AbstractionMmu *mmu)
|
||||
{
|
||||
uint32_t ttbr, ttbcr;
|
||||
MmuRegOps(AM_MMU_CP15_READ, AM_MMU_CP15_TTBCR, &ttbcr);
|
||||
|
||||
/* Set TTBR0 with inner/outer write back write allocate and not shareable, [4:3]=01, [1]=0, [6,0]=01 */
|
||||
ttbr = ((mmu->ttb_pbase & 0xFFFFC000UL) | 0x9UL);
|
||||
/* enable TTBR0 */
|
||||
ttbcr = 0;
|
||||
|
||||
AM_DSB;
|
||||
MmuRegOps(AM_MMU_CP15_WRITE, AM_MMU_CP15_TTBR0, &ttbr);
|
||||
MmuRegOps(AM_MMU_CP15_WRITE, AM_MMU_CP15_TTBCR, &ttbcr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @description: get physical address transformed from virtual address
|
||||
* @param mmu - abstraction mmu pointer
|
||||
* @param vaddr - virtual address pointer
|
||||
* @param paddr - physical address pointer
|
||||
* @return success : 0 error : -1
|
||||
*/
|
||||
static int _AbstracktonMmuTransform(AbstractionMmu *mmu, uint32_t *vaddr, uint32_t *paddr)
|
||||
{
|
||||
uint32_t virtualAddress = *vaddr;
|
||||
|
||||
if (mmu->mmu_status) {
|
||||
mmu_virtual_to_physical(virtualAddress, paddr);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct AbstractionMmuDone mmu_done = {
|
||||
.AbstractionMmuInit = _AbstractionMmuInit,
|
||||
.AbstractionMmuSectionMap = _AbstractionMmuSectionMap,
|
||||
.AbstractionMmuSectionUnmap = _AbstractionMmuSectionUnmap,
|
||||
.AbstractionMmuTtbSwitch = _AbstractionMmuTtbSwitch,
|
||||
.AbstracktonMmuTransform = _AbstracktonMmuTransform,
|
||||
};
|
||||
|
||||
/**
|
||||
* @description: init abstraciton mmu info when system start
|
||||
* @return success : 0 error : -1
|
||||
*/
|
||||
int SysInitAbstractionMmu(void)
|
||||
{
|
||||
abstraction_mmu.mmu_done = &mmu_done;
|
||||
}
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file: mmu.h
|
||||
* @brief: the general management of system mmu
|
||||
* @version: 3.0
|
||||
* @author: AIIT XUOS Lab
|
||||
* @date: 2023/5/24
|
||||
*
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <mmu.h>
|
||||
|
||||
#define ARCH_ARM
|
||||
#ifdef ARCH_ARM
|
||||
/* ARM System Registers */
|
||||
#define AM_DSB __asm__ volatile("dsb" ::: "memory")
|
||||
#define AM_DMB __asm__ volatile("dmb" ::: "memory")
|
||||
#define AM_ISB __asm__ volatile("isb" ::: "memory")
|
||||
#define AM_WFI __asm__ volatile("wfi" ::: "memory")
|
||||
#define AM_BARRIER __asm__ volatile("":::"memory")
|
||||
#define AM_WFE __asm__ volatile("wfe" ::: "memory")
|
||||
#define AM_SEV __asm__ volatile("sev" ::: "memory")
|
||||
|
||||
#define TTBR0_R(val) __asm__ volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(val))
|
||||
#define TTBR0_W(val) __asm__ volatile("mcr p15, 0, %0, c2, c0, 0" ::"r"(val))
|
||||
|
||||
#define TTBCR_R(val) __asm__ volatile("mrc p15, 0, %0, c2, c0, 2" : "=r"(val))
|
||||
#define TTBCR_W(val) __asm__ volatile("mcr p15, 0, %0, c2, c0, 2" ::"r"(val))
|
||||
|
||||
#define CLEARTLB(val) __asm__ volatile("mcr p15, 0, %0, c8, c7, 0" ::"r"(val))
|
||||
#endif
|
||||
|
||||
#define AM_MMU_L1_PAGE_TABLE_SIZE (4 * 4096)
|
||||
#define AM_MMU_L1_SECTION_SHIFT 20
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AM_MMU_CP15_WRITE = 0,
|
||||
AM_MMU_CP15_READ,
|
||||
}MmuCP15OpsType;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AM_MMU_CP15_TTBCR = 0,
|
||||
AM_MMU_CP15_TTBR0,
|
||||
AM_MMU_CP15_CLEARTLB,
|
||||
}MmuCP15RegType;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AM_StronglyOrdered = 0,
|
||||
AM_Device,
|
||||
AM_OuterInner_WB_WA,
|
||||
AM_OuterInner_WT,
|
||||
AM_Noncacheable,
|
||||
}MmuMemoryType;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AM_Noaccess = 0,
|
||||
AM_Read_Write,
|
||||
AM_Read,
|
||||
}MmuAccess;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AM_Shareable = 1,
|
||||
AM_Nonshareable = 0
|
||||
}MmuShareability;
|
||||
|
||||
struct AbstractionMmuDone
|
||||
{
|
||||
int (*AbstractionMmuInit)(AbstractionMmu *mmu, uint32_t *ttb_base);
|
||||
int (*AbstractionMmuSectionMap)(AbstractionMmu *mmu, uint32_t section_size);
|
||||
int (*AbstractionMmuSectionUnmap)(AbstractionMmu *mmu, uint32_t vaddr_start, uint32_t vaddr_size);
|
||||
int (*AbstractionMmuTtbSwitch)(AbstractionMmu *mmu);
|
||||
int (*AbstracktonMmuTransform)(AbstractionMmu *mmu, uint32_t *vaddr, uint32_t *paddr);
|
||||
};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ttb_vbase;
|
||||
uint32_t ttb_pbase;
|
||||
|
||||
uint32_t vaddr_start;
|
||||
uint32_t vaddr_end;
|
||||
uint32_t paddr_start;
|
||||
uint32_t paddr_end;
|
||||
|
||||
uint32_t vpaddr_offset;
|
||||
|
||||
uint32_t pte_attr;
|
||||
uint32_t mmu_status;
|
||||
|
||||
MmuMemoryType mmu_memory_type;
|
||||
MmuAccess mmu_access;
|
||||
MmuShareability mmu_shareability;
|
||||
|
||||
struct AbstractionMmuDone *mmu_done;
|
||||
|
||||
int lock;
|
||||
int link_list;
|
||||
}AbstractionMmu;
|
||||
|
|
@ -1,215 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file: isr.c
|
||||
* @brief: the general management of system isr
|
||||
* @version: 1.0
|
||||
* @author: AIIT XUOS Lab
|
||||
* @date: 2020/3/15
|
||||
*
|
||||
*/
|
||||
#include <string.h>
|
||||
#include "isr.h"
|
||||
|
||||
struct InterruptServiceRoutines isrManager = {0} ;
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
extern int GetCpuId(void);
|
||||
#endif
|
||||
/**
|
||||
* This functionwill get the isr nest level.
|
||||
*
|
||||
* @return isr nest level
|
||||
*/
|
||||
static uint16_t GetIsrCounter()
|
||||
{
|
||||
uint16_t ret = 0;
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
ret = isrManager.isr_count[GetCpuId()];
|
||||
#else
|
||||
ret = isrManager.isr_count;
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void IncIsrCounter()
|
||||
{
|
||||
#ifdef ARCH_SMP
|
||||
isrManager.isr_count[GetCpuId()] ++ ;
|
||||
#else
|
||||
isrManager.isr_count ++;
|
||||
#endif
|
||||
return ;
|
||||
}
|
||||
|
||||
static void DecIsrCounter()
|
||||
{
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
isrManager.isr_count[GetCpuId()] -- ;
|
||||
#else
|
||||
isrManager.isr_count --;
|
||||
#endif
|
||||
return ;
|
||||
}
|
||||
|
||||
bool IsInIsr()
|
||||
{
|
||||
#ifdef ARCH_SMP
|
||||
return ( isrManager.isr_count[GetCpuId()] != 0 ? TRUE : FALSE ) ;
|
||||
#else
|
||||
return ( isrManager.isr_count != 0 ? TRUE : FALSE ) ;
|
||||
#endif
|
||||
|
||||
}
|
||||
/**
|
||||
* This function will register a new irq.
|
||||
*
|
||||
* @param irq_num the number of the irq
|
||||
* @param handler the callback of the interrupt
|
||||
* @param arg param of thge callback
|
||||
*
|
||||
* @return 0 on success; -1 on failure
|
||||
*/
|
||||
static int32_t RegisterHwIrq(uint32_t irq_num, IsrHandlerType handler, void *arg)
|
||||
{
|
||||
if (irq_num >= ARCH_MAX_IRQ_NUM )
|
||||
return -1;
|
||||
|
||||
struct IrqDesc *desc = &isrManager.irq_table[irq_num];
|
||||
|
||||
desc->handler = handler;
|
||||
desc->param = arg;
|
||||
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* This function will free a irq.
|
||||
*
|
||||
* @param irq_num the number of the irq
|
||||
*
|
||||
* @return 0 on success; -1 on failure
|
||||
*/
|
||||
static int32_t FreeHwIrq(uint32_t irq_num)
|
||||
{
|
||||
if (irq_num >= ARCH_MAX_IRQ_NUM )
|
||||
return -1;
|
||||
|
||||
memset(&isrManager.irq_table[irq_num], 0, sizeof(struct IrqDesc));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will enable a irq.
|
||||
*
|
||||
* @param irq_num the number of the irq
|
||||
*
|
||||
* @return 0 on success; -1 on failure
|
||||
*/
|
||||
static int32_t EnableHwIrq(uint32_t irq_num, uint32_t cpu_id)
|
||||
{
|
||||
if (irq_num >= ARCH_MAX_IRQ_NUM )
|
||||
return -1;
|
||||
|
||||
return ArchEnableHwIrq(irq_num, cpu_id);
|
||||
}
|
||||
/**
|
||||
* This function will disable a irq.
|
||||
*
|
||||
* @param irq_num the number of the irq
|
||||
*
|
||||
* @return 0 on success; -1 on failure
|
||||
*/
|
||||
|
||||
static int32_t DisableHwIrq(uint32_t irq_num, uint32_t cpu_id)
|
||||
{
|
||||
if (irq_num >= ARCH_MAX_IRQ_NUM )
|
||||
return -1;
|
||||
|
||||
return ArchDisableHwIrq(irq_num, cpu_id);
|
||||
}
|
||||
|
||||
/* called from arch-specific ISR wrapper */
|
||||
static void IsrCommon(uint32_t irq_num)
|
||||
{
|
||||
struct IrqDesc *desc = &isrManager.irq_table[irq_num];
|
||||
|
||||
if (desc->handler == NULL) {
|
||||
// SYS_KDEBUG_LOG(KDBG_IRQ, ("Spurious interrupt: IRQ No. %d\n", irq_num));
|
||||
while (1) {}
|
||||
}
|
||||
desc->handler(irq_num, desc->param);
|
||||
|
||||
}
|
||||
|
||||
static void SetIsrSwitchTrigerFlag()
|
||||
{
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
isrManager.isr_switch_trigger_flag[GetCpuId()] = 1;
|
||||
#else
|
||||
isrManager.isr_switch_trigger_flag = 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void ClearIsrSwitchTrigerFlag()
|
||||
{
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
isrManager.isr_switch_trigger_flag[GetCpuId()] = 0;
|
||||
#else
|
||||
isrManager.isr_switch_trigger_flag = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static uint8_t GetIsrSwitchTrigerFlag()
|
||||
{
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
return isrManager.isr_switch_trigger_flag[GetCpuId()];
|
||||
#else
|
||||
return isrManager.isr_switch_trigger_flag ;
|
||||
#endif
|
||||
}
|
||||
|
||||
struct IsrDone isrDone = {
|
||||
IsInIsr,
|
||||
RegisterHwIrq ,
|
||||
FreeHwIrq,
|
||||
EnableHwIrq,
|
||||
DisableHwIrq,
|
||||
IsrCommon,
|
||||
GetIsrCounter,
|
||||
IncIsrCounter,
|
||||
DecIsrCounter,
|
||||
GetIsrSwitchTrigerFlag,
|
||||
SetIsrSwitchTrigerFlag,
|
||||
ClearIsrSwitchTrigerFlag
|
||||
};
|
||||
|
||||
void SysInitIsrManager()
|
||||
{
|
||||
extern int __isrtbl_idx_start;
|
||||
extern int __isrtbl_start;
|
||||
extern int __isrtbl_end;
|
||||
memset(&isrManager,0,sizeof(struct InterruptServiceRoutines));
|
||||
isrManager.done = &isrDone;
|
||||
|
||||
uint32_t *index = (uint32_t *)&__isrtbl_idx_start;
|
||||
struct IrqDesc *desc = (struct IrqDesc *)&__isrtbl_start;
|
||||
|
||||
while (desc != (struct IrqDesc *)&__isrtbl_end)
|
||||
isrManager.irq_table[*index++] = *desc++;
|
||||
}
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file: isr.h
|
||||
* @brief: function declaration and structure defintion of isr
|
||||
* @version: 1.0
|
||||
* @author: AIIT XUOS Lab
|
||||
* @date: 2020/3/10
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ISR_H__
|
||||
#define __ISR_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <arch_interrupt.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define DECLARE_HW_IRQ(_irq_num, _handler, _arg) \
|
||||
const uint32_t __irq_desc_idx_##_handler SECTION(".isrtbl.idx") = _irq_num + ARCH_IRQ_NUM_OFFSET ; \
|
||||
const struct IrqDesc __irq_desc_##_handler SECTION(".isrtbl") = { \
|
||||
.handler = _handler, \
|
||||
.param = _arg, \
|
||||
}
|
||||
|
||||
typedef void (*IsrHandlerType)(int vector, void *param);
|
||||
|
||||
struct IrqDesc
|
||||
{
|
||||
IsrHandlerType handler;
|
||||
void *param;
|
||||
|
||||
#ifdef CONFIG_INTERRUPT_INFO
|
||||
char name[NAME_NUM_MAX];
|
||||
uint32_t counter;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct IsrDone
|
||||
{
|
||||
bool (*isInIsr)();
|
||||
int32_t (*registerIrq)(uint32_t irq_num, IsrHandlerType handler, void *arg);
|
||||
int32_t (*freeIrq)(uint32_t irq_num);
|
||||
int32_t (*enableIrq)(uint32_t irq_num, uint32_t cpu_id);
|
||||
int32_t (*disableIrq)(uint32_t irq_num, uint32_t cpu_id);
|
||||
void (*handleIrq)(uint32_t irq_num);
|
||||
uint16_t (*getCounter)() ;
|
||||
void (*incCounter)();
|
||||
void (*decCounter)();
|
||||
uint8_t (*getSwitchTrigerFlag)();
|
||||
void (*setSwitchTrigerFlag)();
|
||||
void (*clearSwitchTrigerFlag)();
|
||||
};
|
||||
|
||||
struct InterruptServiceRoutines {
|
||||
|
||||
#ifdef ARCH_SMP
|
||||
volatile uint16_t isr_count[CPU_NUMBERS];
|
||||
volatile uint8_t isr_switch_trigger_flag[CPU_NUMBERS];
|
||||
#else
|
||||
volatile uint16_t isr_count ;
|
||||
volatile uint8_t isr_switch_trigger_flag;
|
||||
#endif
|
||||
struct IrqDesc irq_table[ARCH_MAX_IRQ_NUM];
|
||||
struct IsrDone *done;
|
||||
};
|
||||
|
||||
extern struct InterruptServiceRoutines isrManager ;
|
||||
|
||||
uint32_t DisableLocalInterrupt();
|
||||
void EnableLocalInterrupt(unsigned long level);
|
||||
|
||||
#define DISABLE_INTERRUPT DisableLocalInterrupt
|
||||
#define ENABLE_INTERRUPT EnableLocalInterrupt
|
||||
|
||||
void SysInitIsrManager();
|
||||
void InitHwinterrupt(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
SRC_DIR := $(ARCH)
|
||||
SRC_DIR := arm
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# The following three platforms support compatiable instructions.
|
||||
SRC_DIR := $(ARCH_ARMV)
|
||||
SRC_DIR := armv7-a
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -1,8 +1,4 @@
|
|||
# The following three platforms support compatiable instructions.
|
||||
|
||||
ifeq ($(CONFIG_BOARD_IMX6Q_SABRELITE_EVB),y)
|
||||
SRC_DIR := cortex-a9
|
||||
endif
|
||||
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -1,66 +0,0 @@
|
|||
.section .vectors, "ax"
|
||||
.code 32
|
||||
|
||||
.globl ExceptionVectors
|
||||
ExceptionVectors:
|
||||
ldr pc, _ResetException
|
||||
ldr pc, _UndefInstrException
|
||||
ldr pc, _SwiException
|
||||
ldr pc, _PrefetchAbortException
|
||||
ldr pc, _DataAbortAbortException
|
||||
ldr pc, _ResvException
|
||||
ldr pc, _IrqException
|
||||
ldr pc, _FiqException
|
||||
|
||||
.globl Reset_Handler
|
||||
.globl UndefInstrExceptionHandle
|
||||
.globl SwiExceptionHandle
|
||||
.globl PrefetchAbortExceptionHandle
|
||||
.globl DataAbortExceptionHandle
|
||||
.globl ResvExceptionHandle
|
||||
.globl ExceptionIsrEntry
|
||||
.globl FiqExceptionHandle
|
||||
|
||||
_ResetException:
|
||||
.word Reset_Handler
|
||||
_UndefInstrException:
|
||||
.word UndefInstrExceptionHandle
|
||||
_SwiException:
|
||||
.word SwiExceptionHandle
|
||||
_PrefetchAbortException:
|
||||
.word PrefetchAbortExceptionHandle
|
||||
_DataAbortAbortException:
|
||||
.word DataAbortExceptionHandle
|
||||
_ResvException:
|
||||
.word ResvExceptionHandle
|
||||
_IrqException:
|
||||
.word ExceptionIsrEntry
|
||||
_FiqException:
|
||||
.word FiqExceptionHandle
|
||||
|
||||
.globl _start
|
||||
Reset_Handler:
|
||||
b _start
|
||||
|
||||
UndefInstrExceptionHandle:
|
||||
b UndefInstrIsrEntry
|
||||
|
||||
SwiExceptionHandle:
|
||||
b SvcIsrEntry
|
||||
|
||||
PrefetchAbortExceptionHandle:
|
||||
b PrefetchAbortIsrEntry
|
||||
|
||||
DataAbortExceptionHandle:
|
||||
b UndefInstrIsrEntry
|
||||
|
||||
ResvExceptionHandle:
|
||||
b DataAbortIsrEntry
|
||||
|
||||
ExceptionIsrEntry:
|
||||
stmfd sp!, {r0-r12,lr}
|
||||
|
||||
bl IsrEntry
|
||||
|
||||
FiqExceptionHandle:
|
||||
b FiqIsrEntry
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
SRC_FILES := boot.S cache.S exception.S cortexA9.S gic.c interrupt.c mmu.c ccm_pll.c
|
||||
SRC_DIR:= imx6q
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -1,54 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
#ifndef ARCH_INTERRUPT_H__
|
||||
#define ARCH_INTERRUPT_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <board.h>
|
||||
#include "gic.h"
|
||||
|
||||
#define ARCH_MAX_IRQ_NUM PLATFORM_MAX_IRQ_NR
|
||||
|
||||
int32_t ArchEnableHwIrq(uint32_t irq_num, uint32_t cpu_id);
|
||||
int32_t ArchDisableHwIrq(uint32_t irq_num, uint32_t cpu_id);
|
||||
|
||||
//! @brief
|
||||
typedef enum {
|
||||
CPU_0,
|
||||
CPU_1,
|
||||
CPU_2,
|
||||
CPU_3,
|
||||
} cpuid_e;
|
||||
|
||||
struct ExceptionStackRegister
|
||||
{
|
||||
uint32_t r0;
|
||||
uint32_t r1;
|
||||
uint32_t r2;
|
||||
uint32_t r3;
|
||||
uint32_t r4;
|
||||
uint32_t r5;
|
||||
uint32_t r6;
|
||||
uint32_t r7;
|
||||
uint32_t r8;
|
||||
uint32_t r9;
|
||||
uint32_t r10;
|
||||
uint32_t r11;
|
||||
uint32_t r12;
|
||||
uint32_t r13_sp;
|
||||
uint32_t r14_lr;
|
||||
uint32_t r15_pc;
|
||||
uint32_t cpsr;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
#include <asm_defines.h>
|
||||
|
||||
.global ExceptionVectors
|
||||
|
||||
.section ".startup","ax"
|
||||
.globl _reset
|
||||
.extern init
|
||||
_reset:
|
||||
|
||||
/* set the cpu to SVC32 mode and disable interrupt */
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #0x1f
|
||||
orr r0, r0, #0x13
|
||||
msr cpsr_c, r0
|
||||
|
||||
/* disable i/d cache mmu*/
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, #(1 << 12) /* i cache */
|
||||
bic r0, #(1 << 2) /* d cache */
|
||||
bic r0, #(1 << 0) /* mmu */
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
ldr r0, =stack_top
|
||||
|
||||
@ get cpu id, and subtract the offset from the stacks base address
|
||||
mrc p15,0,r2,c0,c0,5 @ read multiprocessor affinity register
|
||||
and r2, r2, #3 @ mask off, leaving CPU ID field
|
||||
mov r5, r2 @ save cpu id for later
|
||||
|
||||
@ Set the startup stack for svc
|
||||
mov sp, r0
|
||||
|
||||
@ Enter Undefined Instruction Mode and set its Stack Pointer
|
||||
msr cpsr_c, #MODE_UND|I_BIT|F_BIT
|
||||
mov sp, r0
|
||||
sub r0, r0, #EXCEPTION_STACK_SIZE
|
||||
|
||||
@ Enter Abort Mode and set its Stack Pointer
|
||||
msr cpsr_c, #MODE_ABT|I_BIT|F_BIT
|
||||
mov sp, r0
|
||||
sub r0, r0, #EXCEPTION_STACK_SIZE
|
||||
|
||||
@ Enter FIQ Mode and set its Stack Pointer
|
||||
msr cpsr_c, #MODE_FIQ|I_BIT|F_BIT
|
||||
mov sp, r0
|
||||
sub r0, r0, #EXCEPTION_STACK_SIZE
|
||||
|
||||
@ Enter IRQ Mode and set its Stack Pointer
|
||||
msr cpsr_c, #MODE_IRQ|I_BIT|F_BIT
|
||||
mov sp, r0
|
||||
sub r0, r0, #EXCEPTION_STACK_SIZE
|
||||
|
||||
/* come back to SVC mode */
|
||||
msr cpsr_c, #MODE_SVC|I_BIT|F_BIT
|
||||
|
||||
/*
|
||||
* copy the vector table into the RAM vectors
|
||||
* this assumes that the RAM vectors size is divisible by 3 words (12 bytes)
|
||||
*/
|
||||
ldr r1,=__ram_vectors_start
|
||||
ldr r2,=__ram_vectors_end
|
||||
ldr r3,=ExceptionVectors
|
||||
1: cmp r1,r2
|
||||
ldmlt r3!,{r4,r5,r6}
|
||||
stmlt r1!,{r4,r5,r6}
|
||||
blt 1b
|
||||
|
||||
/* clear .bss */
|
||||
mov r0, #0 /* get a zero */
|
||||
ldr r1,=__bss_start /* bss start */
|
||||
ldr r2,=__bss_end /* bss end */
|
||||
|
||||
bss_loop:
|
||||
cmp r1,r2 /* check if data to clear */
|
||||
strlo r0,[r1],#4 /* clear 4 bytes */
|
||||
blo bss_loop /* loop until done */
|
||||
|
||||
/* call C++ constructors of global objects */
|
||||
ldr r0, =__ctors_start__
|
||||
ldr r1, =__ctors_end__
|
||||
bss_end:
|
||||
|
||||
ctor_loop:
|
||||
cmp r0, r1
|
||||
beq ctor_end
|
||||
ldr r2, [r0], #4
|
||||
stmfd sp!, {r0-r1}
|
||||
mov lr, pc
|
||||
bx r2
|
||||
ldmfd sp!, {r0-r1}
|
||||
b ctor_loop
|
||||
ctor_end:
|
||||
|
||||
bl init
|
||||
|
||||
_loop_here:
|
||||
b _loop_here
|
||||
|
|
@ -1,145 +0,0 @@
|
|||
#include <asm_defines.h>
|
||||
|
||||
.section .text.vectors, "ax"
|
||||
.code 32
|
||||
|
||||
.globl ExceptionVectors
|
||||
ExceptionVectors:
|
||||
ldr pc, _ResetException
|
||||
ldr pc, _UndefInstrException
|
||||
ldr pc, _SwiException
|
||||
ldr pc, _PrefetchAbortException
|
||||
ldr pc, _DataAbortAbortException
|
||||
ldr pc, _ResvException
|
||||
ldr pc, _IrqException
|
||||
ldr pc, _FiqException
|
||||
|
||||
.globl _reset
|
||||
.globl UndefInstrExceptionHandle
|
||||
.globl SwiExceptionHandle
|
||||
.globl PrefetchAbortExceptionHandle
|
||||
.globl DataAbortExceptionHandle
|
||||
.globl ResvExceptionHandle
|
||||
.globl ExceptionIsrEntry
|
||||
.globl FiqExceptionHandle
|
||||
|
||||
_ResetException:
|
||||
.word _reset
|
||||
_UndefInstrException:
|
||||
.word UndefInstrExceptionHandle
|
||||
_SwiException:
|
||||
.word SwiExceptionHandle
|
||||
_PrefetchAbortException:
|
||||
.word PrefetchAbortExceptionHandle
|
||||
_DataAbortAbortException:
|
||||
.word DataAbortExceptionHandle
|
||||
_ResvException:
|
||||
.word ResvExceptionHandle
|
||||
_IrqException:
|
||||
.word ExceptionIsrEntry
|
||||
_FiqException:
|
||||
.word FiqExceptionHandle
|
||||
|
||||
.word 0 // extra word in RAM vectors
|
||||
|
||||
|
||||
.macro push_svc_reg
|
||||
sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */
|
||||
stmia sp, {r0 - r12} @/* Calling r0-r12 */
|
||||
mov r0, sp
|
||||
mrs r6, spsr @/* Save CPSR */
|
||||
str lr, [r0, #15*4] @/* Push PC */
|
||||
str r6, [r0, #16*4] @/* Push CPSR */
|
||||
cps #MODE_SVC
|
||||
str sp, [r0, #13*4] @/* Save calling SP */
|
||||
str lr, [r0, #14*4] @/* Save calling PC */
|
||||
.endm
|
||||
|
||||
.align 5
|
||||
.globl UndefInstrExceptionHandle
|
||||
UndefInstrExceptionHandle:
|
||||
1:
|
||||
b 1b
|
||||
|
||||
.align 5
|
||||
.globl SwiExceptionHandle
|
||||
SwiExceptionHandle:
|
||||
push_svc_reg
|
||||
bl DoSvcCallProcess
|
||||
b .
|
||||
|
||||
.align 5
|
||||
.globl PrefetchAbortExceptionHandle
|
||||
PrefetchAbortExceptionHandle:
|
||||
1:
|
||||
b 1b
|
||||
|
||||
.align 5
|
||||
.globl DataAbortExceptionHandle
|
||||
DataAbortExceptionHandle:
|
||||
1:
|
||||
b 1b
|
||||
|
||||
.align 5
|
||||
.globl ResvExceptionHandle
|
||||
ResvExceptionHandle:
|
||||
1:
|
||||
b 1b
|
||||
|
||||
.section .text.isr, "ax"
|
||||
.align 5
|
||||
.globl ExceptionIsrEntry
|
||||
ExceptionIsrEntry:
|
||||
|
||||
stmfd sp!, {r0-r12,lr}
|
||||
|
||||
bl DoIrqProcess
|
||||
|
||||
@ ldr r0, =rt_thread_switch_interrupt_flag
|
||||
@ ldr r1, [r0]
|
||||
@ cmp r1, #1
|
||||
@ beq rt_hw_context_switch_interrupt_do
|
||||
|
||||
ldmfd sp!, {r0-r12,lr}
|
||||
subs pc, lr, #4
|
||||
|
||||
@ rt_hw_context_switch_interrupt_do:
|
||||
@ mov r1, #0 @ clear flag
|
||||
@ str r1, [r0]
|
||||
|
||||
@ mov r1, sp @ r1 point to {r0-r3} in stack
|
||||
@ add sp, sp, #4*4
|
||||
@ ldmfd sp!, {r4-r12,lr}@ reload saved registers
|
||||
@ mrs r0, spsr @ get cpsr of interrupt thread
|
||||
@ sub r2, lr, #4 @ save old task's pc to r2
|
||||
|
||||
@ @ Switch to SVC mode with no interrupt. If the usr mode guest is
|
||||
@ @ interrupted, this will just switch to the stack of kernel space.
|
||||
@ @ save the registers in kernel space won't trigger data abort.
|
||||
@ msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
|
||||
|
||||
@ stmfd sp!, {r2} @ push old task's pc
|
||||
@ stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4
|
||||
@ ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread
|
||||
@ stmfd sp!, {r1-r4} @ push old task's r0-r3
|
||||
@ stmfd sp!, {r0} @ push old task's cpsr
|
||||
|
||||
@ ldr r4, =rt_interrupt_from_thread
|
||||
@ ldr r5, [r4]
|
||||
@ str sp, [r5] @ store sp in preempted tasks's TCB
|
||||
|
||||
@ ldr r6, =rt_interrupt_to_thread
|
||||
@ ldr r6, [r6]
|
||||
@ ldr sp, [r6] @ get new task's stack pointer
|
||||
|
||||
@ ldmfd sp!, {r4} @ pop new task's cpsr to spsr
|
||||
@ msr spsr_cxsf, r4
|
||||
|
||||
@ ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
|
||||
|
||||
|
||||
.align 5
|
||||
.globl FiqExceptionHandle
|
||||
FiqExceptionHandle:
|
||||
1:
|
||||
b 1b
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
SRC_FILES := schedule.c ipc.c
|
||||
SRC_DIR:=
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -2,7 +2,7 @@ export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
|||
export DEVICE = -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp
|
||||
export CFLAGS := $(DEVICE) -Wall -O0 -g -gdwarf-2
|
||||
export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
|
||||
export LFLAGS := $(DEVICE) -Wl,--gc-sections,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,ExceptionVectors -T $(BSP_ROOT)/link.lds
|
||||
export LFLAGS := $(DEVICE) -Wl,--gc-sections,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q/imx6q_boot.lds
|
||||
export CXXFLAGS :=
|
||||
|
||||
ifeq ($(CONFIG_LIB_MUSLLIB), y)
|
||||
|
|
@ -11,10 +11,6 @@ export LIBCC := -lgcc
|
|||
export LINK_MUSLLIB := $(KERNEL_ROOT)/lib/musllib/libmusl.a
|
||||
endif
|
||||
|
||||
# ifeq ($(CONFIG_RESOURCES_LWIP), y)
|
||||
# export LINK_LWIP := $(KERNEL_ROOT)/resources/ethernet/LwIP/liblwip.a
|
||||
# endif
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H -DCHIP_MX6DQ
|
||||
|
||||
export USING_NEWLIB =1
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file imx6q_boot.lds
|
||||
* @brief imx6q boot lds function
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.08.25
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm") /*binary file format*/
|
||||
OUTPUT_ARCH(arm) /*arch target*/
|
||||
ENTRY(_vector_jumper) /*entry address pointer*/
|
||||
|
||||
/* mx6dq has 256kB of OCRAM
|
||||
* +-------------------+ 0x0093FFFF
|
||||
* | RAM Vector |
|
||||
* +-------------------+ 0x0093FFB8
|
||||
* | Stack |
|
||||
* | 8KB |
|
||||
* +-------------------+ 0x0093E000
|
||||
* | MMU Table |
|
||||
* | 24KB |
|
||||
* +-------------------+ 0x00938000
|
||||
* | |
|
||||
* | Free Area |
|
||||
* | 195KB |
|
||||
* | |
|
||||
* +-------------------+ 0x00907400
|
||||
* | DCD Table |
|
||||
* | 1KB |
|
||||
* +-------------------+ 0x00907000
|
||||
* | Reserved |
|
||||
* | 28KB |
|
||||
* +-------------------+ 0x00900000
|
||||
*/
|
||||
/*
|
||||
#define OCRAM_ORG 0x00907400
|
||||
#define OCRAM_FREE_SIZE 196K*/
|
||||
|
||||
/*
|
||||
* External DDR CHIP_MX6DQ/CHIP_MX6SDL start 0x10000000, CHIP_MX6SL start 0x80000000
|
||||
*/
|
||||
/*
|
||||
#define DDR_ORG 0x10000000
|
||||
#define DDR_LEN 2048M*/
|
||||
|
||||
BOOT_STACK_SIZE = 0x1000;
|
||||
RAM_VECTORS_SIZE = 72;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
ocram (rwx) : ORIGIN = 0x00900000, LENGTH = 256K
|
||||
ddr3 (rwx) : ORIGIN = 0x27800000, LENGTH = 648M
|
||||
virt_ddr3 (WRX) : ORIGIN = 0x800A0000, LENGTH = 648M
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(ddr3);
|
||||
. = ALIGN(4);
|
||||
|
||||
_start_image_add = .;
|
||||
|
||||
.ivt :
|
||||
{
|
||||
. = . + 0x400;
|
||||
KEEP(*(.ivt))
|
||||
} > ddr3
|
||||
|
||||
.boot_data :
|
||||
{
|
||||
__start_boot_data = .;
|
||||
KEEP(*(.boot_data))
|
||||
} > ddr3
|
||||
|
||||
/* aligned to ease the hexdump read of generated binary */
|
||||
.dcd_hdr : ALIGN(16)
|
||||
{
|
||||
KEEP(*(.dcd_hdr))
|
||||
} > ddr3
|
||||
|
||||
.dcd_wrt_cmd :
|
||||
{
|
||||
KEEP(*(.dcd_wrt_cmd))
|
||||
} > ddr3
|
||||
|
||||
.dcd_data :
|
||||
{
|
||||
KEEP(*(.dcd_data))
|
||||
} > ddr3
|
||||
|
||||
.start_sec : {
|
||||
. = ALIGN(4);
|
||||
|
||||
/* read only area. */
|
||||
start_boot.o(.text)
|
||||
boot.o(.text .text.*)
|
||||
pager.o(.text .text.*)
|
||||
mmu.o(.text .text.*)
|
||||
bootdriver.o(.text .text.*)
|
||||
lowlevel_init.o(.text .text.*)
|
||||
|
||||
start_boot.o(.rodata .rodata.*)
|
||||
boot.o(.rodata .rodata.*)
|
||||
pager.o(.rodata .rodata.*)
|
||||
mmu.o(.rodata .rodata.*)
|
||||
bootdriver.o(.rodata .rodata.*)
|
||||
lowlevel_init.o(.rodata .rodata.*)
|
||||
|
||||
/* already initialized to zero. */
|
||||
start_boot.o(.data .data.*)
|
||||
boot.o(.data .data.*)
|
||||
pager.o(.data .data.*)
|
||||
mmu.o(.data .data.*)
|
||||
bootdriver.o(.data .data.*)
|
||||
lowlevel_init.o(.data .data.*)
|
||||
|
||||
/* initialization start checkpoint. */
|
||||
PROVIDE(boot_start_addr = .);
|
||||
|
||||
start_boot.o(.bss .bss.* COMMON)
|
||||
boot.o(.bss .bss.* COMMON)
|
||||
pager.o(.bss .bss.* COMMON)
|
||||
mmu.o(.bss .bss.* COMMON)
|
||||
bootdriver.o(.bss .bss.* COMMON)
|
||||
lowlevel_init.o(.bss .bss.* COMMON)
|
||||
|
||||
/* DEVBASE Coarse Page Tables (num: 2, 0x400 unit) */
|
||||
. = ALIGN(0x400);
|
||||
PROVIDE(_dev_pte = .);
|
||||
. += 0xC000;
|
||||
|
||||
/* DRAM Coarse Page Tables (num: 128, 0x400 unit) */
|
||||
. = ALIGN(0x400);
|
||||
PROVIDE(_pte = .);
|
||||
. += 0x80000;
|
||||
|
||||
/* stack for booting code. */
|
||||
. = ALIGN(0x1000);
|
||||
. += BOOT_STACK_SIZE;
|
||||
PROVIDE(svc_stack = .);
|
||||
|
||||
/* Kernel page table. 16K */
|
||||
. = ALIGN(0x4000);
|
||||
PROVIDE(_kt = .);
|
||||
. += 0x4000;
|
||||
|
||||
/* User page table. 16K */
|
||||
PROVIDE(_ut = .);
|
||||
. += 0x4000;
|
||||
|
||||
/* initialization end checkpoint. */
|
||||
PROVIDE(boot_end_addr = .);
|
||||
} > ddr3
|
||||
|
||||
/* Other Kernel code is placed over 0x80000000 + 128KB. */
|
||||
.text : AT(0x278A0000) {
|
||||
*(.vectors)
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
} > virt_ddr3
|
||||
|
||||
. = ALIGN(0x1000);
|
||||
/* Other Kernel code text checkpoint. */
|
||||
PROVIDE(kern_text = .);
|
||||
|
||||
.data : {
|
||||
*(.data .data.*)
|
||||
PROVIDE(_binary_initcode_start = .);
|
||||
*(.rawdata_initcode*)
|
||||
PROVIDE(_binary_initcode_end = .);
|
||||
PROVIDE(_binary_fs_img_start = .);
|
||||
*(.rawdata_fs_img*)
|
||||
PROVIDE(_binary_fs_img_end = .);
|
||||
} > virt_ddr3
|
||||
|
||||
PROVIDE(kern_data = .);
|
||||
|
||||
_image_size = . - 0x80000000;
|
||||
|
||||
.bss : {
|
||||
*(.bss .bss.* COMMON)
|
||||
} > virt_ddr3
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(kern_end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
#pragma once
|
||||
|
||||
// Interrupt control bits
|
||||
#define NO_INT 0xc0 // disable IRQ.
|
||||
#define DIS_INT 0x80 // disable both IRQ and FIQ.
|
||||
|
||||
// ARM modes.
|
||||
#define MODE_MASK 0x1f
|
||||
#define USR_MODE 0x10
|
||||
#define FIQ_MODE 0x11
|
||||
#define IRQ_MODE 0x12
|
||||
#define SVC_MODE 0x13
|
||||
#define ABT_MODE 0x17
|
||||
#define UND_MODE 0x1b
|
||||
#define SYS_MODE 0x1f
|
||||
|
||||
// vector table
|
||||
#define TRAP_RESET 0
|
||||
#define TRAP_UND 1
|
||||
#define TRAP_SWI 2
|
||||
#define TRAP_IABT 3
|
||||
#define TRAP_DABT 4
|
||||
#define TRAP_NA 5
|
||||
#define TRAP_IRQ 6
|
||||
#define TRAP_FIQ 7
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include "memlayout.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define NR_CPU 4
|
||||
|
||||
#define DMB() __asm__ __volatile__("dmb" ::: "memory")
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t spsr_usr()
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"mrs %0, cpsr"
|
||||
: "=r"(val)
|
||||
:
|
||||
:);
|
||||
val &= ~DIS_INT;
|
||||
val &= ~MODE_MASK;
|
||||
val |= USR_MODE;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline int is_int()
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"mrs %0, cpsr"
|
||||
: "=r"(val)
|
||||
:
|
||||
:);
|
||||
|
||||
return !(val & DIS_INT);
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void flush_tlb(void)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(val) :);
|
||||
|
||||
// invalid entire data and instruction cache
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 0" : : "r"(val) :);
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c7, c11, 0" : : "r"(val) :);
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t ldrex(volatile uint32_t* addr)
|
||||
{
|
||||
// Load link.
|
||||
uint32_t res;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"ldrex %0, [%1]\n"
|
||||
: "=&r"(res)
|
||||
: "r"(addr)
|
||||
: "memory", "cc");
|
||||
return res;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t strex(volatile uint32_t* addr, uint32_t newval)
|
||||
{
|
||||
// Load link.
|
||||
uint32_t res;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" strex %0, %1, [%2]\n"
|
||||
: "=&r"(res)
|
||||
: "r"(newval), "r"(addr)
|
||||
: "memory", "cc");
|
||||
return res;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t xchg(volatile uint32_t* addr, uint32_t newval)
|
||||
{
|
||||
// reference:
|
||||
// https://github.com/torvalds/linux/blob/master/arch/arm/include/asm/atomic.h
|
||||
// https://github.com/torvalds/linux/blob/master/arch/arm/include/asm/cmpxchg.h
|
||||
uint32_t res, tmp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1: ldrex %0, [%3]\n"
|
||||
" strex %1, %2, [%3]\n"
|
||||
" cmp %1, #0\n"
|
||||
" bne 1b"
|
||||
: "=&r"(res), "=&r"(tmp)
|
||||
: "r"(newval), "r"(addr)
|
||||
: "memory", "cc");
|
||||
return res;
|
||||
}
|
||||
|
||||
struct context {
|
||||
uint32_t r4;
|
||||
uint32_t r5;
|
||||
uint32_t r6;
|
||||
uint32_t r7;
|
||||
uint32_t r8;
|
||||
uint32_t r9;
|
||||
uint32_t r10;
|
||||
uint32_t r11;
|
||||
uint32_t r12;
|
||||
uint32_t lr;
|
||||
};
|
||||
|
||||
struct trapframe {
|
||||
uint32_t sp_usr; // user mode sp
|
||||
uint32_t lr_usr; // user mode lr
|
||||
uint32_t r14_svc; // r14_svc (r14_svc == pc if SWI)
|
||||
uint32_t spsr;
|
||||
uint32_t r0;
|
||||
uint32_t r1;
|
||||
uint32_t r2;
|
||||
uint32_t r3;
|
||||
uint32_t r4;
|
||||
uint32_t r5;
|
||||
uint32_t r6;
|
||||
uint32_t r7;
|
||||
uint32_t r8;
|
||||
uint32_t r9;
|
||||
uint32_t r10;
|
||||
uint32_t r11;
|
||||
uint32_t r12;
|
||||
uint32_t pc; // (lr on entry) instruction to resume execution
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -31,7 +31,8 @@
|
|||
#ifndef _CCM_PLL_H_
|
||||
#define _CCM_PLL_H_
|
||||
|
||||
#include "sdk_types.h"
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
//! @addtogroup diag_clocks
|
||||
//! @{
|
||||
|
|
@ -40,15 +41,14 @@
|
|||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define CLK_SRC_32K 32768
|
||||
#define CLK_SRC_32K 32768
|
||||
|
||||
//! @brief Create a clock gate bit mask value.
|
||||
//! @param x 0..15, for CG0 to CG15
|
||||
#define CG(x) (3 << (x*2))
|
||||
#define CG(x) (3 << (x * 2))
|
||||
|
||||
//! @brief Constants for CCM CCGR register fields.
|
||||
enum _clock_gate_constants
|
||||
{
|
||||
enum _clock_gate_constants {
|
||||
CLOCK_ON = 0x3, //!< Clock always on in both run and stop modes.
|
||||
CLOCK_ON_RUN = 0x1, //!< Clock on only in run mode.
|
||||
CLOCK_OFF = 0x0 //!< Clocked gated off.
|
||||
|
|
@ -0,0 +1,584 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file crm_regs.h
|
||||
* @brief support imx6q clock control module define, reference from u-boot-2009-08/cpu/arm_cortexa8/mx6/crm_regs.h
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.09.08
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_MX6_CRM_REGS_H__
|
||||
#define __ARCH_ARM_MACH_MX6_CRM_REGS_H__
|
||||
|
||||
#define MXC_CCM_BASE CCM_BASE_ADDR
|
||||
|
||||
/* Register addresses of CCM*/
|
||||
#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
|
||||
#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
|
||||
#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
|
||||
#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
|
||||
#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
|
||||
#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
|
||||
#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
|
||||
#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
|
||||
#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
|
||||
#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
|
||||
#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
|
||||
#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
|
||||
#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
|
||||
#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
|
||||
#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
|
||||
#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
|
||||
#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
|
||||
#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
|
||||
#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
|
||||
#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
|
||||
#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
|
||||
#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
|
||||
#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
|
||||
#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
|
||||
#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
|
||||
#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
|
||||
#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
|
||||
#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
|
||||
#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
|
||||
#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
|
||||
#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
|
||||
#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
|
||||
#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
|
||||
#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x80)
|
||||
#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88)
|
||||
|
||||
/* Define the bits in register CCR */
|
||||
#define MXC_CCM_CCR_RBC_EN (1 << 27)
|
||||
#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
|
||||
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET (21)
|
||||
#define MXC_CCM_CCR_WB_COUNT_MASK (0x7)
|
||||
#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
|
||||
#define MXC_CCM_CCR_COSC_EN (1 << 12)
|
||||
#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
|
||||
#define MXC_CCM_CCR_OSCNT_OFFSET (0)
|
||||
|
||||
/* Define the bits in register CCDR */
|
||||
#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
|
||||
#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
|
||||
|
||||
/* Define the bits in register CSR */
|
||||
#define MXC_CCM_CSR_COSC_READY (1 << 5)
|
||||
#define MXC_CCM_CSR_REF_EN_B (1 << 0)
|
||||
|
||||
/* Define the bits in register CCSR */
|
||||
#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
|
||||
#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
|
||||
#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
|
||||
#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
|
||||
#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
|
||||
#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
|
||||
#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
|
||||
#define MXC_CCM_CCSR_STEP_SEL (1 << 8)
|
||||
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
|
||||
#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
|
||||
#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
|
||||
|
||||
/* Define the bits in register CACRR */
|
||||
#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CBCDR */
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET (27)
|
||||
#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
|
||||
#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
|
||||
#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET (3)
|
||||
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
|
||||
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET (0)
|
||||
|
||||
/* Define the bits in register CBCMR */
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET (29)
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET (26)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET (23)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET (21)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET (18)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
|
||||
#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET (8)
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET (4)
|
||||
#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
|
||||
#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
|
||||
|
||||
/* Define the bits in register CSCMR1 */
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET (29)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET (27)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET (23)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET (20)
|
||||
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
|
||||
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
|
||||
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
|
||||
#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
|
||||
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (10)
|
||||
#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F)
|
||||
/* On SoloLite */
|
||||
#define MXC_CCM_CSCMR1_PERCLK_SEL (1 << 6)
|
||||
|
||||
/* Define the bits in register CSCMR2 */
|
||||
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
|
||||
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19)
|
||||
#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
|
||||
#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
|
||||
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
|
||||
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (2)
|
||||
/* On SoloLite */
|
||||
#define MXC_CCM_CSCMR2_EXTAUDIO_CLK_SEL_MASK (0x3 << 19)
|
||||
#define MXC_CCM_CSCMR2_EXTAUDIO_CLK_SEL_OFFSET 19
|
||||
|
||||
/* Define the bits in register CSCDR1 */
|
||||
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET (25)
|
||||
#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET (22)
|
||||
#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET (11)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
|
||||
/* On Sololite */
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
|
||||
|
||||
/* Define the bits in register CS1CDR */
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25)
|
||||
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
|
||||
/* On SoloLite */
|
||||
#define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PODF_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PODF_OFFSET 25
|
||||
#define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PRED_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PRED_OFFSET 9
|
||||
|
||||
/* Define the bits in register CS2CDR */
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET (21)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET (18)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET (9)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
|
||||
|
||||
/* Define the bits in register CDCDR */
|
||||
#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
|
||||
#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET (29)
|
||||
#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET (20)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (12)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET (7)
|
||||
/* On SoloLite */
|
||||
#define MXC_CCM_CDCDR_MSHC_XMSCKI_PODF_MASK (0x7 << 29)
|
||||
#define MXC_CCM_CDCDR_MSHC_XMSCKI_PODF_OFFSET 29
|
||||
#define MXC_CCM_CDCDR_MSHC_XMSCLI_CLK_SEL (0x1 << 28)
|
||||
|
||||
/* Define the bits in register CHSCCDR */
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET (15)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET (12)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET (9)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET (6)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET (3)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET (0)
|
||||
/* On Sololite */
|
||||
#define MXC_CCM_CHSCCDR_EPDC_AXI_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CHSCCDR_EPDC_AXI_PRE_CLK_SEL_OFFSET 15
|
||||
#define MXC_CCM_CHSCCDR_EPDC_AXI_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_EPDC_AXI_PODF_OFFSET 12
|
||||
#define MXC_CCM_CHSCCDR_EPDC_AXI_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CHSCCDR_EPDC_AXI_CLK_SEL_OFFSET 9
|
||||
#define MXC_CCM_CHSCCDR_PXP_AXI_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CHSCCDR_PXP_AXI_PRE_CLK_SEL_OFFSET 6
|
||||
#define MXC_CCM_CHSCCDR_PXP_AXI_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_PXP_AXI_PODF_OFFSET 3
|
||||
#define MXC_CCM_CHSCCDR_PXP_AXI_CLK_SEL_MASK 0x7
|
||||
#define MXC_CCM_CHSCCDR_PXP_AXI_CLK_SEL_OFFSET 0
|
||||
|
||||
/* Define the bits in register CSCDR2 */
|
||||
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
|
||||
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET (15)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET (12)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET (9)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET (6)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET (3)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK (0x7)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET (0)
|
||||
/* On SoloLite */
|
||||
#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL (0x1 << 18)
|
||||
#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL_OFFSET 15
|
||||
#define MXC_CCM_CSCDR2_EPDC_PIX_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CSCDR2_EPDC_PIX_PODF_OFFSET 12
|
||||
#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_MASK (0X7 << 9)
|
||||
#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_OFFSET 9
|
||||
#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL_OFFSET 6
|
||||
#define MXC_CCM_CSCDR2_LCDIF_PIX_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CSCDR2_LCDIF_PIX_PODF_OFFSET 3
|
||||
#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK 0x7
|
||||
#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 0
|
||||
|
||||
/* Define the bits in register CSCDR3 */
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET (11)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET (9)
|
||||
|
||||
/* Define the bits in register CDHIPR */
|
||||
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
|
||||
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
|
||||
#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
|
||||
#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
|
||||
#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
|
||||
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
|
||||
#define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1)
|
||||
|
||||
/* Define the bits in register CLPCR */
|
||||
#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
|
||||
#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
|
||||
#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
|
||||
#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
|
||||
#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
|
||||
#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
|
||||
#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
|
||||
#define MXC_CCM_CLPCR_VSTBY (1 << 8)
|
||||
#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
|
||||
#define MXC_CCM_CLPCR_SBYOS (1 << 6)
|
||||
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
|
||||
#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
|
||||
#define MXC_CCM_CLPCR_LPM_MASK (0x3)
|
||||
#define MXC_CCM_CLPCR_LPM_OFFSET (0)
|
||||
|
||||
/* Define the bits in register CISR */
|
||||
#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
|
||||
#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
|
||||
#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
|
||||
#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
|
||||
#define MXC_CCM_CISR_COSC_READY (1 << 6)
|
||||
#define MXC_CCM_CISR_LRF_PLL (1)
|
||||
|
||||
/* Define the bits in register CIMR */
|
||||
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
|
||||
#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
|
||||
#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
|
||||
#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL (1)
|
||||
|
||||
/* Define the bits in register CCOSR */
|
||||
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
|
||||
#define MXC_CCM_CCOSR_CLKO2_CLKO1_SEL (0x1 << 8)
|
||||
#define MXC_CCM_CCOSR_CKO1_EN (0x1 << 7)
|
||||
#define MXC_CCM_CCOSR_CKO1_DIV_MASK (0x7 << 4)
|
||||
#define MXC_CCM_CCOSR_CKO1_DIV_OFFSET (4)
|
||||
#define MXC_CCM_CCOSR_CKO1_SEL_MASK (0xF)
|
||||
#define MXC_CCM_CCOSR_CKO1_SEL_OFFSET (0)
|
||||
|
||||
/* Define the bits in registers CGPR */
|
||||
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
|
||||
#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
|
||||
#define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1)
|
||||
/* On SoloLite */
|
||||
#define MXC_CCM_CGPR_MEM_IPG_STOP_MASK (0x1 << 1)
|
||||
|
||||
/* Define the bits in registers CCGRx */
|
||||
#define MXC_CCM_CCGR_CG_MASK 3
|
||||
|
||||
#define MXC_CCM_CCGR0_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
|
||||
#define MXC_CCM_CCGR0_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR0_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR0_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR0_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR0_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR0_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR0_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR0_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR0_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR0_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CCGR0_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CCGR0_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CCGR0_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR0_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CCGR0_CG0_OFFSET 0
|
||||
#define MXC_CCM_CCGR0_CG0_MASK 3
|
||||
|
||||
#define MXC_CCM_CCGR1_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR1_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR1_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR1_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR1_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR1_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR1_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR1_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR1_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR1_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR1_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR1_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR1_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR1_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR1_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR1_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR2_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR2_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR2_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR2_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR2_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR2_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR2_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR2_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR2_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR2_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR2_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR2_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR2_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR2_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR2_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR2_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR3_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR3_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR3_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR3_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR3_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR3_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR3_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR3_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR3_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR3_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR3_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR3_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR3_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR3_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR3_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR3_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR4_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR4_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR4_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR4_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR4_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR4_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR4_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR4_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR4_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR4_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR4_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR4_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR4_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR4_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR4_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR4_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR5_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR5_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR5_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR5_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR5_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR5_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR5_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR5_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR5_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCGR5_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CCGR5_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR5_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR5_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR5_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR5_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR5_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR6_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR6_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR6_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR6_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR6_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR6_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR6_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR6_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR6_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCGR6_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CCGR6_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR6_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR6_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR6_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR6_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR6_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR7_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR7_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR7_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR7_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR7_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR7_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR7_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR7_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR7_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCGR7_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CCGR7_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR7_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR7_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR7_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR7_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR7_CG0_OFFSET 0
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_MX6_CRM_REGS_H__ */
|
||||
|
|
@ -30,7 +30,8 @@
|
|||
#ifndef __GIC_H__
|
||||
#define __GIC_H__
|
||||
|
||||
#include "sdk_types.h"
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
//! @addtogroup gic
|
||||
//! @{
|
||||
|
|
@ -44,15 +45,14 @@
|
|||
//! These options are used for the @a filter_list parameter of the gic_send_sgi()
|
||||
//! function. They control how to select which CPUs that the interrupt is
|
||||
//! sent to.
|
||||
enum _gicd_sgi_filter
|
||||
{
|
||||
enum _gicd_sgi_filter {
|
||||
//! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
|
||||
kGicSgiFilter_UseTargetList = 0,
|
||||
|
||||
|
||||
//! Forward the interrupt to all CPU interfaces except that of the processor that requested
|
||||
//! the interrupt.
|
||||
kGicSgiFilter_AllOtherCPUs = 1,
|
||||
|
||||
|
||||
//! Forward the interrupt only to the CPU interface of the processor that requested the
|
||||
//! interrupt.
|
||||
kGicSgiFilter_OnlyThisCPU = 2
|
||||
|
|
@ -170,7 +170,6 @@ uint32_t gic_read_irq_ack(void);
|
|||
void gic_write_end_of_irq(uint32_t irq_id);
|
||||
//@}
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
@ -27,17 +27,16 @@
|
|||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include "sdk_types.h"
|
||||
#include <stdint.h>
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @brief Offsets to the GIC registers.
|
||||
enum _gic_base_offsets
|
||||
{
|
||||
kGICDBaseOffset = 0x1000, //!< GIC distributor offset.
|
||||
kGICCBaseOffset = 0x100 //!< GIC CPU interface offset.
|
||||
enum _gic_base_offsets {
|
||||
kGICDBaseOffset = 0x1000, //!< GIC distributor offset.
|
||||
kGICCBaseOffset = 0x100 //!< GIC CPU interface offset.
|
||||
};
|
||||
|
||||
//! @brief GIC distributor registers.
|
||||
|
|
@ -47,48 +46,45 @@ enum _gic_base_offsets
|
|||
//! The IPRIORITYRn and ITARGETSRn registers are byte accessible, so their types are uint8_t
|
||||
//! instead of uint32_t to reflect this. These members are indexed directly with the interrupt
|
||||
//! number.
|
||||
struct _gicd_registers
|
||||
{
|
||||
uint32_t CTLR; //!< Distributor Control Register.
|
||||
uint32_t TYPER; //!< Interrupt Controller Type Register.
|
||||
uint32_t IIDR; //!< Distributor Implementer Identification Register.
|
||||
struct _gicd_registers {
|
||||
uint32_t CTLR; //!< Distributor Control Register.
|
||||
uint32_t TYPER; //!< Interrupt Controller Type Register.
|
||||
uint32_t IIDR; //!< Distributor Implementer Identification Register.
|
||||
uint32_t _reserved0[29];
|
||||
uint32_t IGROUPRn[8]; //!< Interrupt Group Registers.
|
||||
uint32_t IGROUPRn[8]; //!< Interrupt Group Registers.
|
||||
uint32_t _reserved1[24];
|
||||
uint32_t ISENABLERn[32]; //!< Interrupt Set-Enable Registers.
|
||||
uint32_t ICENABLERn[32]; //!< Interrupt Clear-Enable Registers.
|
||||
uint32_t ISPENDRn[32]; //!< Interrupt Set-Pending Registers.
|
||||
uint32_t ICPENDRn[32]; //!< Interrupt Clear-Pending Registers.
|
||||
uint32_t ICDABRn[32]; //!< Active Bit Registers.
|
||||
uint32_t ISENABLERn[32]; //!< Interrupt Set-Enable Registers.
|
||||
uint32_t ICENABLERn[32]; //!< Interrupt Clear-Enable Registers.
|
||||
uint32_t ISPENDRn[32]; //!< Interrupt Set-Pending Registers.
|
||||
uint32_t ICPENDRn[32]; //!< Interrupt Clear-Pending Registers.
|
||||
uint32_t ICDABRn[32]; //!< Active Bit Registers.
|
||||
uint32_t _reserved2[32];
|
||||
uint8_t IPRIORITYRn[255 * sizeof(uint32_t)]; //!< Interrupt Priority Registers. (Byte accessible)
|
||||
uint8_t IPRIORITYRn[255 * sizeof(uint32_t)]; //!< Interrupt Priority Registers. (Byte accessible)
|
||||
uint32_t _reserved3;
|
||||
uint8_t ITARGETSRn[255 * sizeof(uint32_t)]; //!< Interrupt Processor Targets Registers. (Byte accessible)
|
||||
uint8_t ITARGETSRn[255 * sizeof(uint32_t)]; //!< Interrupt Processor Targets Registers. (Byte accessible)
|
||||
uint32_t _reserved4;
|
||||
uint32_t ICFGRn[64]; //!< Interrupt Configuration Registers.
|
||||
uint32_t ICFGRn[64]; //!< Interrupt Configuration Registers.
|
||||
uint32_t _reserved5[128];
|
||||
uint32_t SGIR; //!< Software Generated Interrupt Register
|
||||
uint32_t SGIR; //!< Software Generated Interrupt Register
|
||||
};
|
||||
|
||||
//! @brief Bitfields constants for the GICD_CTLR register.
|
||||
enum _gicd_ctlr_fields
|
||||
{
|
||||
enum _gicd_ctlr_fields {
|
||||
kBM_GICD_CTLR_EnableGrp1 = (1 << 1),
|
||||
kBM_GICD_CTLR_EnableGrp0 = (1 << 0)
|
||||
};
|
||||
|
||||
//! @brief Bitfields constants for the GICD_SGIR register.
|
||||
enum _gicd_sgir_fields
|
||||
{
|
||||
enum _gicd_sgir_fields {
|
||||
kBP_GICD_SGIR_TargetListFilter = 24,
|
||||
kBM_GICD_SGIR_TargetListFilter = (0x3 << kBP_GICD_SGIR_TargetListFilter),
|
||||
|
||||
|
||||
kBP_GICD_SGIR_CPUTargetList = 16,
|
||||
kBM_GICD_SGIR_CPUTargetList = (0xff << kBP_GICD_SGIR_CPUTargetList),
|
||||
|
||||
|
||||
kBP_GICD_SGIR_NSATT = 15,
|
||||
kBM_GICD_SGIR_NSATT = (1 << kBP_GICD_SGIR_NSATT),
|
||||
|
||||
|
||||
kBP_GICD_SGIR_SGIINTID = 0,
|
||||
kBM_GICD_SGIR_SGIINTID = 0xf
|
||||
};
|
||||
|
|
@ -96,35 +92,33 @@ enum _gicd_sgir_fields
|
|||
//! @brief GIC CPU interface registers.
|
||||
//!
|
||||
//! Uses the GICv2 register names. Does not include GICv2 registers.
|
||||
struct _gicc_registers
|
||||
{
|
||||
uint32_t CTLR; //!< CPU Interface Control Register.
|
||||
uint32_t PMR; //!< Interrupt Priority Mask Register.
|
||||
uint32_t BPR; //!< Binary Point Register.
|
||||
uint32_t IAR; //!< Interrupt Acknowledge Register.
|
||||
uint32_t EOIR; //!< End of Interrupt Register.
|
||||
uint32_t RPR; //!< Running Priority Register.
|
||||
struct _gicc_registers {
|
||||
uint32_t CTLR; //!< CPU Interface Control Register.
|
||||
uint32_t PMR; //!< Interrupt Priority Mask Register.
|
||||
uint32_t BPR; //!< Binary Point Register.
|
||||
uint32_t IAR; //!< Interrupt Acknowledge Register.
|
||||
uint32_t EOIR; //!< End of Interrupt Register.
|
||||
uint32_t RPR; //!< Running Priority Register.
|
||||
uint32_t HPPIR; //!< Highest Priority Pending Interrupt Register.
|
||||
uint32_t ABPR; //!< Aliased Binary Point Register. (only visible with a secure access)
|
||||
uint32_t ABPR; //!< Aliased Binary Point Register. (only visible with a secure access)
|
||||
uint32_t _reserved[56];
|
||||
uint32_t IIDR; //!< CPU Interface Identification Register.
|
||||
uint32_t IIDR; //!< CPU Interface Identification Register.
|
||||
};
|
||||
|
||||
//! @brief Bitfields constants for the GICC_CTLR register.
|
||||
enum _gicc_ctlr_fields
|
||||
{
|
||||
enum _gicc_ctlr_fields {
|
||||
kBP_GICC_CTLR_EnableS = 0,
|
||||
kBM_GICC_CTLR_EnableS = (1 << 0),
|
||||
|
||||
|
||||
kBP_GICC_CTLR_EnableNS = 1,
|
||||
kBM_GICC_CTLR_EnableNS = (1 << 1),
|
||||
|
||||
|
||||
kBP_GICC_CTLR_AckCtl = 2,
|
||||
kBM_GICC_CTLR_AckCtl = (1 << 2),
|
||||
|
||||
|
||||
kBP_GICC_CTLR_FIQEn = 3,
|
||||
kBM_GICC_CTLR_FIQEn = (1 << 3),
|
||||
|
||||
|
||||
kBP_GICC_CTLR_SBPR = 4,
|
||||
kBM_GICC_CTLR_SBPR = (1 << 4)
|
||||
};
|
||||
|
|
@ -0,0 +1,589 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file hdmi_regs.h
|
||||
* @brief registers defination of hdmi tx module.
|
||||
* @ingroup diag_hdmi
|
||||
*/
|
||||
|
||||
#ifndef __HDMI_REGS_H__
|
||||
#define __HDMI_REGS_H__
|
||||
|
||||
#include "soc_memory_map.h"
|
||||
|
||||
// HDMI PHY REGISTERS
|
||||
#define CREGS_PLL_DIV_ADDR 0x06
|
||||
#define CREGS_PLL_GMP_CNTRL_ADDR 0x15
|
||||
#define CREGS_PLL_PROP_INT_CNTRL_ADDR 0x10
|
||||
#define CREGS_PATTERNGEN 0x1B
|
||||
#define CREGS_PGMODE 0x1C
|
||||
#define CREGS_DIGTXMODE 0x1E
|
||||
|
||||
//
|
||||
// Hdmi controller registers
|
||||
//
|
||||
|
||||
// Identification Registers
|
||||
#define HDMI_DESIGN_ID HDMI_BASE_ADDR+0x0000
|
||||
#define HDMI_REVISION_ID HDMI_BASE_ADDR+0x0001
|
||||
#define HDMI_PRODUCT_ID0 HDMI_BASE_ADDR+0x0002
|
||||
#define HDMI_PRODUCT_ID1 HDMI_BASE_ADDR+0x0003
|
||||
#define HDMI_CONFIG0_ID HDMI_BASE_ADDR+0x0004
|
||||
#define HDMI_CONFIG1_ID HDMI_BASE_ADDR+0x0005
|
||||
#define HDMI_CONFIG2_ID HDMI_BASE_ADDR+0x0006
|
||||
#define HDMI_CONFIG3_ID HDMI_BASE_ADDR+0x0007
|
||||
|
||||
// Interrupt Registers
|
||||
#define HDMI_IH_FC_STAT0 HDMI_BASE_ADDR+0x0100
|
||||
#define HDMI_IH_FC_STAT1 HDMI_BASE_ADDR+0x0101
|
||||
#define HDMI_IH_FC_STAT2 HDMI_BASE_ADDR+0x0102
|
||||
#define HDMI_IH_AS_STAT0 HDMI_BASE_ADDR+0x0103
|
||||
#define HDMI_IH_PHY_STAT0 HDMI_BASE_ADDR+0x0104
|
||||
#define HDMI_IH_I2CM_STAT0 HDMI_BASE_ADDR+0x0105
|
||||
#define HDMI_IH_CEC_STAT0 HDMI_BASE_ADDR+0x0106
|
||||
#define HDMI_IH_VP_STAT0 HDMI_BASE_ADDR+0x0107
|
||||
#define HDMI_IH_I2CMPHY_STAT0 HDMI_BASE_ADDR+0x0108
|
||||
#define HDMI_IH_AHBDMAAUD_STAT0 HDMI_BASE_ADDR+0x0109
|
||||
|
||||
#define HDMI_IH_MUTE_FC_STAT0 HDMI_BASE_ADDR+0x0180
|
||||
#define HDMI_IH_MUTE_FC_STAT1 HDMI_BASE_ADDR+0x0181
|
||||
#define HDMI_IH_MUTE_FC_STAT2 HDMI_BASE_ADDR+0x0182
|
||||
#define HDMI_IH_MUTE_AS_STAT0 HDMI_BASE_ADDR+0x0183
|
||||
#define HDMI_IH_MUTE_PHY_STAT0 HDMI_BASE_ADDR+0x0184
|
||||
#define HDMI_IH_MUTE_I2CM_STAT0 HDMI_BASE_ADDR+0x0185
|
||||
#define HDMI_IH_MUTE_CEC_STAT0 HDMI_BASE_ADDR+0x0186
|
||||
#define HDMI_IH_MUTE_VP_STAT0 HDMI_BASE_ADDR+0x0187
|
||||
#define HDMI_IH_MUTE_I2CMPHY_STAT0 HDMI_BASE_ADDR+0x0188
|
||||
#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 HDMI_BASE_ADDR+0x0189
|
||||
#define HDMI_IH_MUTE HDMI_BASE_ADDR+0x01FF
|
||||
|
||||
// Video Sample Registers
|
||||
#define HDMI_TX_INVID0 HDMI_BASE_ADDR+0x0200
|
||||
#define HDMI_TX_INSTUFFING HDMI_BASE_ADDR+0x0201
|
||||
#define HDMI_TX_GYDATA0 HDMI_BASE_ADDR+0x0202
|
||||
#define HDMI_TX_GYDATA1 HDMI_BASE_ADDR+0x0203
|
||||
#define HDMI_TX_RCRDATA0 HDMI_BASE_ADDR+0x0204
|
||||
#define HDMI_TX_RCRDATA1 HDMI_BASE_ADDR+0x0205
|
||||
#define HDMI_TX_BCBDATA0 HDMI_BASE_ADDR+0x0206
|
||||
#define HDMI_TX_BCBDATA1 HDMI_BASE_ADDR+0x0207
|
||||
|
||||
// Video Packetizer Registers
|
||||
#define HDMI_VP_STATUS HDMI_BASE_ADDR+0x0800
|
||||
#define HDMI_VP_PR_CD HDMI_BASE_ADDR+0x0801
|
||||
#define HDMI_VP_STUFF HDMI_BASE_ADDR+0x0802
|
||||
#define HDMI_VP_REMAP HDMI_BASE_ADDR+0x0803
|
||||
#define HDMI_VP_CONF HDMI_BASE_ADDR+0x0804
|
||||
#define HDMI_VP_STAT HDMI_BASE_ADDR+0x0805
|
||||
#define HDMI_VP_INT HDMI_BASE_ADDR+0x0806
|
||||
#define HDMI_VP_MASK HDMI_BASE_ADDR+0x0807
|
||||
#define HDMI_VP_POL HDMI_BASE_ADDR+0x0808
|
||||
|
||||
// Frame Composer Registers
|
||||
#define HDMI_FC_INVIDCONF HDMI_BASE_ADDR+0x1000
|
||||
#define HDMI_FC_INHACTV0 HDMI_BASE_ADDR+0x1001
|
||||
#define HDMI_FC_INHACTV1 HDMI_BASE_ADDR+0x1002
|
||||
#define HDMI_FC_INHBLANK0 HDMI_BASE_ADDR+0x1003
|
||||
#define HDMI_FC_INHBLANK1 HDMI_BASE_ADDR+0x1004
|
||||
#define HDMI_FC_INVACTV0 HDMI_BASE_ADDR+0x1005
|
||||
#define HDMI_FC_INVACTV1 HDMI_BASE_ADDR+0x1006
|
||||
#define HDMI_FC_INVBLANK HDMI_BASE_ADDR+0x1007
|
||||
#define HDMI_FC_HSYNCINDELAY0 HDMI_BASE_ADDR+0x1008
|
||||
#define HDMI_FC_HSYNCINDELAY1 HDMI_BASE_ADDR+0x1009
|
||||
#define HDMI_FC_HSYNCINWIDTH0 HDMI_BASE_ADDR+0x100A
|
||||
#define HDMI_FC_HSYNCINWIDTH1 HDMI_BASE_ADDR+0x100B
|
||||
#define HDMI_FC_VSYNCINDELAY HDMI_BASE_ADDR+0x100C
|
||||
#define HDMI_FC_VSYNCINWIDTH HDMI_BASE_ADDR+0x100D
|
||||
#define HDMI_FC_INFREQ0 HDMI_BASE_ADDR+0x100E
|
||||
#define HDMI_FC_INFREQ1 HDMI_BASE_ADDR+0x100F
|
||||
#define HDMI_FC_INFREQ2 HDMI_BASE_ADDR+0x1010
|
||||
#define HDMI_FC_CTRLDUR HDMI_BASE_ADDR+0x1011
|
||||
#define HDMI_FC_EXCTRLDUR HDMI_BASE_ADDR+0x1012
|
||||
#define HDMI_FC_EXCTRLSPAC HDMI_BASE_ADDR+0x1013
|
||||
#define HDMI_FC_CH0PREAM HDMI_BASE_ADDR+0x1014
|
||||
#define HDMI_FC_CH1PREAM HDMI_BASE_ADDR+0x1015
|
||||
#define HDMI_FC_CH2PREAM HDMI_BASE_ADDR+0x1016
|
||||
#define HDMI_FC_AVICONF3 HDMI_BASE_ADDR+0x1017
|
||||
#define HDMI_FC_GCP HDMI_BASE_ADDR+0x1018
|
||||
#define HDMI_FC_AVICONF0 HDMI_BASE_ADDR+0x1019
|
||||
#define HDMI_FC_AVICONF1 HDMI_BASE_ADDR+0x101A
|
||||
#define HDMI_FC_AVICONF2 HDMI_BASE_ADDR+0x101B
|
||||
#define HDMI_FC_AVIVID HDMI_BASE_ADDR+0x101C
|
||||
#define HDMI_FC_AVIETB0 HDMI_BASE_ADDR+0x101D
|
||||
#define HDMI_FC_AVIETB1 HDMI_BASE_ADDR+0x101E
|
||||
#define HDMI_FC_AVISBB0 HDMI_BASE_ADDR+0x101F
|
||||
#define HDMI_FC_AVISBB1 HDMI_BASE_ADDR+0x1020
|
||||
#define HDMI_FC_AVIELB0 HDMI_BASE_ADDR+0x1021
|
||||
#define HDMI_FC_AVIELB1 HDMI_BASE_ADDR+0x1022
|
||||
#define HDMI_FC_AVISRB0 HDMI_BASE_ADDR+0x1023
|
||||
#define HDMI_FC_AVISRB1 HDMI_BASE_ADDR+0x1024
|
||||
#define HDMI_FC_AUDICONF0 HDMI_BASE_ADDR+0x1025
|
||||
#define HDMI_FC_AUDICONF1 HDMI_BASE_ADDR+0x1026
|
||||
#define HDMI_FC_AUDICONF2 HDMI_BASE_ADDR+0x1027
|
||||
#define HDMI_FC_AUDICONF3 HDMI_BASE_ADDR+0x1028
|
||||
#define HDMI_FC_VSDIEEEID0 HDMI_BASE_ADDR+0x1029
|
||||
#define HDMI_FC_VSDSIZE HDMI_BASE_ADDR+0x102A
|
||||
#define HDMI_FC_VSDIEEEID1 HDMI_BASE_ADDR+0x1030
|
||||
#define HDMI_FC_VSDIEEEID2 HDMI_BASE_ADDR+0x1031
|
||||
#define HDMI_FC_VSDPAYLOAD0 HDMI_BASE_ADDR+0x1032
|
||||
#define HDMI_FC_VSDPAYLOAD1 HDMI_BASE_ADDR+0x1033
|
||||
#define HDMI_FC_VSDPAYLOAD2 HDMI_BASE_ADDR+0x1034
|
||||
#define HDMI_FC_VSDPAYLOAD3 HDMI_BASE_ADDR+0x1035
|
||||
#define HDMI_FC_VSDPAYLOAD4 HDMI_BASE_ADDR+0x1036
|
||||
#define HDMI_FC_VSDPAYLOAD5 HDMI_BASE_ADDR+0x1037
|
||||
#define HDMI_FC_VSDPAYLOAD6 HDMI_BASE_ADDR+0x1038
|
||||
#define HDMI_FC_VSDPAYLOAD7 HDMI_BASE_ADDR+0x1039
|
||||
#define HDMI_FC_VSDPAYLOAD8 HDMI_BASE_ADDR+0x103A
|
||||
#define HDMI_FC_VSDPAYLOAD9 HDMI_BASE_ADDR+0x103B
|
||||
#define HDMI_FC_VSDPAYLOAD10 HDMI_BASE_ADDR+0x103C
|
||||
#define HDMI_FC_VSDPAYLOAD11 HDMI_BASE_ADDR+0x103D
|
||||
#define HDMI_FC_VSDPAYLOAD12 HDMI_BASE_ADDR+0x103E
|
||||
#define HDMI_FC_VSDPAYLOAD13 HDMI_BASE_ADDR+0x103F
|
||||
#define HDMI_FC_VSDPAYLOAD14 HDMI_BASE_ADDR+0x1040
|
||||
#define HDMI_FC_VSDPAYLOAD15 HDMI_BASE_ADDR+0x1041
|
||||
#define HDMI_FC_VSDPAYLOAD16 HDMI_BASE_ADDR+0x1042
|
||||
#define HDMI_FC_VSDPAYLOAD17 HDMI_BASE_ADDR+0x1043
|
||||
#define HDMI_FC_VSDPAYLOAD18 HDMI_BASE_ADDR+0x1044
|
||||
#define HDMI_FC_VSDPAYLOAD19 HDMI_BASE_ADDR+0x1045
|
||||
#define HDMI_FC_VSDPAYLOAD20 HDMI_BASE_ADDR+0x1046
|
||||
#define HDMI_FC_VSDPAYLOAD21 HDMI_BASE_ADDR+0x1047
|
||||
#define HDMI_FC_VSDPAYLOAD22 HDMI_BASE_ADDR+0x1048
|
||||
#define HDMI_FC_VSDPAYLOAD23 HDMI_BASE_ADDR+0x1049
|
||||
#define HDMI_FC_SPDVENDORNAME0 HDMI_BASE_ADDR+0x104A
|
||||
#define HDMI_FC_SPDVENDORNAME1 HDMI_BASE_ADDR+0x104B
|
||||
#define HDMI_FC_SPDVENDORNAME2 HDMI_BASE_ADDR+0x104C
|
||||
#define HDMI_FC_SPDVENDORNAME3 HDMI_BASE_ADDR+0x104D
|
||||
#define HDMI_FC_SPDVENDORNAME4 HDMI_BASE_ADDR+0x104E
|
||||
#define HDMI_FC_SPDVENDORNAME5 HDMI_BASE_ADDR+0x104F
|
||||
#define HDMI_FC_SPDVENDORNAME6 HDMI_BASE_ADDR+0x1050
|
||||
#define HDMI_FC_SPDVENDORNAME7 HDMI_BASE_ADDR+0x1051
|
||||
#define HDMI_FC_SDPPRODUCTNAME0 HDMI_BASE_ADDR+0x1052
|
||||
#define HDMI_FC_SDPPRODUCTNAME1 HDMI_BASE_ADDR+0x1053
|
||||
#define HDMI_FC_SDPPRODUCTNAME2 HDMI_BASE_ADDR+0x1054
|
||||
#define HDMI_FC_SDPPRODUCTNAME3 HDMI_BASE_ADDR+0x1055
|
||||
#define HDMI_FC_SDPPRODUCTNAME4 HDMI_BASE_ADDR+0x1056
|
||||
#define HDMI_FC_SDPPRODUCTNAME5 HDMI_BASE_ADDR+0x1057
|
||||
#define HDMI_FC_SDPPRODUCTNAME6 HDMI_BASE_ADDR+0x1058
|
||||
#define HDMI_FC_SDPPRODUCTNAME7 HDMI_BASE_ADDR+0x1059
|
||||
#define HDMI_FC_SDPPRODUCTNAME8 HDMI_BASE_ADDR+0x105A
|
||||
#define HDMI_FC_SDPPRODUCTNAME9 HDMI_BASE_ADDR+0x105B
|
||||
#define HDMI_FC_SDPPRODUCTNAME10 HDMI_BASE_ADDR+0x105C
|
||||
#define HDMI_FC_SDPPRODUCTNAME11 HDMI_BASE_ADDR+0x105D
|
||||
#define HDMI_FC_SDPPRODUCTNAME12 HDMI_BASE_ADDR+0x105E
|
||||
#define HDMI_FC_SDPPRODUCTNAME13 HDMI_BASE_ADDR+0x105F
|
||||
#define HDMI_FC_SDPPRODUCTNAME14 HDMI_BASE_ADDR+0x1060
|
||||
#define HDMI_FC_SPDPRODUCTNAME15 HDMI_BASE_ADDR+0x1061
|
||||
#define HDMI_FC_SPDDEVICEINF HDMI_BASE_ADDR+0x1062
|
||||
#define HDMI_FC_AUDSCONF HDMI_BASE_ADDR+0x1063
|
||||
#define HDMI_FC_AUDSSTAT HDMI_BASE_ADDR+0x1064
|
||||
#define HDMI_FC_AUDSV HDMI_BASE_ADDR+0x1065
|
||||
#define HDMI_FC_AUDSU HDMI_BASE_ADDR+0x1066
|
||||
#define HDMI_FC_AUDSCHNLS0 HDMI_BASE_ADDR+0x1067
|
||||
#define HDMI_FC_AUDSCHNLS1 HDMI_BASE_ADDR+0x1068
|
||||
#define HDMI_FC_AUDSCHNLS2 HDMI_BASE_ADDR+0x1069
|
||||
#define HDMI_FC_AUDSCHNLS3 HDMI_BASE_ADDR+0x106A
|
||||
#define HDMI_FC_AUDSCHNLS4 HDMI_BASE_ADDR+0x106B
|
||||
#define HDMI_FC_AUDSCHNLS5 HDMI_BASE_ADDR+0x106C
|
||||
#define HDMI_FC_AUDSCHNLS6 HDMI_BASE_ADDR+0x106D
|
||||
#define HDMI_FC_AUDSCHNLS7 HDMI_BASE_ADDR+0x106E
|
||||
#define HDMI_FC_AUDSCHNLS8 HDMI_BASE_ADDR+0x106F
|
||||
#define HDMI_FC_DATACH0FILL HDMI_BASE_ADDR+0x1070
|
||||
#define HDMI_FC_DATACH1FILL HDMI_BASE_ADDR+0x1071
|
||||
#define HDMI_FC_DATACH2FILL HDMI_BASE_ADDR+0x1072
|
||||
#define HDMI_FC_CTRLQHIGH HDMI_BASE_ADDR+0x1073
|
||||
#define HDMI_FC_CTRLQLOW HDMI_BASE_ADDR+0x1074
|
||||
#define HDMI_FC_ACP0 HDMI_BASE_ADDR+0x1075
|
||||
#define HDMI_FC_ACP28 HDMI_BASE_ADDR+0x1076
|
||||
#define HDMI_FC_ACP27 HDMI_BASE_ADDR+0x1077
|
||||
#define HDMI_FC_ACP26 HDMI_BASE_ADDR+0x1078
|
||||
#define HDMI_FC_ACP25 HDMI_BASE_ADDR+0x1079
|
||||
#define HDMI_FC_ACP24 HDMI_BASE_ADDR+0x107A
|
||||
#define HDMI_FC_ACP23 HDMI_BASE_ADDR+0x107B
|
||||
#define HDMI_FC_ACP22 HDMI_BASE_ADDR+0x107C
|
||||
#define HDMI_FC_ACP21 HDMI_BASE_ADDR+0x107D
|
||||
#define HDMI_FC_ACP20 HDMI_BASE_ADDR+0x107E
|
||||
#define HDMI_FC_ACP19 HDMI_BASE_ADDR+0x107F
|
||||
#define HDMI_FC_ACP18 HDMI_BASE_ADDR+0x1080
|
||||
#define HDMI_FC_ACP17 HDMI_BASE_ADDR+0x1081
|
||||
#define HDMI_FC_ACP16 HDMI_BASE_ADDR+0x1082
|
||||
#define HDMI_FC_ACP15 HDMI_BASE_ADDR+0x1083
|
||||
#define HDMI_FC_ACP14 HDMI_BASE_ADDR+0x1084
|
||||
#define HDMI_FC_ACP13 HDMI_BASE_ADDR+0x1085
|
||||
#define HDMI_FC_ACP12 HDMI_BASE_ADDR+0x1086
|
||||
#define HDMI_FC_ACP11 HDMI_BASE_ADDR+0x1087
|
||||
#define HDMI_FC_ACP10 HDMI_BASE_ADDR+0x1088
|
||||
#define HDMI_FC_ACP9 HDMI_BASE_ADDR+0x1089
|
||||
#define HDMI_FC_ACP8 HDMI_BASE_ADDR+0x108A
|
||||
#define HDMI_FC_ACP7 HDMI_BASE_ADDR+0x108B
|
||||
#define HDMI_FC_ACP6 HDMI_BASE_ADDR+0x108C
|
||||
#define HDMI_FC_ACP5 HDMI_BASE_ADDR+0x108D
|
||||
#define HDMI_FC_ACP4 HDMI_BASE_ADDR+0x108E
|
||||
#define HDMI_FC_ACP3 HDMI_BASE_ADDR+0x108F
|
||||
#define HDMI_FC_ACP2 HDMI_BASE_ADDR+0x1090
|
||||
#define HDMI_FC_ACP1 HDMI_BASE_ADDR+0x1091
|
||||
#define HDMI_FC_ISCR1_0 HDMI_BASE_ADDR+0x1092
|
||||
#define HDMI_FC_ISCR1_16 HDMI_BASE_ADDR+0x1093
|
||||
#define HDMI_FC_ISCR1_15 HDMI_BASE_ADDR+0x1094
|
||||
#define HDMI_FC_ISCR1_14 HDMI_BASE_ADDR+0x1095
|
||||
#define HDMI_FC_ISCR1_13 HDMI_BASE_ADDR+0x1096
|
||||
#define HDMI_FC_ISCR1_12 HDMI_BASE_ADDR+0x1097
|
||||
#define HDMI_FC_ISCR1_11 HDMI_BASE_ADDR+0x1098
|
||||
#define HDMI_FC_ISCR1_10 HDMI_BASE_ADDR+0x1099
|
||||
#define HDMI_FC_ISCR1_9 HDMI_BASE_ADDR+0x109A
|
||||
#define HDMI_FC_ISCR1_8 HDMI_BASE_ADDR+0x109B
|
||||
#define HDMI_FC_ISCR1_7 HDMI_BASE_ADDR+0x109C
|
||||
#define HDMI_FC_ISCR1_6 HDMI_BASE_ADDR+0x109D
|
||||
#define HDMI_FC_ISCR1_5 HDMI_BASE_ADDR+0x109E
|
||||
#define HDMI_FC_ISCR1_4 HDMI_BASE_ADDR+0x109F
|
||||
#define HDMI_FC_ISCR1_3 HDMI_BASE_ADDR+0x10A0
|
||||
#define HDMI_FC_ISCR1_2 HDMI_BASE_ADDR+0x10A1
|
||||
#define HDMI_FC_ISCR1_1 HDMI_BASE_ADDR+0x10A2
|
||||
#define HDMI_FC_ISCR2_15 HDMI_BASE_ADDR+0x10A3
|
||||
#define HDMI_FC_ISCR2_14 HDMI_BASE_ADDR+0x10A4
|
||||
#define HDMI_FC_ISCR2_13 HDMI_BASE_ADDR+0x10A5
|
||||
#define HDMI_FC_ISCR2_12 HDMI_BASE_ADDR+0x10A6
|
||||
#define HDMI_FC_ISCR2_11 HDMI_BASE_ADDR+0x10A7
|
||||
#define HDMI_FC_ISCR2_10 HDMI_BASE_ADDR+0x10A8
|
||||
#define HDMI_FC_ISCR2_9 HDMI_BASE_ADDR+0x10A9
|
||||
#define HDMI_FC_ISCR2_8 HDMI_BASE_ADDR+0x10AA
|
||||
#define HDMI_FC_ISCR2_7 HDMI_BASE_ADDR+0x10AB
|
||||
#define HDMI_FC_ISCR2_6 HDMI_BASE_ADDR+0x10AC
|
||||
#define HDMI_FC_ISCR2_5 HDMI_BASE_ADDR+0x10AD
|
||||
#define HDMI_FC_ISCR2_4 HDMI_BASE_ADDR+0x10AE
|
||||
#define HDMI_FC_ISCR2_3 HDMI_BASE_ADDR+0x10AF
|
||||
#define HDMI_FC_ISCR2_2 HDMI_BASE_ADDR+0x10B0
|
||||
#define HDMI_FC_ISCR2_1 HDMI_BASE_ADDR+0x10B1
|
||||
#define HDMI_FC_ISCR2_0 HDMI_BASE_ADDR+0x10B2
|
||||
#define HDMI_FC_DATAUTO0 HDMI_BASE_ADDR+0x10B3
|
||||
#define HDMI_FC_DATAUTO1 HDMI_BASE_ADDR+0x10B4
|
||||
#define HDMI_FC_DATAUTO2 HDMI_BASE_ADDR+0x10B5
|
||||
#define HDMI_FC_DATMAN HDMI_BASE_ADDR+0x10B6
|
||||
#define HDMI_FC_DATAUTO3 HDMI_BASE_ADDR+0x10B7
|
||||
#define HDMI_FC_RDRB0 HDMI_BASE_ADDR+0x10B8
|
||||
#define HDMI_FC_RDRB1 HDMI_BASE_ADDR+0x10B9
|
||||
#define HDMI_FC_RDRB2 HDMI_BASE_ADDR+0x10BA
|
||||
#define HDMI_FC_RDRB3 HDMI_BASE_ADDR+0x10BB
|
||||
#define HDMI_FC_RDRB4 HDMI_BASE_ADDR+0x10BC
|
||||
#define HDMI_FC_RDRB5 HDMI_BASE_ADDR+0x10BD
|
||||
#define HDMI_FC_RDRB6 HDMI_BASE_ADDR+0x10BE
|
||||
#define HDMI_FC_RDRB7 HDMI_BASE_ADDR+0x10BF
|
||||
#define HDMI_FC_STAT0 HDMI_BASE_ADDR+0x10D0
|
||||
#define HDMI_FC_INT0 HDMI_BASE_ADDR+0x10D1
|
||||
#define HDMI_FC_MASK0 HDMI_BASE_ADDR+0x10D2
|
||||
#define HDMI_FC_POL0 HDMI_BASE_ADDR+0x10D3
|
||||
#define HDMI_FC_STAT1 HDMI_BASE_ADDR+0x10D4
|
||||
#define HDMI_FC_INT1 HDMI_BASE_ADDR+0x10D5
|
||||
#define HDMI_FC_MASK1 HDMI_BASE_ADDR+0x10D6
|
||||
#define HDMI_FC_POL1 HDMI_BASE_ADDR+0x10D7
|
||||
#define HDMI_FC_STAT2 HDMI_BASE_ADDR+0x10D8
|
||||
#define HDMI_FC_INT2 HDMI_BASE_ADDR+0x10D9
|
||||
#define HDMI_FC_MASK2 HDMI_BASE_ADDR+0x10DA
|
||||
#define HDMI_FC_POL2 HDMI_BASE_ADDR+0x10DB
|
||||
#define HDMI_FC_PRCONF HDMI_BASE_ADDR+0x10E0
|
||||
|
||||
#define HDMI_FC_GMD_STAT HDMI_BASE_ADDR+0x1100
|
||||
#define HDMI_FC_GMD_EN HDMI_BASE_ADDR+0x1101
|
||||
#define HDMI_FC_GMD_UP HDMI_BASE_ADDR+0x1102
|
||||
#define HDMI_FC_GMD_CONF HDMI_BASE_ADDR+0x1103
|
||||
#define HDMI_FC_GMD_HB HDMI_BASE_ADDR+0x1104
|
||||
#define HDMI_FC_GMD_PB0 HDMI_BASE_ADDR+0x1105
|
||||
#define HDMI_FC_GMD_PB1 HDMI_BASE_ADDR+0x1106
|
||||
#define HDMI_FC_GMD_PB2 HDMI_BASE_ADDR+0x1107
|
||||
#define HDMI_FC_GMD_PB3 HDMI_BASE_ADDR+0x1108
|
||||
#define HDMI_FC_GMD_PB4 HDMI_BASE_ADDR+0x1109
|
||||
#define HDMI_FC_GMD_PB5 HDMI_BASE_ADDR+0x110A
|
||||
#define HDMI_FC_GMD_PB6 HDMI_BASE_ADDR+0x110B
|
||||
#define HDMI_FC_GMD_PB7 HDMI_BASE_ADDR+0x110C
|
||||
#define HDMI_FC_GMD_PB8 HDMI_BASE_ADDR+0x110D
|
||||
#define HDMI_FC_GMD_PB9 HDMI_BASE_ADDR+0x110E
|
||||
#define HDMI_FC_GMD_PB10 HDMI_BASE_ADDR+0x110F
|
||||
#define HDMI_FC_GMD_PB11 HDMI_BASE_ADDR+0x1110
|
||||
#define HDMI_FC_GMD_PB12 HDMI_BASE_ADDR+0x1111
|
||||
#define HDMI_FC_GMD_PB13 HDMI_BASE_ADDR+0x1112
|
||||
#define HDMI_FC_GMD_PB14 HDMI_BASE_ADDR+0x1113
|
||||
#define HDMI_FC_GMD_PB15 HDMI_BASE_ADDR+0x1114
|
||||
#define HDMI_FC_GMD_PB16 HDMI_BASE_ADDR+0x1115
|
||||
#define HDMI_FC_GMD_PB17 HDMI_BASE_ADDR+0x1116
|
||||
#define HDMI_FC_GMD_PB18 HDMI_BASE_ADDR+0x1117
|
||||
#define HDMI_FC_GMD_PB19 HDMI_BASE_ADDR+0x1118
|
||||
#define HDMI_FC_GMD_PB20 HDMI_BASE_ADDR+0x1119
|
||||
#define HDMI_FC_GMD_PB21 HDMI_BASE_ADDR+0x111A
|
||||
#define HDMI_FC_GMD_PB22 HDMI_BASE_ADDR+0x111B
|
||||
#define HDMI_FC_GMD_PB23 HDMI_BASE_ADDR+0x111C
|
||||
#define HDMI_FC_GMD_PB24 HDMI_BASE_ADDR+0x111D
|
||||
#define HDMI_FC_GMD_PB25 HDMI_BASE_ADDR+0x111E
|
||||
#define HDMI_FC_GMD_PB26 HDMI_BASE_ADDR+0x111F
|
||||
#define HDMI_FC_GMD_PB27 HDMI_BASE_ADDR+0x1120
|
||||
|
||||
#define HDMI_FC_DBGFORCE HDMI_BASE_ADDR+0x1200
|
||||
#define HDMI_FC_DBGAUD0CH0 HDMI_BASE_ADDR+0x1201
|
||||
#define HDMI_FC_DBGAUD1CH0 HDMI_BASE_ADDR+0x1202
|
||||
#define HDMI_FC_DBGAUD2CH0 HDMI_BASE_ADDR+0x1203
|
||||
#define HDMI_FC_DBGAUD0CH1 HDMI_BASE_ADDR+0x1204
|
||||
#define HDMI_FC_DBGAUD1CH1 HDMI_BASE_ADDR+0x1205
|
||||
#define HDMI_FC_DBGAUD2CH1 HDMI_BASE_ADDR+0x1206
|
||||
#define HDMI_FC_DBGAUD0CH2 HDMI_BASE_ADDR+0x1207
|
||||
#define HDMI_FC_DBGAUD1CH2 HDMI_BASE_ADDR+0x1208
|
||||
#define HDMI_FC_DBGAUD2CH2 HDMI_BASE_ADDR+0x1209
|
||||
#define HDMI_FC_DBGAUD0CH3 HDMI_BASE_ADDR+0x120A
|
||||
#define HDMI_FC_DBGAUD1CH3 HDMI_BASE_ADDR+0x120B
|
||||
#define HDMI_FC_DBGAUD2CH3 HDMI_BASE_ADDR+0x120C
|
||||
#define HDMI_FC_DBGAUD0CH4 HDMI_BASE_ADDR+0x120D
|
||||
#define HDMI_FC_DBGAUD1CH4 HDMI_BASE_ADDR+0x120E
|
||||
#define HDMI_FC_DBGAUD2CH4 HDMI_BASE_ADDR+0x120F
|
||||
#define HDMI_FC_DBGAUD0CH5 HDMI_BASE_ADDR+0x1210
|
||||
#define HDMI_FC_DBGAUD1CH5 HDMI_BASE_ADDR+0x1211
|
||||
#define HDMI_FC_DBGAUD2CH5 HDMI_BASE_ADDR+0x1212
|
||||
#define HDMI_FC_DBGAUD0CH6 HDMI_BASE_ADDR+0x1213
|
||||
#define HDMI_FC_DBGAUD1CH6 HDMI_BASE_ADDR+0x1214
|
||||
#define HDMI_FC_DBGAUD2CH6 HDMI_BASE_ADDR+0x1215
|
||||
#define HDMI_FC_DBGAUD0CH7 HDMI_BASE_ADDR+0x1216
|
||||
#define HDMI_FC_DBGAUD1CH7 HDMI_BASE_ADDR+0x1217
|
||||
#define HDMI_FC_DBGAUD2CH7 HDMI_BASE_ADDR+0x1218
|
||||
#define HDMI_FC_DBGTMDS0 HDMI_BASE_ADDR+0x1219
|
||||
#define HDMI_FC_DBGTMDS1 HDMI_BASE_ADDR+0x121A
|
||||
#define HDMI_FC_DBGTMDS2 HDMI_BASE_ADDR+0x121B
|
||||
|
||||
// HDMI Source PHY Registers
|
||||
#define HDMI_PHY_CONF0 HDMI_BASE_ADDR+0x3000
|
||||
#define HDMI_PHY_TST0 HDMI_BASE_ADDR+0x3001
|
||||
#define HDMI_PHY_TST1 HDMI_BASE_ADDR+0x3002
|
||||
#define HDMI_PHY_TST2 HDMI_BASE_ADDR+0x3003
|
||||
#define HDMI_PHY_STAT0 HDMI_BASE_ADDR+0x3004
|
||||
#define HDMI_PHY_INT0 HDMI_BASE_ADDR+0x3005
|
||||
#define HDMI_PHY_MASK0 HDMI_BASE_ADDR+0x3006
|
||||
#define HDMI_PHY_POL0 HDMI_BASE_ADDR+0x3007
|
||||
|
||||
// HDMI Master PHY Registers
|
||||
#define HDMI_PHY_I2CM_SLAVE_ADDR HDMI_BASE_ADDR+0x3020
|
||||
#define HDMI_PHY_I2CM_ADDRESS_ADDR HDMI_BASE_ADDR+0x3021
|
||||
#define HDMI_PHY_I2CM_DATAO_1_ADDR HDMI_BASE_ADDR+0x3022
|
||||
#define HDMI_PHY_I2CM_DATAO_0_ADDR HDMI_BASE_ADDR+0x3023
|
||||
#define HDMI_PHY_I2CM_DATAI_1_ADDR HDMI_BASE_ADDR+0x3024
|
||||
#define HDMI_PHY_I2CM_DATAI_0_ADDR HDMI_BASE_ADDR+0x3025
|
||||
#define HDMI_PHY_I2CM_OPERATION_ADDR HDMI_BASE_ADDR+0x3026
|
||||
#define HDMI_PHY_I2CM_INT_ADDR HDMI_BASE_ADDR+0x3027
|
||||
#define HDMI_PHY_I2CM_CTLINT_ADDR HDMI_BASE_ADDR+0x3028
|
||||
#define HDMI_PHY_I2CM_DIV_ADDR HDMI_BASE_ADDR+0x3029
|
||||
#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR HDMI_BASE_ADDR+0x302a
|
||||
#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR HDMI_BASE_ADDR+0x302b
|
||||
#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR HDMI_BASE_ADDR+0x302c
|
||||
#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR HDMI_BASE_ADDR+0x302d
|
||||
#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR HDMI_BASE_ADDR+0x302e
|
||||
#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR HDMI_BASE_ADDR+0x302f
|
||||
#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR HDMI_BASE_ADDR+0x3030
|
||||
#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR HDMI_BASE_ADDR+0x3031
|
||||
#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR HDMI_BASE_ADDR+0x3032
|
||||
|
||||
#define HDMI_AUD_N1 HDMI_BASE_ADDR+0x3200
|
||||
#define HDMI_AUD_N2 HDMI_BASE_ADDR+0x3201
|
||||
#define HDMI_AUD_N3 HDMI_BASE_ADDR+0x3202
|
||||
|
||||
#define HDMI_AUD_CTS1 HDMI_BASE_ADDR+0x3203
|
||||
#define HDMI_AUD_CTS2 HDMI_BASE_ADDR+0x3204
|
||||
#define HDMI_AUD_CTS3 HDMI_BASE_ADDR+0x3205
|
||||
#define HDMI_AUD_INPUTCLKFS HDMI_BASE_ADDR+0x3206
|
||||
|
||||
// Generic Parallel Audio Interface Registers
|
||||
#define HDMI_GP_CONF0 HDMI_BASE_ADDR+0x3500
|
||||
#define HDMI_GP_CONF1 HDMI_BASE_ADDR+0x3501
|
||||
#define HDMI_GP_CONF2 HDMI_BASE_ADDR+0x3502
|
||||
#define HDMI_GP_STAT HDMI_BASE_ADDR+0x3503
|
||||
#define HDMI_GP_INT HDMI_BASE_ADDR+0x3504
|
||||
#define HDMI_GP_MASK HDMI_BASE_ADDR+0x3505
|
||||
#define HDMI_GP_POL HDMI_BASE_ADDR+0x3506
|
||||
|
||||
// Audio DMA Registers (TBD)
|
||||
#define HDMI_AHB_DMA_CONF0 HDMI_BASE_ADDR+0x3600
|
||||
#define HDMI_AHB_DMA_START HDMI_BASE_ADDR+0x3601
|
||||
#define HDMI_AHB_DMA_STOP HDMI_BASE_ADDR+0x3602
|
||||
#define HDMI_AHB_DMA_THRSLD HDMI_BASE_ADDR+0x3603
|
||||
#define HDMI_AHB_DMA_STRADDR0 HDMI_BASE_ADDR+0x3604
|
||||
#define HDMI_AHB_DMA_STRADDR1 HDMI_BASE_ADDR+0x3605
|
||||
#define HDMI_AHB_DMA_STRADDR2 HDMI_BASE_ADDR+0x3606
|
||||
#define HDMI_AHB_DMA_STRADDR3 HDMI_BASE_ADDR+0x3607
|
||||
#define HDMI_AHB_DMA_STPADDR0 HDMI_BASE_ADDR+0x3608
|
||||
#define HDMI_AHB_DMA_STPADDR1 HDMI_BASE_ADDR+0x3609
|
||||
#define HDMI_AHB_DMA_STPADDR2 HDMI_BASE_ADDR+0x360a
|
||||
#define HDMI_AHB_DMA_STPADDR3 HDMI_BASE_ADDR+0x360b
|
||||
#define HDMI_AHB_DMA_BSTADDR0 HDMI_BASE_ADDR+0x360c
|
||||
#define HDMI_AHB_DMA_BSTADDR1 HDMI_BASE_ADDR+0x360d
|
||||
#define HDMI_AHB_DMA_BSTADDR2 HDMI_BASE_ADDR+0x360e
|
||||
#define HDMI_AHB_DMA_BSTADDR3 HDMI_BASE_ADDR+0x360f
|
||||
#define HDMI_AHB_DMA_MBLENGTH0 HDMI_BASE_ADDR+0x3610
|
||||
#define HDMI_AHB_DMA_MBLENGTH1 HDMI_BASE_ADDR+0x3611
|
||||
#define HDMI_AHB_DMA_STAT HDMI_BASE_ADDR+0x3612
|
||||
#define HDMI_AHB_DMA_INT HDMI_BASE_ADDR+0x3613
|
||||
#define HDMI_AHB_DMA_MASK HDMI_BASE_ADDR+0x3614
|
||||
#define HDMI_AHB_DMA_POL HDMI_BASE_ADDR+0x3615
|
||||
#define HDMI_AHB_DMA_CONF1 HDMI_BASE_ADDR+0x3616
|
||||
#define HDMI_AHB_DMA_BUFFSTAT HDMI_BASE_ADDR+0x3617
|
||||
#define HDMI_AHB_DMA_BUFFINT HDMI_BASE_ADDR+0x3618
|
||||
#define HDMI_AHB_DMA_BUFFMASK HDMI_BASE_ADDR+0x3619
|
||||
#define HDMI_AHB_DMA_BUFFPOL HDMI_BASE_ADDR+0x361a
|
||||
|
||||
// Main Controller Registers
|
||||
#define HDMI_MC_SFRDIV HDMI_BASE_ADDR+0x4000
|
||||
#define HDMI_MC_CLKDIS HDMI_BASE_ADDR+0x4001
|
||||
#define HDMI_MC_SWRSTZ HDMI_BASE_ADDR+0x4002
|
||||
#define HDMI_MC_OPCTRL HDMI_BASE_ADDR+0x4003
|
||||
#define HDMI_MC_FLOWCTRL HDMI_BASE_ADDR+0x4004
|
||||
#define HDMI_MC_PHYRSTZ HDMI_BASE_ADDR+0x4005
|
||||
#define HDMI_MC_LOCKONCLOCK HDMI_BASE_ADDR+0x4006
|
||||
#define HDMI_MC_HEACPHY_RST HDMI_BASE_ADDR+0x4007
|
||||
|
||||
// Color Space Converter Registers
|
||||
#define HDMI_CSC_CFG HDMI_BASE_ADDR+0x4100
|
||||
#define HDMI_CSC_SCALE HDMI_BASE_ADDR+0x4101
|
||||
#define HDMI_CSC_COEF_A1_MSB HDMI_BASE_ADDR+0x4102
|
||||
#define HDMI_CSC_COEF_A1_LSB HDMI_BASE_ADDR+0x4103
|
||||
#define HDMI_CSC_COEF_A2_MSB HDMI_BASE_ADDR+0x4104
|
||||
#define HDMI_CSC_COEF_A2_LSB HDMI_BASE_ADDR+0x4105
|
||||
#define HDMI_CSC_COEF_A3_MSB HDMI_BASE_ADDR+0x4106
|
||||
#define HDMI_CSC_COEF_A3_LSB HDMI_BASE_ADDR+0x4107
|
||||
#define HDMI_CSC_COEF_A4_MSB HDMI_BASE_ADDR+0x4108
|
||||
#define HDMI_CSC_COEF_A4_LSB HDMI_BASE_ADDR+0x4109
|
||||
#define HDMI_CSC_COEF_B1_MSB HDMI_BASE_ADDR+0x410A
|
||||
#define HDMI_CSC_COEF_B1_LSB HDMI_BASE_ADDR+0x410B
|
||||
#define HDMI_CSC_COEF_B2_MSB HDMI_BASE_ADDR+0x410C
|
||||
#define HDMI_CSC_COEF_B2_LSB HDMI_BASE_ADDR+0x410D
|
||||
#define HDMI_CSC_COEF_B3_MSB HDMI_BASE_ADDR+0x410E
|
||||
#define HDMI_CSC_COEF_B3_LSB HDMI_BASE_ADDR+0x410F
|
||||
#define HDMI_CSC_COEF_B4_MSB HDMI_BASE_ADDR+0x4110
|
||||
#define HDMI_CSC_COEF_B4_LSB HDMI_BASE_ADDR+0x4111
|
||||
#define HDMI_CSC_COEF_C1_MSB HDMI_BASE_ADDR+0x4112
|
||||
#define HDMI_CSC_COEF_C1_LSB HDMI_BASE_ADDR+0x4113
|
||||
#define HDMI_CSC_COEF_C2_MSB HDMI_BASE_ADDR+0x4114
|
||||
#define HDMI_CSC_COEF_C2_LSB HDMI_BASE_ADDR+0x4115
|
||||
#define HDMI_CSC_COEF_C3_MSB HDMI_BASE_ADDR+0x4116
|
||||
#define HDMI_CSC_COEF_C3_LSB HDMI_BASE_ADDR+0x4117
|
||||
#define HDMI_CSC_COEF_C4_MSB HDMI_BASE_ADDR+0x4118
|
||||
#define HDMI_CSC_COEF_C4_LSB HDMI_BASE_ADDR+0x4119
|
||||
|
||||
// HDCP Encryption Engine Registers
|
||||
#define HDMI_A_HDCPCFG0 HDMI_BASE_ADDR+0x5000
|
||||
#define HDMI_A_HDCPCFG1 HDMI_BASE_ADDR+0x5001
|
||||
#define HDMI_A_HDCPOBS0 HDMI_BASE_ADDR+0x5002
|
||||
#define HDMI_A_HDCPOBS1 HDMI_BASE_ADDR+0x5003
|
||||
#define HDMI_A_HDCPOBS2 HDMI_BASE_ADDR+0x5004
|
||||
#define HDMI_A_HDCPOBS3 HDMI_BASE_ADDR+0x5005
|
||||
#define HDMI_A_APIINTCLR HDMI_BASE_ADDR+0x5006
|
||||
#define HDMI_A_APIINTSTAT HDMI_BASE_ADDR+0x5007
|
||||
#define HDMI_A_APIINTMSK HDMI_BASE_ADDR+0x5008
|
||||
#define HDMI_A_VIDPOLCFG HDMI_BASE_ADDR+0x5009
|
||||
#define HDMI_A_OESSWCFG HDMI_BASE_ADDR+0x500A
|
||||
#define HDMI_A_TIMER1SETUP0 HDMI_BASE_ADDR+0x500B
|
||||
#define HDMI_A_TIMER1SETUP1 HDMI_BASE_ADDR+0x500C
|
||||
#define HDMI_A_TIMER2SETUP0 HDMI_BASE_ADDR+0x500D
|
||||
#define HDMI_A_TIMER2SETUP1 HDMI_BASE_ADDR+0x500E
|
||||
#define HDMI_A_100MSCFG HDMI_BASE_ADDR+0x500F
|
||||
#define HDMI_A_2SCFG0 HDMI_BASE_ADDR+0x5010
|
||||
#define HDMI_A_2SCFG1 HDMI_BASE_ADDR+0x5011
|
||||
#define HDMI_A_5SCFG0 HDMI_BASE_ADDR+0x5012
|
||||
#define HDMI_A_5SCFG1 HDMI_BASE_ADDR+0x5013
|
||||
#define HDMI_A_SRMVERLSB HDMI_BASE_ADDR+0x5014
|
||||
#define HDMI_A_SRMVERMSB HDMI_BASE_ADDR+0x5015
|
||||
#define HDMI_A_SRMCTRL HDMI_BASE_ADDR+0x5016
|
||||
#define HDMI_A_SFRSETUP HDMI_BASE_ADDR+0x5017
|
||||
#define HDMI_A_I2CHSETUP HDMI_BASE_ADDR+0x5018
|
||||
#define HDMI_A_INTSETUP HDMI_BASE_ADDR+0x5019
|
||||
#define HDMI_A_PRESETUP HDMI_BASE_ADDR+0x501A
|
||||
#define HDMI_A_SRM_BASE HDMI_BASE_ADDR+0x5020
|
||||
|
||||
// CEC Engine Registers
|
||||
#define HDMI_CEC_CTRL HDMI_BASE_ADDR+0x7D00
|
||||
#define HDMI_CEC_STAT HDMI_BASE_ADDR+0x7D01
|
||||
#define HDMI_CEC_MASK HDMI_BASE_ADDR+0x7D02
|
||||
#define HDMI_CEC_POLARITY HDMI_BASE_ADDR+0x7D03
|
||||
#define HDMI_CEC_INT HDMI_BASE_ADDR+0x7D04
|
||||
#define HDMI_CEC_ADDR_L HDMI_BASE_ADDR+0x7D05
|
||||
#define HDMI_CEC_ADDR_H HDMI_BASE_ADDR+0x7D06
|
||||
#define HDMI_CEC_TX_CNT HDMI_BASE_ADDR+0x7D07
|
||||
#define HDMI_CEC_RX_CNT HDMI_BASE_ADDR+0x7D08
|
||||
#define HDMI_CEC_TX_DATA0 HDMI_BASE_ADDR+0x7D10
|
||||
#define HDMI_CEC_TX_DATA1 HDMI_BASE_ADDR+0x7D11
|
||||
#define HDMI_CEC_TX_DATA2 HDMI_BASE_ADDR+0x7D12
|
||||
#define HDMI_CEC_TX_DATA3 HDMI_BASE_ADDR+0x7D13
|
||||
#define HDMI_CEC_TX_DATA4 HDMI_BASE_ADDR+0x7D14
|
||||
#define HDMI_CEC_TX_DATA5 HDMI_BASE_ADDR+0x7D15
|
||||
#define HDMI_CEC_TX_DATA6 HDMI_BASE_ADDR+0x7D16
|
||||
#define HDMI_CEC_TX_DATA7 HDMI_BASE_ADDR+0x7D17
|
||||
#define HDMI_CEC_TX_DATA8 HDMI_BASE_ADDR+0x7D18
|
||||
#define HDMI_CEC_TX_DATA9 HDMI_BASE_ADDR+0x7D19
|
||||
#define HDMI_CEC_TX_DATA10 HDMI_BASE_ADDR+0x7D1a
|
||||
#define HDMI_CEC_TX_DATA11 HDMI_BASE_ADDR+0x7D1b
|
||||
#define HDMI_CEC_TX_DATA12 HDMI_BASE_ADDR+0x7D1c
|
||||
#define HDMI_CEC_TX_DATA13 HDMI_BASE_ADDR+0x7D1d
|
||||
#define HDMI_CEC_TX_DATA14 HDMI_BASE_ADDR+0x7D1e
|
||||
#define HDMI_CEC_TX_DATA15 HDMI_BASE_ADDR+0x7D1f
|
||||
#define HDMI_CEC_RX_DATA0 HDMI_BASE_ADDR+0x7D20
|
||||
#define HDMI_CEC_RX_DATA1 HDMI_BASE_ADDR+0x7D21
|
||||
#define HDMI_CEC_RX_DATA2 HDMI_BASE_ADDR+0x7D22
|
||||
#define HDMI_CEC_RX_DATA3 HDMI_BASE_ADDR+0x7D23
|
||||
#define HDMI_CEC_RX_DATA4 HDMI_BASE_ADDR+0x7D24
|
||||
#define HDMI_CEC_RX_DATA5 HDMI_BASE_ADDR+0x7D25
|
||||
#define HDMI_CEC_RX_DATA6 HDMI_BASE_ADDR+0x7D26
|
||||
#define HDMI_CEC_RX_DATA7 HDMI_BASE_ADDR+0x7D27
|
||||
#define HDMI_CEC_RX_DATA8 HDMI_BASE_ADDR+0x7D28
|
||||
#define HDMI_CEC_RX_DATA9 HDMI_BASE_ADDR+0x7D29
|
||||
#define HDMI_CEC_RX_DATA10 HDMI_BASE_ADDR+0x7D2a
|
||||
#define HDMI_CEC_RX_DATA11 HDMI_BASE_ADDR+0x7D2b
|
||||
#define HDMI_CEC_RX_DATA12 HDMI_BASE_ADDR+0x7D2c
|
||||
#define HDMI_CEC_RX_DATA13 HDMI_BASE_ADDR+0x7D2d
|
||||
#define HDMI_CEC_RX_DATA14 HDMI_BASE_ADDR+0x7D2e
|
||||
#define HDMI_CEC_RX_DATA15 HDMI_BASE_ADDR+0x7D2f
|
||||
#define HDMI_CEC_LOCK HDMI_BASE_ADDR+0x7D30
|
||||
#define HDMI_CEC_WKUPCTRL HDMI_BASE_ADDR+0x7D31
|
||||
|
||||
// I2C Master Registers (E-DDC)
|
||||
#define HDMI_I2CM_SLAVE HDMI_BASE_ADDR+0x7E00
|
||||
#define HDMI_I2CMESS HDMI_BASE_ADDR+0x7E01
|
||||
#define HDMI_I2CM_DATAO HDMI_BASE_ADDR+0x7E02
|
||||
#define HDMI_I2CM_DATAI HDMI_BASE_ADDR+0x7E03
|
||||
#define HDMI_I2CM_OPERATION HDMI_BASE_ADDR+0x7E04
|
||||
#define HDMI_I2CM_INT HDMI_BASE_ADDR+0x7E05
|
||||
#define HDMI_I2CM_CTLINT HDMI_BASE_ADDR+0x7E06
|
||||
#define HDMI_I2CM_DIV HDMI_BASE_ADDR+0x7E07
|
||||
#define HDMI_I2CM_SEGADDR HDMI_BASE_ADDR+0x7E08
|
||||
#define HDMI_I2CM_SOFTRSTZ HDMI_BASE_ADDR+0x7E09
|
||||
#define HDMI_I2CM_SEGPTR HDMI_BASE_ADDR+0x7E0A
|
||||
#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR HDMI_BASE_ADDR+0x7E0B
|
||||
#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR HDMI_BASE_ADDR+0x7E0C
|
||||
#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR HDMI_BASE_ADDR+0x7E0D
|
||||
#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR HDMI_BASE_ADDR+0x7E0E
|
||||
#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR HDMI_BASE_ADDR+0x7E0F
|
||||
#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR HDMI_BASE_ADDR+0x7E10
|
||||
#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR HDMI_BASE_ADDR+0x7E11
|
||||
#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR HDMI_BASE_ADDR+0x7E12
|
||||
|
||||
// Random Number Generator Registers (RNG)
|
||||
#define HDMI_RNG_BASE HDMI_BASE_ADDR+0x8000
|
||||
|
||||
#endif //HDMI_COMMON_H
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file imx6q.h
|
||||
* @brief support imx6q arch define
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.09.08
|
||||
*/
|
||||
|
||||
#ifndef IMX6Q_H
|
||||
#define IMX6Q_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
#include <iomux_v3.h>
|
||||
#include <soc_memory_map.h>
|
||||
#include <regs_anadig.h>
|
||||
#include <regs_pins.h>
|
||||
#include <regsuart.h>
|
||||
#include <crm_regs.h>
|
||||
#include <registers.h>
|
||||
#include <arm_cp_registers.h>
|
||||
|
||||
#include <uart.h>
|
||||
|
||||
#define SNVS_LPGPR_OFFSET 0x68
|
||||
#define IOMUXC_GPR1_OFFSET 0x4
|
||||
|
||||
//! @name Instruction macros
|
||||
//@{
|
||||
#define _ARM_NOP() __asm__ volatile("nop\n\t")
|
||||
#define _ARM_WFI() __asm__ volatile("wfi\n\t")
|
||||
#define _ARM_WFE() __asm__ volatile("wfe\n\t")
|
||||
#define _ARM_SEV() __asm__ volatile("sev\n\t")
|
||||
#define _ARM_DSB() __asm__ volatile("dsb\n\t")
|
||||
#define _ARM_ISB() __asm__ volatile("isb\n\t")
|
||||
|
||||
#define _ARM_MRC(coproc, opcode1, Rt, CRn, CRm, opcode2) \
|
||||
__asm__ volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt))
|
||||
|
||||
#define _ARM_MCR(coproc, opcode1, Rt, CRn, CRm, opcode2) \
|
||||
__asm__ volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt))
|
||||
//@}
|
||||
|
||||
|
||||
#define WriteReg(value, address) (*(volatile unsigned int *)(address) = (value))
|
||||
#define ReadReg(address) (*(volatile unsigned int *)(address))
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -28,7 +28,6 @@
|
|||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
/*!
|
||||
* @file imx_uart.h
|
||||
* @brief various defines used by imx_uart.c
|
||||
|
|
@ -37,65 +36,66 @@
|
|||
#ifndef __IMX_UART_H__
|
||||
#define __IMX_UART_H__
|
||||
|
||||
#include "sdk.h"
|
||||
#include "stdint.h"
|
||||
|
||||
//! @addtogroup diag_uart
|
||||
//! @{
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//Constants
|
||||
// Constants
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/* UART specific defines */
|
||||
//! @brief Modes of the PARITY for UART transfer.
|
||||
enum _uart_parity
|
||||
{
|
||||
PARITY_NONE = 0, //!< PARITY mode is PARITY_NONE.
|
||||
PARITY_EVEN = 2, //!< PARITY mode is PARITY_EVEN.
|
||||
PARITY_ODD = 3 //!< PARITY mode is PARITY_ODD.
|
||||
enum _uart_parity {
|
||||
PARITY_NONE = 0, //!< PARITY mode is PARITY_NONE.
|
||||
PARITY_EVEN = 2, //!< PARITY mode is PARITY_EVEN.
|
||||
PARITY_ODD = 3 //!< PARITY mode is PARITY_ODD.
|
||||
};
|
||||
|
||||
//! @brief Number of stopbits after a character.
|
||||
enum _uart_stopbits
|
||||
{
|
||||
STOPBITS_ONE = 0, //!< One stopbits after a character.
|
||||
STOPBITS_TWO = 1 //!< Two stopbits after a character.
|
||||
enum _uart_stopbits {
|
||||
STOPBITS_ONE = 0, //!< One stopbits after a character.
|
||||
STOPBITS_TWO = 1 //!< Two stopbits after a character.
|
||||
};
|
||||
|
||||
//! @brief Flow control mode for UART transfer.
|
||||
enum _uart_flowctrl
|
||||
{
|
||||
FLOWCTRL_OFF = 0, //!< Flow control off for UART transfer.
|
||||
FLOWCTRL_ON = 1 //!< Flow control on for UART transfer.
|
||||
enum _uart_flowctrl {
|
||||
FLOWCTRL_OFF = 0, //!< Flow control off for UART transfer.
|
||||
FLOWCTRL_ON = 1 //!< Flow control on for UART transfer.
|
||||
};
|
||||
|
||||
//! @brief Specify the FIFO for UART transfer.
|
||||
enum _uart_fifo
|
||||
{
|
||||
TX_FIFO = 0, //!< Config the TX fifo for UART transfer.
|
||||
RX_FIFO = 1 //!< Config the RX fifo for UART transfer.
|
||||
};
|
||||
enum _uart_fifo {
|
||||
TX_FIFO = 0, //!< Config the TX fifo for UART transfer.
|
||||
RX_FIFO = 1 //!< Config the RX fifo for UART transfer.
|
||||
};
|
||||
|
||||
//! @brief Specify the number of bits in a data
|
||||
enum _uart_bits
|
||||
{
|
||||
SEVENBITS = 0, //!< Config seven bits in a data.
|
||||
EIGHTBITS = 1 //!< Config eight bits in a data.
|
||||
enum _uart_bits {
|
||||
SEVENBITS = 0, //!< Config seven bits in a data.
|
||||
EIGHTBITS = 1 //!< Config eight bits in a data.
|
||||
};
|
||||
|
||||
//! @brief Specify the service mode
|
||||
#define DMA_MODE 2 //!< Config the service mode for dma request.
|
||||
#define IRQ_MODE 1 //!< Config the service mode for interrupt.
|
||||
#define DMA_MODE 2 //!< Config the service mode for dma request.
|
||||
#define IRQ_MODE 1 //!< Config the service mode for interrupt.
|
||||
|
||||
#define UART_MODULE_CLK(x) ((x) == HW_UART1 ? UART1_MODULE_CLK : (x) == HW_UART2 ? UART2_MODULE_CLK : (x) == HW_UART3 ? UART3_MODULE_CLK : (x) == HW_UART4 ? UART4_MODULE_CLK : -1)
|
||||
#define UART_MODULE_CLK(x) ((x) == HW_UART1 ? UART1_MODULE_CLK : (x) == HW_UART2 ? UART2_MODULE_CLK \
|
||||
: (x) == HW_UART3 ? UART3_MODULE_CLK \
|
||||
: (x) == HW_UART4 ? UART4_MODULE_CLK \
|
||||
: -1)
|
||||
|
||||
#define UART_IRQS(x) ((x) == HW_UART1 ? IMX_INT_UART1 : (x) == HW_UART2 ? IMX_INT_UART2 : (x) == HW_UART3 ? IMX_INT_UART3 : (x) == HW_UART4 ? IMX_INT_UART4 : (x) == HW_UART5 ? IMX_INT_UART5 : 0xFFFFFFFF)
|
||||
#define UART_IRQS(x) ((x) == HW_UART1 ? IMX_INT_UART1 : (x) == HW_UART2 ? IMX_INT_UART2 \
|
||||
: (x) == HW_UART3 ? IMX_INT_UART3 \
|
||||
: (x) == HW_UART4 ? IMX_INT_UART4 \
|
||||
: (x) == HW_UART5 ? IMX_INT_UART5 \
|
||||
: 0xFFFFFFFF)
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//API
|
||||
// API
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Initialize the UART port
|
||||
*
|
||||
|
|
@ -109,7 +109,7 @@ enum _uart_bits
|
|||
* @param flowcontrol enable (RTS/CTS) hardware flow control:
|
||||
* FLOWCTRL_ON, FLOWCTRL_OFF.
|
||||
*/
|
||||
void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity,uint8_t stopbits, uint8_t datasize, uint8_t flowcontrol);
|
||||
void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity, uint8_t stopbits, uint8_t datasize, uint8_t flowcontrol);
|
||||
|
||||
/*!
|
||||
* @brief Output a character to UART port
|
||||
|
|
@ -118,7 +118,7 @@ void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity,uint8_t stop
|
|||
* @param ch pointer to the character for output
|
||||
* @return the character that has been sent
|
||||
*/
|
||||
uint8_t uart_putchar(uint32_t instance, uint8_t * ch);
|
||||
uint8_t uart_putchar(uint32_t instance, uint8_t* ch);
|
||||
|
||||
/*!
|
||||
* @brief Receive a character on the UART port
|
||||
|
|
@ -139,7 +139,7 @@ uint8_t uart_getchar(uint32_t instance);
|
|||
* @param service_mode FIFO served with DMA or IRQ or polling (default).
|
||||
*/
|
||||
void uart_set_FIFO_mode(uint32_t instance, uint8_t fifo, uint8_t trigger_level,
|
||||
uint8_t service_mode);
|
||||
uint8_t service_mode);
|
||||
|
||||
/*!
|
||||
* @brief Enables UART loopback test mode
|
||||
|
|
@ -157,8 +157,7 @@ void uart_set_loopback_mode(uint32_t instance, uint8_t state);
|
|||
* @param irq_subroutine the UART interrupt interrupt routine.
|
||||
* @param state ENABLE or DISABLE the interrupt.
|
||||
*/
|
||||
void uart_setup_interrupt(uint32_t instance, void (*irq_subroutine)(int vector, void *param), uint8_t state);
|
||||
|
||||
void uart_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), uint8_t state);
|
||||
|
||||
/*!
|
||||
* @brief Obtain UART reference frequency
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
|
||||
* Copyright (c) 2009-2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
|
|
@ -27,15 +27,34 @@
|
|||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef __INTERRUPT_H__
|
||||
#define __INTERRUPT_H__
|
||||
|
||||
#if !defined(__PRINT_CLOCK_INFO_H__)
|
||||
#define __PRINT_CLOCK_INFO_H__
|
||||
#include "irq_numbers.h"
|
||||
|
||||
#include "sdk.h"
|
||||
|
||||
//! @addtogroup app_common
|
||||
//! @addtogroup diag_interrupt
|
||||
//! @{
|
||||
|
||||
/*!
|
||||
* @file interrupt.h
|
||||
* @brief Interface for the interrupt manager.
|
||||
*/
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @brief
|
||||
typedef enum {
|
||||
CPU_0,
|
||||
CPU_1,
|
||||
CPU_2,
|
||||
CPU_3,
|
||||
} cpuid_e;
|
||||
|
||||
//! @brief Interrupt service routine.
|
||||
typedef void (*irq_hdlr_t)(void);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// API
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -44,17 +63,30 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
//! @brief Enable an interrupt.
|
||||
//!
|
||||
//! Sets the interrupt priority and makes it non-secure. Then the interrupt is
|
||||
//! enabled on the CPU specified by @a cpu_id.
|
||||
//!
|
||||
//! @param irq_id The interrupt number to enable.
|
||||
//! @param cpu_id The index of the CPU for which the interrupt will be enabled.
|
||||
//! @param priority The interrupt priority, from 0-255. Lower numbers have higher priority.
|
||||
void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority);
|
||||
|
||||
/*!
|
||||
* @brief Display module frequency
|
||||
*/
|
||||
void show_freq(void);
|
||||
//! @brief Disable an interrupt on the specified CPU.
|
||||
//!
|
||||
//! @param irq_id The interrupt number to disabled.
|
||||
//! @param cpu_id The index of the CPU for which the interrupt will be disabled.
|
||||
void disable_interrupt(uint32_t irq_id, uint32_t cpu_id);
|
||||
|
||||
/*!
|
||||
* @brief Display the board's DDR configuration
|
||||
*/
|
||||
void show_ddr_config(void);
|
||||
//! @brief Set the interrupt service routine for the specified interrupt.
|
||||
//!
|
||||
//! @param irq_id The interrupt number.
|
||||
//! @param isr Function that will be called to handle the interrupt.
|
||||
void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr);
|
||||
|
||||
//! @brief Interrupt handler that simply prints a message.
|
||||
void default_interrupt_routine(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
@ -62,7 +94,7 @@ void show_ddr_config(void);
|
|||
|
||||
//! @}
|
||||
|
||||
#endif // __PRINT_CLOCK_INFO_H__
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
|
||||
* <armlinux@phytec.de>
|
||||
*
|
||||
* Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file iomux_v3.h
|
||||
* @brief support imx6q iomux function define, reference from u-boot-2009-08/include/asm-arm/arch-mx6/iomux_v3.h
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.09.08
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __MACH_IOMUX_V3_H__
|
||||
#define __MACH_IOMUX_V3_H__
|
||||
|
||||
/*
|
||||
* build IOMUX_PAD structure
|
||||
*
|
||||
* This iomux scheme is based around pads, which are the physical balls
|
||||
* on the processor.
|
||||
*
|
||||
* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
|
||||
* things like driving strength and pullup/pulldown.
|
||||
* - Each pad can have but not necessarily does have an output routing register
|
||||
* (IOMUXC_SW_MUX_CTL_PAD_x).
|
||||
* - Each pad can have but not necessarily does have an input routing register
|
||||
* (IOMUXC_x_SELECT_INPUT)
|
||||
*
|
||||
* The three register sets do not have a fixed offset to each other,
|
||||
* hence we order this table by pad control registers (which all pads
|
||||
* have) and put the optional i/o routing registers into additional
|
||||
* fields.
|
||||
*
|
||||
* The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
|
||||
* If <padname> or <padmode> refers to a GPIO, it is named
|
||||
* GPIO_<unit>_<num>
|
||||
*
|
||||
* IOMUX/PAD Bit field definitions
|
||||
*
|
||||
* MUX_CTRL_OFS: 0..11 (12)
|
||||
* PAD_CTRL_OFS: 12..23 (12)
|
||||
* SEL_INPUT_OFS: 24..35 (12)
|
||||
* MUX_MODE + SION: 36..40 (5)
|
||||
* PAD_CTRL + NO_PAD_CTRL: 41..59 (19)
|
||||
* SEL_INP: 60..63 (4)
|
||||
*/
|
||||
|
||||
typedef uint64_t iomux_v3_cfg_t;
|
||||
typedef unsigned int iomux_pin_name_t;
|
||||
|
||||
#define MUX_CTRL_OFS_SHIFT 0
|
||||
#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
|
||||
#define MUX_PAD_CTRL_OFS_SHIFT 12
|
||||
#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
|
||||
MUX_PAD_CTRL_OFS_SHIFT)
|
||||
#define MUX_SEL_INPUT_OFS_SHIFT 24
|
||||
#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
|
||||
MUX_SEL_INPUT_OFS_SHIFT)
|
||||
|
||||
#define MUX_MODE_SHIFT 36
|
||||
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
|
||||
#define MUX_PAD_CTRL_SHIFT 41
|
||||
#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT)
|
||||
#define MUX_SEL_INPUT_SHIFT 60
|
||||
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
|
||||
|
||||
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
|
||||
|
||||
#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
|
||||
_sel_input, _pad_ctrl) \
|
||||
(((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_sel_input_ofs) << \
|
||||
MUX_SEL_INPUT_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
|
||||
|
||||
#if defined CONFIG_MX6Q
|
||||
#define MX6X_IOMUX(s) MX6Q_##s
|
||||
#elif defined CONFIG_MX6DL
|
||||
#define MX6X_IOMUX(s) MX6DL_##s
|
||||
#elif defined CONFIG_MX6SL
|
||||
#define MX6X_IOMUX(s) MX6SL_##s
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Use to set PAD control
|
||||
*/
|
||||
#define PAD_CTL_LVE_OFFSET (22)
|
||||
#define PAD_CTL_LVE (1 << 18)
|
||||
#define NO_PAD_CTRL (1 << 17)
|
||||
#define PAD_CTL_HYS (1 << 16)
|
||||
|
||||
#define NO_PAD_I 0
|
||||
#define NO_MUX_I 0
|
||||
#define IOMUX_CONFIG_SION (0x1 << 4)
|
||||
|
||||
#define PAD_CTL_PUS_100K_DOWN (0 << 14)
|
||||
#define PAD_CTL_PUS_47K_UP (1 << 14)
|
||||
#define PAD_CTL_PUS_100K_UP (2 << 14)
|
||||
#define PAD_CTL_PUS_22K_UP (3 << 14)
|
||||
|
||||
#define PAD_CTL_PUE (1 << 13)
|
||||
#define PAD_CTL_PKE (1 << 12)
|
||||
#define PAD_CTL_ODE (1 << 11)
|
||||
|
||||
#define PAD_CTL_SPEED_LOW (1 << 6)
|
||||
#define PAD_CTL_SPEED_MED (2 << 6)
|
||||
#define PAD_CTL_SPEED_HIGH (3 << 6)
|
||||
|
||||
#define PAD_CTL_DSE_DISABLE (0 << 3)
|
||||
#define PAD_CTL_DSE_240ohm (1 << 3)
|
||||
#define PAD_CTL_DSE_120ohm (2 << 3)
|
||||
#define PAD_CTL_DSE_80ohm (3 << 3)
|
||||
#define PAD_CTL_DSE_60ohm (4 << 3)
|
||||
#define PAD_CTL_DSE_48ohm (5 << 3)
|
||||
#define PAD_CTL_DSE_40ohm (6 << 3)
|
||||
#define PAD_CTL_DSE_34ohm (7 << 3)
|
||||
|
||||
#define PAD_CTL_SRE_FAST (1 << 0)
|
||||
#define PAD_CTL_SRE_SLOW (0 << 0)
|
||||
|
||||
#define GPIO_PIN_MASK 0x1f
|
||||
|
||||
#define GPIO_PORT_SHIFT 5
|
||||
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
|
||||
|
||||
/*
|
||||
* setups a single pad in the iomuxer
|
||||
*/
|
||||
int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
|
||||
|
||||
/*
|
||||
* setups mutliple pads
|
||||
* convenient way to call the above function with tables
|
||||
*/
|
||||
int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
|
||||
|
||||
/*
|
||||
* Set bits for general purpose registers
|
||||
*/
|
||||
void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value);
|
||||
|
||||
/*
|
||||
* Initialise the iomux controller
|
||||
*/
|
||||
void mxc_iomux_v3_init(void *iomux_v3_base);
|
||||
|
||||
#endif /* __MACH_IOMUX_V3_H__*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,229 @@
|
|||
/*
|
||||
* Copyright (c) 2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#if !defined(__IRQ_NUMBERS_H__)
|
||||
#define __IRQ_NUMBERS_H__
|
||||
|
||||
#define HW_NR_IRQS IMX_INTERRUPT_COUNT
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @brief i.MX6 interrupt numbers.
|
||||
//!
|
||||
//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series.
|
||||
//! Use these numbers when specifying an interrupt to the GIC.
|
||||
//!
|
||||
//! The first 16 interrupts are special in that they are reserved for software interrupts generated
|
||||
//! by the SWI instruction.
|
||||
enum _imx_interrupts {
|
||||
SW_INTERRUPT_0 = 0, //!< Software interrupt 0.
|
||||
SW_INTERRUPT_1 = 1, //!< Software interrupt 1.
|
||||
SW_INTERRUPT_2 = 2, //!< Software interrupt 2.
|
||||
SW_INTERRUPT_3 = 3, //!< Software interrupt 3.
|
||||
SW_INTERRUPT_4 = 4, //!< Software interrupt 4.
|
||||
SW_INTERRUPT_5 = 5, //!< Software interrupt 5.
|
||||
SW_INTERRUPT_6 = 6, //!< Software interrupt 6.
|
||||
SW_INTERRUPT_7 = 7, //!< Software interrupt 7.
|
||||
SW_INTERRUPT_8 = 8, //!< Software interrupt 8.
|
||||
SW_INTERRUPT_9 = 9, //!< Software interrupt 9.
|
||||
SW_INTERRUPT_10 = 10, //!< Software interrupt 10.
|
||||
SW_INTERRUPT_11 = 11, //!< Software interrupt 11.
|
||||
SW_INTERRUPT_12 = 12, //!< Software interrupt 12.
|
||||
SW_INTERRUPT_13 = 13, //!< Software interrupt 13.
|
||||
SW_INTERRUPT_14 = 14, //!< Software interrupt 14.
|
||||
SW_INTERRUPT_15 = 15, //!< Software interrupt 15.
|
||||
RSVD_INTERRUPT_16 = 16, //!< Reserved.
|
||||
RSVD_INTERRUPT_17 = 17, //!< Reserved.
|
||||
RSVD_INTERRUPT_18 = 18, //!< Reserved.
|
||||
RSVD_INTERRUPT_19 = 19, //!< Reserved.
|
||||
RSVD_INTERRUPT_20 = 20, //!< Reserved.
|
||||
RSVD_INTERRUPT_21 = 21, //!< Reserved.
|
||||
RSVD_INTERRUPT_22 = 22, //!< Reserved.
|
||||
RSVD_INTERRUPT_23 = 23, //!< Reserved.
|
||||
RSVD_INTERRUPT_24 = 24, //!< Reserved.
|
||||
RSVD_INTERRUPT_25 = 25, //!< Reserved.
|
||||
RSVD_INTERRUPT_26 = 26, //!< Reserved.
|
||||
RSVD_INTERRUPT_27 = 27, //!< Reserved.
|
||||
RSVD_INTERRUPT_28 = 28, //!< Reserved.
|
||||
RSVD_INTERRUPT_29 = 29, //!< Reserved.
|
||||
RSVD_INTERRUPT_30 = 30, //!< Reserved.
|
||||
RSVD_INTERRUPT_31 = 31, //!< Reserved.
|
||||
IMX_INT_IOMUXC_GPR = 32, //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot.
|
||||
IMX_INT_CHEETAH_CSYSPWRUPREQ = 33, //!< @todo Listed as DAP in RM
|
||||
IMX_INT_SDMA = 34, //!< Logical OR of all 48 SDMA interrupt requests/events from all channels.
|
||||
IMX_INT_VPU_JPG = 35, //!< JPEG codec interrupt request.
|
||||
IMX_INT_SNVS_LP_SET_PWR_OFF = 36, //!< PMIC power off request.
|
||||
IMX_INT_IPU1_ERR = 37, //!< IPU1 error interrupt request.
|
||||
IMX_INT_IPU1_FUNC = 38, //!< IPU1 sync interrupt request.
|
||||
IMX_INT_IPU2_ERR = 39, //!< IPU2 error interrupt request.
|
||||
IMX_INT_IPU2_FUNC = 40, //!< IPU2 sync interrupt request.
|
||||
IMX_INT_GPU3D = 41, //!< GPU3D interrupt request.
|
||||
IMX_INT_GPU2D = 42, //!< Idle interrupt from GPU2D (for S/W power gating).
|
||||
IMX_INT_OPENVG_XAQ2 = 43, //!< GPU2D general interrupt request.
|
||||
IMX_INT_VPU_IPI = 44, //!< VPU interrupt request.
|
||||
IMX_INT_APBHDMA = 45, //!< Logical OR of 4 signals: dma_chan[0-3]_irq, GPMI operation channel description complete interrupt.
|
||||
IMX_INT_EIM = 46, //!< EIM interrupt request.
|
||||
IMX_INT_BCH = 47, //!< BCH operation complete interrupt.
|
||||
IMX_INT_GPMI = 48, //!< GPMI operation timeout error interrupt.
|
||||
IMX_INT_DTCP = 49, //!< DTCP interrupt request.
|
||||
IMX_INT_VDOA = 50, //!< Logical OR of VDOA interrupt requests.
|
||||
IMX_INT_SNVS = 51, //!< SNVS consolidated interrupt.
|
||||
IMX_INT_SNVS_SEC = 52, //!< SNVS security interrupt.
|
||||
IMX_INT_CSU = 53, //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted.
|
||||
IMX_INT_USDHC1 = 54, //!< uSDHC1 (Enhanced SDHC) interrupt request.
|
||||
IMX_INT_USDHC2 = 55, //!< uSDHC2 (Enhanced SDHC) interrupt request.
|
||||
IMX_INT_USDHC3 = 56, //!< uSDHC3 (Enhanced SDHC) interrupt request.
|
||||
IMX_INT_USDHC4 = 57, //!< uSDHC4 (Enhanced SDHC) interrupt request.
|
||||
IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests.
|
||||
IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests.
|
||||
IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests.
|
||||
IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests.
|
||||
IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests.
|
||||
IMX_INT_ECSPI1 = 63, //!< eCSPI1 interrupt request.
|
||||
IMX_INT_ECSPI2 = 64, //!< eCSPI2 interrupt request.
|
||||
IMX_INT_ECSPI3 = 65, //!< eCSPI3 interrupt request.
|
||||
IMX_INT_ECSPI4 = 66, //!< eCSPI4 interrupt request.
|
||||
IMX_INT_ECSPI5 = 67, //!< eCSPI5 interrupt request.
|
||||
IMX_INT_I2C1 = 68, //!< I2C1 interrupt request.
|
||||
IMX_INT_I2C2 = 69, //!< I2C2 interrupt request.
|
||||
IMX_INT_I2C3 = 70, //!< I2C3 interrupt request.
|
||||
IMX_INT_SATA = 71, //!< SATA interrupt request.
|
||||
IMX_INT_USBOH3_UH1 = 72, //!< USB Host 1 interrupt request.
|
||||
IMX_INT_USBOH3_UH2 = 73, //!< USB Host 2 interrupt request.
|
||||
IMX_INT_USBOH3_UH3 = 74, //!< USB Host 3 interrupt request.
|
||||
IMX_INT_USBOH3_UOTG = 75, //!< USB OTG interrupt request.
|
||||
IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request.
|
||||
IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request.
|
||||
IMX_INT_SSI1 = 78, //!< SSI1 interrupt request.
|
||||
IMX_INT_SSI2 = 79, //!< SSI2 interrupt request.
|
||||
IMX_INT_SSI3 = 80, //!< SSI3 interrupt request.
|
||||
IMX_INT_TEMPERATURE = 81, //!< Temperature Sensor (temp. greater than threshold) interrupt request.
|
||||
IMX_INT_ASRC = 82, //!< ASRC interrupt request.
|
||||
IMX_INT_ESAI = 83, //!< ESAI interrupt request.
|
||||
IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts.
|
||||
IMX_INT_MLB = 85, //!< MLB error interrupt request.
|
||||
IMX_INT_PMU_ANA_BO = 86, //!< PMU analog regulator brown-out interrupt request.
|
||||
IMX_INT_GPT = 87, //!< Logical OR of GPT rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines.
|
||||
IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt.
|
||||
IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt.
|
||||
IMX_INT_GPIO1_INT7 = 90, //!< INT7 interrupt request.
|
||||
IMX_INT_GPIO1_INT6 = 91, //!< INT6 interrupt request.
|
||||
IMX_INT_GPIO1_INT5 = 92, //!< INT5 interrupt request.
|
||||
IMX_INT_GPIO1_INT4 = 93, //!< INT4 interrupt request.
|
||||
IMX_INT_GPIO1_INT3 = 94, //!< INT3 interrupt request.
|
||||
IMX_INT_GPIO1_INT2 = 95, //!< INT2 interrupt request.
|
||||
IMX_INT_GPIO1_INT1 = 96, //!< INT1 interrupt request.
|
||||
IMX_INT_GPIO1_INT0 = 97, //!< INT0 interrupt request.
|
||||
IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15.
|
||||
IMX_INT_GPIO1_INT31_16 = 99, //!< Combined interrupt indication for GPIO1 signals 16 - 31.
|
||||
IMX_INT_GPIO2_INT15_0 = 100, //!< Combined interrupt indication for GPIO2 signals 0 - 15.
|
||||
IMX_INT_GPIO2_INT31_16 = 101, //!< Combined interrupt indication for GPIO2 signals 16 - 31.
|
||||
IMX_INT_GPIO3_INT15_0 = 102, //!< Combined interrupt indication for GPIO3 signals 0 - 15.
|
||||
IMX_INT_GPIO3_INT31_16 = 103, //!< Combined interrupt indication for GPIO3 signals 16 - 31.
|
||||
IMX_INT_GPIO4_INT15_0 = 104, //!< Combined interrupt indication for GPIO4 signals 0 - 15.
|
||||
IMX_INT_GPIO4_INT31_16 = 105, //!< Combined interrupt indication for GPIO4 signals 16 - 31.
|
||||
IMX_INT_GPIO5_INT15_0 = 106, //!< Combined interrupt indication for GPIO5 signals 0 - 15.
|
||||
IMX_INT_GPIO5_INT31_16 = 107, //!< Combined interrupt indication for GPIO5 signals 16 - 31.
|
||||
IMX_INT_GPIO6_INT15_0 = 108, //!< Combined interrupt indication for GPIO6 signals 0 - 15.
|
||||
IMX_INT_GPIO6_INT31_16 = 109, //!< Combined interrupt indication for GPIO6 signals 16 - 31.
|
||||
IMX_INT_GPIO7_INT15_0 = 110, //!< Combined interrupt indication for GPIO7 signals 0 - 15.
|
||||
IMX_INT_GPIO7_INT31_16 = 111, //!< Combined interrupt indication for GPIO7 signals 16 - 31.
|
||||
IMX_INT_WDOG1 = 112, //!< WDOG1 timer reset interrupt request.
|
||||
IMX_INT_WDOG2 = 113, //!< WDOG2 timer reset interrupt request.
|
||||
IMX_INT_KPP = 114, //!< Key Pad interrupt request.
|
||||
IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
|
||||
IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
|
||||
IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
|
||||
IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
|
||||
IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1.
|
||||
IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2.
|
||||
IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1.
|
||||
IMX_INT_GPC_INT2 = 122, //!< GPC interrupt request 2.
|
||||
IMX_INT_SRC = 123, //!< SRC interrupt request.
|
||||
IMX_INT_CHEETAH_L2 = 124, //!< Logical OR of all L2 interrupt requests.
|
||||
IMX_INT_CHEETAH_PARITY = 125, //!< Parity Check error interrupt request.
|
||||
IMX_INT_CHEETAH_PERFORM = 126, //!< Logical OR of Performance Unit interrupts.
|
||||
IMX_INT_CHEETAH_TRIGGER = 127, //!< Logical OR of CTI trigger outputs.
|
||||
IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC.
|
||||
IMX_INT_INTERRUPT_129 = 129, //!< Reserved.
|
||||
IMX_INT_INTERRUPT_130 = 130, //!< Reserved.
|
||||
IMX_INT_INTERRUPT_131 = 131, //!< Reserved.
|
||||
IMX_INT_CSI_INTR1 = 132, //!< MIPI CSI interrupt request 1.
|
||||
IMX_INT_CSI_INTR2 = 133, //!< MIPI CSI interrupt request 2.
|
||||
IMX_INT_DSI = 134, //!< MIPI DSI interrupt request.
|
||||
IMX_INT_HSI = 135, //!< MIPI HSI interrupt request.
|
||||
IMX_INT_SJC = 136, //!< SJC interrupt from General Purpose register.
|
||||
IMX_INT_CAAM_INT0 = 137, //!< CAAM job ring 0 interrupt.
|
||||
IMX_INT_CAAM_INT1 = 138, //!< CAAM job ring 1 interrupt.
|
||||
IMX_INT_INTERRUPT_139 = 139, //!< Reserved.
|
||||
IMX_INT_TZASC1 = 140, //!< ASC1 interrupt request.
|
||||
IMX_INT_TZASC2 = 141, //!< ASC2 interrupt request.
|
||||
IMX_INT_FLEXCAN1 = 142, //!< FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein.
|
||||
IMX_INT_FLEXCAN2 = 143, //!< FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein.
|
||||
IMX_INT_PERFMON1 = 144, //!< Reserved.
|
||||
IMX_INT_PERFMON2 = 145, //!< Reserved.
|
||||
IMX_INT_PERFMON3 = 146, //!< Reserved.
|
||||
IMX_INT_HDMI_TX = 147, //!< HDMI master interrupt request.
|
||||
IMX_INT_HDMI_TX_WAKEUP = 148, //!< HDMI CEC engine dedicated interrupt signal raised by a wake-up event.
|
||||
IMX_INT_MLB_AHB0 = 149, //!< Channels [31:0] interrupt requests.
|
||||
IMX_INT_ENET = 150, //!< MAC 0 IRQ, Logical OR of:
|
||||
//! - MAC 0 Periodic Timer Overflow
|
||||
//! - MAC 0 Time Stamp Available
|
||||
//! - MAC 0 Payload Receive Error
|
||||
//! - MAC 0 Transmit FIFO Underrun
|
||||
//! - MAC 0 Collision Retry Limit
|
||||
//! - MAC 0 Late Collision
|
||||
//! - MAC 0 Ethernet Bus Error
|
||||
//! - MAC 0 MII Data Transfer Done
|
||||
//! - MAC 0 Receive Buffer Done
|
||||
//! - MAC 0 Receive Frame Done
|
||||
//! - MAC 0 Transmit Buffer Done
|
||||
//! - MAC 0 Transmit Frame Done
|
||||
//! - MAC 0 Graceful Stop
|
||||
//! - MAC 0 Babbling Transmit Error
|
||||
//! - MAC 0 Babbling Receive Error
|
||||
//! - MAC 0 Wakeup Request [synchronous]
|
||||
IMX_INT_ENET_1588 = 151, //!< MAC 0 1588 Timer interrupt [synchronous] request.
|
||||
IMX_INT_PCIE_1 = 152, //!< PCIe interrupt request 1.
|
||||
IMX_INT_PCIE_2 = 153, //!< PCIe interrupt request 2.
|
||||
IMX_INT_PCIE_3 = 154, //!< PCIe interrupt request 3.
|
||||
IMX_INT_PCIE_4 = 155, //!< PCIe interrupt request 4.
|
||||
IMX_INT_DCIC1 = 156, //!< Logical OR of DCIC1 interrupt requests.
|
||||
IMX_INT_DCIC2 = 157, //!< Logical OR of DCIC2 interrupt requests.
|
||||
IMX_INT_MLB_AHB1 = 158, //!< Logical OR of channel[63:32] interrupt requests.
|
||||
IMX_INT_PMU_DIG_BO = 159, //!< //!< PMU digital regulator brown-out interrupt request.
|
||||
IMX_INTERRUPT_COUNT = 160 //!< Total number of interrupts.
|
||||
};
|
||||
|
||||
#endif // __IRQ_NUMBERS_H__
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
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Reference in New Issue